DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/18/26 has been entered.
Response to Amendment
Upon further consideration, the previous indication that dependent claim 17 possessed allowable subject matter has been withdrawn, and new grounds of rejection have been presented below against amended claim 12 which incorporates the limitations from dependent claim 17.
Response to Arguments
Applicant’s arguments, dated 8/18/2026, with respect to claims 1 and 18 have been fully considered and are persuasive. The amendments have placed claims 1 and 18 in condition for allowance.
Applicant's arguments filed 8/18/2026 with respect to claim 12 have been fully considered but they are not persuasive. Examiner believes the indication of allowable subject matter for claim 17 in the office action dated 3/9/2026 was in error and a rejection of the claim limitations of the formerly dependent claim, now incorporated into independent claim 12, have been presented below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yung (US 2018/0284830) in view of Wang (US 2010/0019746).
With respect to claim 12, Yung discloses a voltage regulator (Fig. 2 204) configured to generate an output voltage (Fig. 2 226), comprising: an error amplifier circuit (Fig. 2 214) configured to generate a gate voltage (Fig. 2 224) based on a first reference voltage level (Fig. 2 202) and a first voltage level (Fig. 218 feeds back output voltage) of a first end of a target circuit (Fig. 2 228), and at least one pass transistor (Fig. 2 208) configured to generate the output voltage in response to the gate voltage, wherein the first end of the target circuit (Fig. 2 228) is connected to the at least one pass transistor through a circuit line (Fig. 2 216); a feedback circuit (Fig. 6-1 R1,R2) connected between the first end of the target circuit and the error amplifier circuit and configured to generate a third voltage level (Fig. 6-1 voltage 402) based on the first voltage level (Fig. 6-1 voltage 216) and to provide the third voltage level to the error amplifier circuit (Fig. 6-1 receives 402 at 212), wherein the error amplifier circuit is configured to generate (Fig. 6-1 608 depends on 402) the gate voltage based on the third voltage level (Fig. 6-1 402), and wherein the operating voltage of the target circuit (Fig. 6-1 voltage 216) is greater than (Fig. 6-1 potential at 402 is divided from voltage 216) a potential difference between the third voltage level (Fig. 3 voltage at 45-46-12) and the second voltage level (Fig. 6-1 ground), and wherein the feedback circuit includes: a first resistor (Fig. 6-1 R1) connected between (i) a feedback node (Fig. 6-1 402) connected (Fig. 6-1 212) to the error amplifier circuit and (ii) a ground node (Fig. 6-1 ground symbol); and a second resistor (Fig. 6-1 R2) connected between the feedback node and the first end of the target circuit. Yung discloses a common ground (Fig. 2 220) for the second reference voltage level and the second voltage level, and does not require a separate second reference voltage level from the second voltage level of a second end of the target circuit.
Wang discloses an error amplifier circuit (Fig. 3 1) comprising: a first differential pair (Fig. 2 26,15) comprising: a first input terminal (Fig. 3 22) configured to receive a first reference voltage level (Fig. 3 Vref- from reference ground), and a second input terminal (Fig. 3 11) configured to receive a first voltage level (Fig. 3 Vref+) of a first end of a target circuit, and a second differential pair (Fig. 2 16,25) comprising: a third input terminal (Fig. 3 12) configured to receive a second reference voltage level (Fig. 3 Vout+ divided by 45-46), and a fourth input terminal (Fig. 3 21) configured to receive a second voltage level (Fig. 3 Vout- load return) of a second end of the target circuit; wherein the error amplifier circuit is configured to generate the gate voltage (Fig. 3 gate 42) based on a first potential difference (Fig. 2 potential 11-22) of the first differential pair and a second potential difference (Fig. 2 potential 12-21) of the second differential pair; at least one power transistor (Fig. 3 42) configured to generate the output volage in response to the gate voltage (Fig. 3 gate voltage 42), wherein the first end (Fig. 3 end 51-52) of the target circuit is connected to the at least one power transistor through a circuit line (Fig 3 52),
wherein a potential difference (Fig. 3 11-22) between the first reference voltage level and the second reference level is a reference voltage (paragraph 45), and wherein a second potential difference (Fig. 2 potential 12-21) between (Fig. 3 output voltage across load 51 plus stray resistance voltage driven to reference voltage) the first voltage level and the second voltage level is an operating voltage of the target circuit (Fig. 3 output voltage – ground); and a feedback circuit (Fig. 3 45-46) connected between the first end of the target circuit and the error amplifier circuit and configured to generate a third voltage level (Fig. 3 voltage at node 45-46) based on the first voltage level and to provide the third voltage level to the error amplifier circuit, wherein the error amplifier circuit is configured to generate the gate voltage based on the third voltage level (Fig. 2 voltage at 12), and wherein the operating voltage of the target circuit (Fig. 3 voltage 51) is greater than (since Fig. 3 potential at 45-46 is a divided operating voltage) a potential difference between the third voltage level (Fig. 3 voltage at 45-46-12) and the second voltage level (Fig. 3 voltage at 12).wherein the feedback circuit includes: a first resistor (Fig. 3 46) connected between (i) a feedback node (Fig. 3 node 45-46) connected to the error amplifier circuit and (ii) a ground node (Fig. 3 ground); and a second resistor (Fig. 3 45) connected between the feedback node and the first end of the target circuit. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement an error amplifier circuit comprising: a first differential pair comprising: a first input terminal configured to receive a first reference voltage level, and a second input terminal configured to receive a second reference voltage level, and a second differential pair comprising: a third input terminal configured to receive a first voltage level of a first end of a target circuit, and a fourth input terminal configured to receive a second voltage level of a second end of the target circuit, wherein the error amplifier circuit is configured to generate a gate voltage based on a first potential difference of the first differential pair and a second potential difference of the second differential pair; and at least one pass transistor configured to generate the output voltage in response to the gate voltage, wherein the first end of the target circuit is connected to the at least one pass transistor through a circuit line, wherein the first potential difference is between the first reference voltage level and the second reference voltage level and is a reference voltage, and wherein the second potential difference is between the first voltage level and the second voltage level and is an operating voltage of the target circuit, in order to account for the voltage drop due to the wiring from the load to the error amplifier.
With respect to claim 13, Yung in view of Wang make obvious the voltage regulator of claim 12, wherein the output voltage (Fig. 3 voltage across 47 to ground) is greater (Fig. 3 greater by the voltage drops across conductors 52 and 53) than the operating voltage (Fig. 3 voltage across 51).
With respect to claim 14, Yung in view of Wang make obvious the voltage regulator of claim 12, wherein the operating voltage matches (Fig. 3 output voltage driven to reference voltage) the reference voltage (Fig. 3 voltage from 48 to ground).
Allowable Subject Matter
Claims 1-8, 10-11 and 18-20 are allowed, while Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. See the action dated 7/1/2026 for the reasons for the indication of allowable subject matter in claim 17. The following is an examiner’s statement of reasons for allowance:
With respect to claim 1, the prior art does not disclose or suggest, primarily, wherein the error amplifier circuit includes: a first transistor connected between a first node and a third node and configured to operate in response to the first reference voltage level; a second transistor connected between a second node and a fourth node and configured to operate in response to the second reference voltage level; a third transistor connected between the first node and a fifth node and configured to operate in response to the first voltage level; a fourth transistor connected between the second node and a sixth node and configured to operate in response to the second voltage level; a fifth transistor connected between a power node and the third node and configured to operate in response to a bias voltage; a sixth transistor connected between the power node and the fourth node and configured to operate in response to the bias voltage; a seventh transistor connected between the power node and the fifth node and configured to operate in response to the bias voltage; an eighth transistor connected between the power node and the sixth node and configured to operate in response to the bias voltage; and an output stage circuit configured to generate the gate voltage based on a first signal at the first node and a second signal at the second node.
With respect to claim 18, the prior art does not disclose or suggest, primarily, first ends of target circuits included in each of the plurality of electronic devices, a first switch circuit connected between first ends of the target circuits and the error amplifier circuit and configured to select one or more of the target circuits to be connected to the error amplifier circuit through the first switch circuit; and a second switch circuit connected between second ends of the target circuits and the error amplifier circuit and configured to select one or more of the target circuits to be connected to the error amplifier circuit through the second switch circuit, wherein a voltage level of a third node at which the error amplifier circuit and the first switch circuit are connected matches the first voltage level, and wherein a voltage level of a fourth node where the error amplifier circuit and the second switch circuit are connected matches the second voltage level.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tao (US 2021/0344271) discloses an error amplifier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
