DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/5/2026 have been fully considered but they are not persuasive. Applicant has not interpreted how the claims read on the secondary reference Wang in the same way as how the claims read upon Applicant’s own disclosure. Examiner reminds Applicant that the claims are interpreted in light of the specification. Applicant argues the first differential pair of Wang corresponds to 11 and 12, while the second differential pair corresponds to 21 and 22, which is incorrect. The first differential pair of Wang is 22 and 11, while the second differential pair is 12 and 21. Such an interpretation is consistent with Applicant’s disclosure. Examiner refers Applicant to their Figures 2 and 3, where the first differential pair is VL1 and VL2 which form the reference voltage VREF as shown in Figure 2, and the second differential pair is VL3 and VL4, which form the target voltage V1. As can be seen in Figure 3, VL1 and VL2 form the claimed first differential pair and VL3 and VL4 form the claimed second differential pair. The structure in Wang corresponds to the structure of Applicant with Vref- corresponding to VL1/22; Vref+ as VL2/11; Vout+ as VL3/12 and Vout- as VL4/21. Applicant’s differential pairs in Applicant’s Figure 3 are not VL4-VL1 and VL2-VL3 and Applicant cannot properly construe 11-12 and 21-22 of Wang as the differential pairs. When properly interpreted, Wang does teach the recited features in the rejection of amended claim 1 and the two ends of the target circuit are from the same differential pair. The rejections under Yung in view of Wang have been maintained below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-8, 12-14, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yung (US 2018/0284830) in view of Wang (US 2010/0019746).
With respect to claim 1, Yung discloses a voltage regulator (Fig. 2 204) comprising: at least one pass transistor (Fig. 2 208 or Fig. 7-1 T11) configured to generate an output voltage (Fig. 2 226) based on a gate voltage (Fig. 2 voltage 214); and an error amplifier circuit (Fig. 2 206) configured to output the gate voltage, wherein the error amplifier circuit includes: a first input terminal (Fig. 2 210) configured to receive a first reference voltage level from a reference voltage generator (Fig. 2 202); a third input terminal configured to receive a first voltage level (Fig. 2 218) of a first end of a target circuit (Fig. 2 228); and an output terminal (Fig. 2 214), wherein the error amplifier circuit is configured to generate the gate voltage based on the first reference voltage level, the second reference voltage level, the first voltage level, and the second voltage level, and to output the gate voltage at the output terminal, and wherein a potential difference between the first voltage level and the second voltage level is an operating voltage (Fig. 2 226) of the target circuit. Yung discloses wherein the reference voltage and load share a common ground (Fig. 2 220) and does not disclose wherein the error amplifier receives
a second input terminal configured to receive a second reference voltage level from the reference voltage generator and a fourth input terminal configured to receive a second voltage level of a second end of the target circuit.
Wang discloses a voltage regulator with an error amplifier circuit (Fig. 3 1) configured to output the gate voltage (Fig. 3 voltage 33), wherein the error amplifier circuit includes: a first differential pair (Fig. 3 22,11) comprising: a first input terminal (Fig. 3 22) configured to receive a first reference voltage level (Fig. 3 Vref- from reference ground) from a reference voltage generator (Fig. 3 48 return); a second input terminal (Fig. 3 11) configured to receive a second reference voltage level (Fig. 3 Vref+) from the reference voltage generator; a second differential pair (Fig. 2 12,21) comprising: a third input terminal (Fig. 3 12) configured to receive a first voltage level (Fig. 3 Vout+ divided by 45-46) of a first end of a target circuit (Fig. 3 51), and a fourth input terminal (Fig. 3 21) configured to receive a second voltage level (Fig. 3 Vout- load return) of a second end of the target circuit; and an output terminal (Fig. 3 33), wherein the error amplifier circuit is configured to generate the gate voltage (Fig. 3 gate 42) based on
a first potential difference (Fig. 2 potential 11-22) of the first differential pair and a second potential difference (Fig. 2 potential 12-21) of the second differential pair, and to output the gate voltage at the output terminal, and wherein the second potential difference (Fig. 2 potential 12-21) is between (Fig. 3 output voltage across load 51 plus stray resistance voltage driven to reference voltage) the first voltage level and the second voltage level and is an operating voltage of the target circuit (Fig. 3 output voltage – ground). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement an error amplifier circuit configured to output the gate voltage, wherein the error amplifier circuit includes: a first differential pair comprising: a first input terminal configured to receive a first reference voltage level from a reference voltage generator; a second input terminal configured to receive a second reference voltage level from the reference voltage generator; a second differential pair comprising: a third input terminal configured to receive a first voltage level of a first end of a target circuit, and a fourth input terminal configured to receive a second voltage level of a second end of the target circuit; and an output terminal, wherein the error amplifier circuit is configured to generate the gate voltage based on a first potential difference of the first differential pair and a second potential difference of the second differential pair, and to output the gate voltage at the output terminal, and wherein the second potential difference is between the first voltage level and is the second voltage level is an operating voltage of the target circuit, in order to account for the voltage drop due to the wiring from the load to the error amplifier.
With respect to claim 2, Yung in view of Wang make obvious the voltage regulator of claim 1, wherein the operating voltage (Fig. 3 voltage across 51) of the target circuit is smaller (Fig. 3 smaller by voltage drop across 52 and 51) than the output voltage (Fig. 3 voltage at 47).
With respect to claim 3, Yung in view of Wang make obvious the voltage regulator of claim 1, wherein the first potential difference is between the first reference voltage level (Fig. 3 22) and the second reference voltage level (Fig. 3 11) is a reference voltage (Wang paragraph 45).
With respect to claim 4, Yung in view of Wang make obvious the voltage regulator of claim 3, wherein the operating voltage matches the reference voltage (Wang Fig. 2 drives the operating voltage at the load to the reference voltage).
With respect to claim 5, Yung in view of Wang make obvious the voltage regulator of claim 1, wherein the error amplifier circuit is configured to: sum (Wang Fig. 2 32 sums 14 and 24) signals based on the first reference voltage level (Fig. 2 22) and the first voltage level (Fig. 2 12), respectively, to obtain a first signal (Fig. 2 32); sum (Wang Fig. 2 31) signals based on the second reference voltage level (Fig. 2 11) and the second voltage level (Fig. 2 21), respectively, to obtain a second signal (Fig. 2 31); compare (Fig. 2 34-36) the first signal and the second signal, to obtain a comparison result (Fig. 2 33); and generate the gate voltage (Fig. 2 gate 42) based on the comparison result.
With respect to claim 7, Yung in view of Wang make obvious the voltage regulator of claim 1, wherein the at least one pass transistor includes: a first transistor (Fig. 7-1 T11) connected between a first node (Fig. 7-1 216) and a second node (Fig. 7-1 708) and configured to operate in response to the gate voltage (Fig. 7-1 224); a second transistor (Fig. 7-1 T20) including a gate connected (Fig. 7-1 connected through T15,T16,T22,T12) to the second node and connected between the first node and a power node (Fig. 7-1 Vin); and a third transistor (Fig. 7-1 T21) connected between the second node and a ground node (Fig. 7-1 ground symbol)and configured to operate in response to a bias voltage (Fig. 7-1 voltage 708), and wherein the first node and the target circuit are connected through a circuit line (Fig. 7-1 line to 226).
With respect to claim 8, Yung in view of Wang make obvious the voltage regulator of claim 1, wherein the at least one pass transistor includes a p-type metal-oxide-semiconductor field-effect-transistor (Fig. 7-1 T11) connected to an output node (Fig. 7-1 216) and configured to operate in response to the gate voltage, and wherein the output node is connected to the first end of the target circuit through a circuit line (Fig. 7-1 line to 226).
With respect to claim 12, Yung discloses a voltage regulator (Fig. 2 104) configured to generate an output voltage (Fig. 2 226), comprising: an error amplifier circuit (Fig. 2 214) configured to generate a gate voltage (Fig. 2 224) based on a first reference voltage level (Fig. 2 202) and a first voltage level (Fig. 218 feeds back output voltage) of a first end of a target circuit (Fig. 2 228), and at least one pass transistor (Fig. 2 208) configured to generate the output voltage in response to the gate voltage, wherein the first end of the target circuit (Fig. 2 228) is connected to the at least one pass transistor through a circuit line (Fig. 2 216). Yung discloses a common ground (Fig. 2 220) for the second reference voltage level and the second voltage level, and does not require a separate second reference voltage level from the second voltage level of a second end of the target circuit.
Wang discloses an error amplifier circuit (Fig. 3 1) comprising: a first differential pair (Fig. 3 22,11) comprising: a first input terminal (Fig. 3 22) configured to receive a first reference voltage level (Fig. 3 Vref- from reference ground) from a reference voltage generator (Fig. 3 48 return); a second input terminal (Fig. 3 11) configured to receive a second reference voltage level (Fig. 3 Vref+), and a second differential pair (Fig. 2 12,21) comprising: a third input terminal (Fig. 3 12) configured to receive a first voltage level (Fig. 3 Vout+ divided by 45-46) of a first end of a target circuit (Fig. 3 51), and a fourth input terminal (Fig. 3 21) configured to receive a second voltage level (Fig. 3 Vout- load return) of a second end of the target circuit; wherein the error amplifier circuit is configured to generate the gate voltage (Fig. 3 gate 42) based on a first potential difference (Fig. 2 potential 11-22) of the first differential pair and a second potential difference (Fig. 2 potential 12-21) of the second differential pair; at least one power transistor (Fig. 3 42) configured to generate the output volage in response to the gate voltage (Fig. 3 gate voltage 42), wherein the first end (Fig. 3 end 51-52) of the target circuit is connected to the at least one power transistor through a circuit line (Fig 3 52),
wherein the first potential difference (Fig. 3 11-22) is between the first reference voltage level and the second reference level and is a reference voltage (paragraph 45), and wherein the second potential difference (Fig. 2 potential 12-21) is between (Fig. 3 output voltage across load 51 plus stray resistance voltage driven to reference voltage) the first voltage level and the second voltage level and is an operating voltage of the target circuit (Fig. 3 output voltage – ground). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement an error amplifier circuit comprising: a first differential pair comprising: a first input terminal configured to receive a first reference voltage level, and a second input terminal configured to receive a second reference voltage level, and a second differential pair comprising: a third input terminal configured to receive a first voltage level of a first end of a target circuit, and a fourth input terminal configured to receive a second voltage level of a second end of the target circuit, wherein the error amplifier circuit is configured to generate a gate voltage based on a first potential difference of the first differential pair and a second potential difference of the second differential pair; and at least one pass transistor configured to generate the output voltage in response to the gate voltage, wherein the first end of the target circuit is connected to the at least one pass transistor through a circuit line, wherein the first potential difference is between the first reference voltage level and the second reference voltage level and is a reference voltage, and wherein the second potential difference is between the first voltage level and the second voltage level and is an operating voltage of the target circuit, in order to account for the voltage drop due to the wiring from the load to the error amplifier.
With respect to claim 13, Yung in view of Wang make obvious the voltage regulator of claim 12, wherein the output voltage (Fig. 3 voltage across 47 to ground) is greater (Fig. 3 greater by the voltage drops across conductors 52 and 53) than the operating voltage (Fig. 3 voltage across 51).
With respect to claim 14, Yung in view of Wang make obvious the voltage regulator of claim 12, wherein the operating voltage matches (Fig. 3 output voltage driven to reference voltage) the reference voltage (Fig. 3 voltage from 48 to ground).
With respect to claim 16, Yung in view of Wang make obvious the voltage regulator of claim 12, further comprising: a feedback circuit (Yung Fig. 6-1 R1,R2; Wang Fig. 3 45-46) connected between the first end of the target circuit and the error amplifier circuit and configured to generate a third voltage level (Fig. 6-1 voltage 402) based on the first voltage level and to provide the third voltage level to the error amplifier circuit, wherein the error amplifier circuit is configured to generate the gate voltage based on the third voltage level (Wang Fig. 2 12), and wherein the operating voltage of the target circuit (Wang Fig. 3 voltage 51) is greater than (since Fig. 3 potential at 45-46 is a divided operating voltage) a potential difference between the third voltage level (Fig. 3 voltage at 45-46-12) and the second voltage level.
With respect to claim 18, Yung discloses an electronic system comprising: a plurality of electronic devices (Fig. 1 106,108); and a power management integrated circuit (Fig. 1 102) including a voltage regulator (Fig. 1 104) configured to provide an output voltage (Fig. 2 226) to the plurality of electronic devices, wherein the voltage regulator includes: an error amplifier circuit (Fig. 2 206) configured to generate a gate voltage (Fig. 2 214) based on a first voltage level (Fig. 2 218) of a first node (Fig. 2 216) connected to a first end of target circuits included in each of the plurality of electronic devices, the first ends of the target circuits being provided with an operating current (Fig.2 230), a first reference voltage level (Fig. 2 202), and a common ground (Fig. 2 220). Yung remains silent as to providing the ground voltage of the load and the reference voltage to the error amplifier. Wang discloses a voltage regulator with an error amplifier circuit (Fig. 3 1) comprising: a first differential pair (Fig. 3 22,11) comprising: a first input terminal (Fig. 3 22) configured to receive a first reference voltage level (Fig. 3 Vref- from reference ground), and a second input terminal (Fig. 3 11) configured to receive a second reference voltage level (Fig. 3 Vref+), and a second differential pair (Fig. 2 12,21) comprising: a third input terminal (Fig. 3 12) configured to receive a first voltage level (Fig. 3 Vout+ divided by 45-46) and connected to a first end of a target circuit (Fig. 3 51), and a fourth input terminal (Fig. 3 21) configured to receive a second voltage level (Fig. 3 Vout- load return) of a second end of the target circuit, wherein the error amplifier circuit is configured to generate a gate voltage (Fig. 3 gate 42) based on a first potential difference (Fig. 2 potential 11-22) of the first differential pair and a second potential difference (Fig. 2 potential 12-21) of the second differential pair. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a first differential pair comprising: a first input terminal configured to receive a first reference voltage level, and a second input terminal configured to receive a second reference voltage level, and a second differential pair comprising: a third input terminal at a first voltage level and connected to first ends of target circuits included in each of the plurality of electronic devices, the first ends of the target circuits being provided with an operating current, and a fourth input terminal connected to second ends of the target circuits and at a second voltage level, wherein the error amplifier circuit is configured to generate a gate voltage based on a first potential difference of the first differential pair and a second potential difference of the second differential pair, in order to account for the voltage drop due to the wiring from the load to the error amplifier.
With respect to claim 19, Yung in view of Wang make obvious the voltage regulator of claim 18, wherein the error amplifier circuit is configured to: sum (Wang Fig. 2 32 sums 14 and 24) signals based on the first reference voltage level (Fig. 2 22) and the first voltage level (Fig. 2 12), respectively, to obtain a first signal (Fig. 2 32); sum (Wang Fig. 2 31) signals based on the second reference voltage level (Fig. 2 11) and the second voltage level (Fig. 2 21), respectively, to obtain a second signal (Fig. 2 31); compare (Fig. 2 34-36) the first signal and the second signal, to obtain a comparison result (Fig. 2 33); and generate the gate voltage (Fig. 2 gate 42) based on the comparison result.
With respect to claim 20, Yung in view of Wang make obvious the electronic system of claim 19, wherein the voltage regulator includes: a pass transistor (Yung Fig. 2 208) configured to generate the output voltage based on the gate voltage.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yung (US 2018/0284830) in view of Wang (US 2010/0019746) and further in view of Im (US 2011/0102072).
With respect to claim 6, Yung in view of Wang make obvious the voltage regulator of claim 1 as set forth above, and remain silent as to implementing header and footer transistors. The use of header and footer transistors were well known before the effective filing date of the claimed invention.
Im discloses a circuit further comprising: a header transistor (Fig. 1 10) connected between the at least one pass transistor (Fig. 1 14) and the first end of the target circuit (Fig. 1 4) and configured to operate in response to a first power gating voltage (Fig. 1 gate voltages from 20 to GH0-GH3); and a footer transistor (Fig. 1 16) connected between the second end of the target circuit and a ground node (Fig. 1 18) and configured to operate in response to a second power gating voltage (Fig. 1 gate voltages from 20 to GF0-GF3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a header transistor connected between the at least one pass transistor and the first end of the target circuit and configured to operate in response to a first power gating voltage; and a footer transistor connected between the second end of the target circuit and a ground node and configured to operate in response to a second power gating voltage, in order to reduce power consumption is the target circuit during low power modes.
Allowable Subject Matter
Claims 9-11, 15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. See the action date 3/9/26 for the reasons for indicating allowable subject matter for claims 9 and 17. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 15, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, further comprising: target circuits connected between an output node of the at least one pass transistor and a circuit ground; a first switch circuit connected between first ends of the target circuits and the error amplifier circuit and configured to select one or more of the target circuits to be connected to the error amplifier circuit through the first switch circuit; and a second switch circuit connected between second ends of the target circuits and the error amplifier circuit and configured to select one or more of the target circuits to be connected to the error amplifier circuit through the second switch circuit, wherein a voltage level of a third node at which the error amplifier circuit and the first switch circuit are connected matches the first voltage level, and wherein a voltage level of a fourth node where the error amplifier circuit and the second switch circuit are connected matches the second voltage level.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lo (US 2009/0039848) discloses direct feedback of the output voltage (Fig. 1 Vdd) from a pass transistor (Fig. 1 Mpass) to the error amplifier (Fig. 1 180 or feedback through a voltage divider (Fig. 2 44,46).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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