Prosecution Insights
Last updated: April 19, 2026
Application No. 18/757,173

SPARSITY STORAGE ARCHITECTURES FOR TRANSPOSABLE DATASETS

Non-Final OA §102
Filed
Jun 27, 2024
Examiner
NGUYEN, LINH V
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Microsoft Technology Licensing, LLC
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
91%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
1044 granted / 1172 resolved
+21.1% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
38 currently pending
Career history
1210
Total Applications
across all art units

Statute-Specific Performance

§101
2.9%
-37.1% vs TC avg
§103
43.7%
+3.7% vs TC avg
§102
40.0%
+0.0% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1172 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION 2. This office action is in response to communication filed on 06/27/2024. Claims 1-20 are pending on this application. Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 4. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frumkin et al. Pub. No. 2020/0342632. Regarding claim 1. Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin disclose a computing device (100) for implementing sparsity storage architectures (Transmit and/or Store 102), the computing device (100) comprising: processing circuitry (140, 140’) and memory (10, 102, 20), comprising instructions that, during execution , cause the processing circuitry (140, 140’) to: receive a dataset (104) comprising data values (value of 104); encode (10) the received dataset (104) by: identifying a subset (non-zero values) of the data values (values of 104) in the received dataset (104); and generating metadata (Mask; paragraph 0047 discloses “The mask provides data for determining location of non-zero values”) describing indices (paragraph 0044) of the subset (non-zero values) of the data values in the received dataset (104) ; and store the encoded dataset (Transmit and/or Store 102) comprising the metadata (Mask; see Fig. 4 ) and a packed data (non-zero values), wherein the packed data (non-zero values ) corresponds to the subset of the data value (non-zero values in Fig. 4) , and wherein the encoded dataset (102) is capable of being decoded (Decompressor 20) into a transposable data format (106c) with a same sparsity level in transposed (Transposed Sparse Matrix of 106c) and non-transposed (Sparse matrix array 106a) forms. Regarding claim 2. The computing device of claim 1, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further discloses wherein the instructions, during execution, further cause the processing circuitry (140, 140’) to: decode (20) the encoded dataset(102) into a transposable dataset (106c) that comprises: the packed data (non-zero values) in indices (Fig. 4) of the transposable dataset (106c) corresponding to the indices of the subset of the data values (non-zero values in Fig. 4) in the received dataset (104) ; and zero-valued data values (zero values in Fig. 3A and Fig. 3B) in remaining indices of the transposable dataset (106c) . Regarding claim 3. The computing device of claim 2, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further discloses wherein the instructions, during execution, further cause the processing circuitry (140, 140’) to: transpose (106c) the transposable dataset (Fig. 3A and Fig. 3B). Regarding claim 4. The computing device of claim 3, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. further discloses wherein the instructions, during execution, further cause the processing circuitry to: encode (10) the transposed (AT Fig. 3A, 3B) transposable dataset (A in Fig. 3A, 3B). Regarding claim 5. The computing device of claim 2, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further discloses wherein the transposable dataset (A) is formatted as a square matrix (square matrix of A). Regarding claim 6. The computing device of claim 1, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. further disclose wherein the instructions, during execution, further cause the processing circuitry (140, 140’) to: store an encoded data tile (Transmit and/or Store 102), comprising a plurality of encoded datasets (Fig. 3A, Fig.3B, Fig. 3C) that includes the stored encoded dataset (Fig. 3A, Fig.3B, Fig. 3C). Regarding claim 7. The computing device of claim 6, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. further disclose wherein the instructions, during execution, further cause the processing circuitry to: decode (20 the encoded data tile (120) into a transposable decoded data tile (106s) comprising a plurality of transposable datasets (106cm 106d), wherein the transposable decoded data tile (106c, 106d) is capable of being encoded (10) in its transposed form (106c, 106d). Regarding claim 8. The computing device of claim 6, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. further discloses wherein the encoded data tile is stored (Transmit and/or Store 102) such that the encoded datasets (Transmit and/or Store 102) are stored with interleaving packed data (Fig. 5B discloses interleaving MUX of Non-Zero extraction) and metadata (Fig. 5B discloses interleaving MUX of Bitmask). Regarding claim 9. The computing device of claim 6, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. further disclose wherein the encoded data tile is stored (Transmit and/or Store 102) such that packed data of the encoded datasets (non-zero values in diagonal order) are stored together in a first location (location of non-zero values in diagonal order in 102) and the metadata (Mas) of the encoded datasets (non-zero values in diagonal order) are stored together in a second location (location of Mask in 102). Regarding claim 10. The computing device of claim 1, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. further disclose wherein the metadata (MASK) comprises one or more of a list of indices (Bit map indices of Fig. 4) of the subset of the data values (non-zero values in Fig. 4), an encoded (10) form of a list (List of bit mapping in Fig. 4) of indices of the subset of the data values (indices of the subset of the data values in Fig. 4) , or a bitmap (see Fig. 4) , wherein each bit in the bitmap (bitmap in Fig. 4) corresponds to an index (paragraph 0131) of a data value of the received dataset (non-zero data value of received data set in Fig. 4). Regarding claim 11. Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. discloses a method for implementing sparsity storage architectures (transmit and/or Store), the method comprising: receiving a dataset (104) comprising data values (data values of 104); encoding (10) the received dataset (104) by: identifying a subset of the data values (non-zero values in diagonal order) in the received dataset (104); and generating metadata (Mask; paragraph 0047 discloses “The mask provides data for determining location of non-zero values”) describing indices (paragraph 0044) of the subset of the data values (non-zero values) in the received dataset (104); and storing (Transmit and/or Store 102) the encoded dataset (MASK; non-zero values in diagonal order) comprising the metadata (MASK) and packed data (non-zero values in diagonal order), wherein the packed data (non-zero values in diagonal order) corresponds to the subset of the data values (non-zero values in 104), and wherein the encoded dataset (MASK; non-zero values in diagonal order) is capable of being decoded (20) into a transposable data format (106c) with a same sparsity level in transposed (Sparse matrix array of 106c) and non-transposed forms (Sparse matrix array of 106a). Regarding claim 12. The method of claim 11, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further comprising: decoding (20) the encoded dataset (102) into a transposable dataset (106c) that comprises: the packed data (non-zero values in diagonal order) in indices (paragraph 0044) of the transposable dataset (106c) corresponding to the indices (paragraph 0044) of the subset of the data values (non-zero values) in the received dataset (104) ; and zero-valued data values (zero values in 104) in remaining indices of the transposable dataset (Figs. 3A, 3B, 3C). Regarding claim 13. The method of claim 12, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further comprising transposing (106c) the transposable dataset (Figs. 3A, 3B, 3C). Regarding claim 14. The method of claim 12, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further comprising: wherein the transposable dataset (Fig. 3A and Fig. 3B) is formatted as a square matrix (Square Matrix of A and A’ in Fig. 3A and Fig. 3B). Regarding claim 15. The method of claim 11, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further comprising: storing an encoded data tile (102) comprising a plurality of encoded datasets (Fig. 3A, 3B, 3C) that includes the stored encoded dataset (102). Regarding claim 16. The method of claim 15, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further comprising: decoding (20) the encoded data tile (102) into a transposable decoded data tile (106c) comprising a plurality of transposable datasets (Fig. 3A, 3B, 3C), wherein the transposable decoded data tile (106c) is capable of being encoded (10) in its transposed form (106c). Regarding claim 17. The method of claim 15, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further comprising: wherein the encoded data tile (non-zero values in diagonal order) is stored such that the encoded datasets (Transmit and/or Store 102) are stored with interleaving packed (Fig. 5B discloses interleaving MUX of Non-Zero extraction) data and metadata (Fig. 5B discloses interleaving MUX of Bitmask). Regarding claim 18. The method of claim 15, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 further discloses wherein the encoded data tile (MASK) is stored such that packed data ((non-zero values in diagonal order) of the encoded datasets (non-zero values in diagonal order) are stored together in a first location (first location of 102), and the metadata (MASK) of the encoded datasets (non-zero values in diagonal order) are stored together in a second location (second location of 102). Regarding claim 19. The method of claim 11, Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. further disclose wherein the metadata (MASK) comprises one or more of a list of indices (Bit map indices of Fig. 4) of the subset of the data values (non-zero values in Fig. 4), an encoded (10) form of a list of indices of the subset of the data values (indices of the subset of the data values in Fig. 4), or a bitmap (bitmap in Fig. 4), wherein each bit in the bitmap (bitmap in Fig. 4) corresponds to an index ((paragraph 0131) of a data value of the received dataset (non-zero data of received data value in Fig. 4) Regarding claim 20. Fig. 1A Fig. 1B, Fig. 3A, Fig. 4 and Fig. 5 of Frumkin et al. a computing device (100) for implementing sparsity storage architectures ((transmit and/or Store)) , the computing device (100) comprising: processing circuitry (140, 140’) and memory (10, 102, 20) comprising instructions that, during execution, cause the processing circuitry (140, 140’) to: receive an encoded dataset (MASK, Non-zero values in diagonal order) that includes a block of data values (Non-zero values in diagonal order) and metadata (MASK) describing a set of indices to be set to data values of the block of data values (paragraph 0047 discloses “The mask provides data for determining location of non-zero values”; and decode (20) the encoded dataset (dataset (MASK, Non-zero values in diagonal order) into a transposable matrix (106c) by: for each index of the set of indices (see Fig. 4 for discloses bitmap “1” indexing for non-zero values), inserting a data value (insert bit map “1” in Fig. 4) from the block of data values (non-zero data values in received data in Fig. 1) into the index (bit map indexing of Fig. 4) of the transposable matrix (transposable Matrix in Fig. 4) ; and inserting a common value (inserting “0”) to remaining indices (remaining of zero value positions) in the transposable matrix (transposable Matrix in Fig. 4) that were not inserted with a data value (non-zero value) from the block of data values (bocks of data values of received data in Fig. 4). Contact Information 5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications. 01/02/2026 /LINH V NGUYEN/Primary Examiner, Art Unit 2845
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Prosecution Timeline

Jun 27, 2024
Application Filed
Jan 03, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
91%
With Interview (+2.1%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1172 resolved cases by this examiner. Grant probability derived from career allow rate.

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