DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Final Office Action is in response to the applicant’s remarks and arguments filed on November 19, 2025.
Claims 1-21 were previously pending in the application. Claims 22-24 are added and claims 2-3, 11 and 15 are canceled. Claims 1, 4-5, 7-10, 12 and 17-19 are amended.
Claims 1, 4-10, 12-14 and 16-24 remain pending in the application. Claims 1, 4-10, 12-14 and 16-24 are being considered on the merits.
Response to Arguments
The applicant’s remarks and/or arguments, filed on November 19, 2025 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Applicant's arguments, in the applicant’s remarks and amendments, filed on November 19, 2025, have been fully considered and are persuasive. Therefore, the previous claim(s) rejection under 35 U.S.C 102 has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art US20160188466A1 issued to Hady et al. and in view of the previously cited prior art(s).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-10, 12-14, 16-17, 19-20 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hady et Al. (US 20160188466 A1) and "Access: Smart Scheduling for Asymmetric Cache CMPs", Xiaowei Jiang et al., 2011 IEEE 17th International Symposium on High Performance Computer Architecture (2011, Page(s): 527-538) and Fang et al. (a Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures, Micromachines 2022).
As per claim 1, Hady discloses A computing device comprising:
a set of a first type of cores [Para [0010]-[0012], Figs 1A-1C, heterogeneous cores (CPU + NPU)];
a second set of a second type of cores that are a heterogeneous type from the set of the first type of cores [Para [0010]-[0012], Figs 1A-1C, heterogeneous cores (CPU + NPU)].
Hady further discloses a shared cache for all cores [Para 0010-0012].
However, Hady does not specifically teach a first last level cache associated with the set of the first type of cores; a second last level cache that is asymmetrical from the first last level cache, the second last level cache associated with the second set of the second type of cores as recited in the claim.
Jiang discloses a first last level cache associated with the set of the first type of cores [Figs 3-4; Core-0, Core-; Large Cache, Big LLC];
a second last level cache that is asymmetrical from the first last level cache, the second last level cache associated with the second set of the second type of cores [Figs 3-4; Core-2, Core-3 with Small cache, Small LLC]. Jiang teaches asymmetric cache architecture in which different processing resources are intentionally provided different cache resources to improve performance and resource utilization.
Both Hady and Jiang teach assigning processing resources to cache and are therefore combinable/modifiable.
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Hady’s heterogeneous processor architecture so that the cache associated with one processor group differs from the cache associated with another processor group because Jiang teaches that asymmetric cache organizations improve performance and permit cache resources to be matched to processor requirements.
The resulting system would comprise a first heterogeneous processor cluster having a first LLC and a second heterogeneous processor cluster having a second LLC whose characteristics differ, thereby meeting the claimed asymmetric cache limitation.
Motivation would improve performance by tailoring cache resources to workload characteristics rather than providing identical cache resources.
Fang teaches asymmetric multicore processors exhibit different memory behavior; big and little cores compete differently for LLC resources; and cache management should preferentially retain data for performance cores [Section 1].
Although Fang assumes a shared LLC rather than separate LLCs, it provides additional motivation for allocating different cache resources to different core types since a shared partitioned memory can operate similarly to separate memories.
Because heterogeneous cores exhibit different cache behavior, it would have been obvious to provide cache resources tailored to the respective heterogeneous core types rather than identical cache structures, thereby allowing heterogeneous cores to benefit from differentiated cache treatment.
One of ordinary skill in the art would have been motivated before the effective filing date of the claimed invention to modify Hady’s heterogeneous processor groups so that the cache associated with one processor group differs from the cache associated with another processor group in size, associativity, latency, or replacement policy in order to improve area efficiency, power consumption, and workload-specific performance.
As per claim 4, Hady discloses the computing device of claim 1, wherein the set of the first type of cores have at least one performance characteristic that is different than the set of the second type of cores [Para [0011]-[0012], CPU and NPU cores with different architectures and performance.. Both have different characteristics (latency/bandwidth, etc.)].
As per claim 5, Hady discloses the computing device of claim 1, wherein the set of the first type of cores comprise high performance cores and the set of the second type of cores comprise efficiency cores [Para [0012], [0020], CPUs (high performance), NPUs (specialized/efficient for networking). NPUs are specialized/efficient for certain tasks.].
As per claim 6, Jiang discloses the computing device of claim 5, wherein the first last level cache is larger than the second last level cache [Figs 3-4; Large Cache, Small Cache; Big LLC, Small LLC].
As per claim 7, Jiang discloses the computing device of claim 1, further comprising an operating system and a memory controller, the memory controller configured to assign instructions requested by the operating system to either the first set of cores associated with the first last level cache or the second set of cores associated with the second last level cache [Section 3.3, pgs 532-533; When a thread arrives, the scheduler decides where to map the thread by comparing the following six cases (keep in mind that number of threads on each core/cache needs to be roughly the same to maintain fairness in terms of CPU time a thread can get)].
As per claim 8, Jiang teaches the computing device of claim 7, wherein the memory controller is configured to assign instructions based on both performance characteristics of the first set of cores and the second set of cores and sizes of the first last level cache and the second last level cache [Section 3.3, pgs 532-533; When a thread arrives, the scheduler decides where to map the thread by comparing the following six cases (keep in mind that number of threads on each core/cache needs to be roughly the same to maintain fairness in terms of CPU time a thread can get)].
As per claim 9, Hady discloses the computing device of claim 1, wherein the computing device comprises a laptop, and wherein the set of the first type of cores and the set of second type of cores are included in a central processing unit of the laptop [Para [0010], Figs. 1A-1C, Hady is generic to “processors,” could be used in a laptop. Not limiting; not a critical distinction.].
Fang et al. discloses the computing device comprises a laptop, and wherein the first set of cores and the second set of cores are included in a central processing unit of the laptop [Section 1; Modern computer systems are more diverse than ever, ranging in size from handheld embedded machines to large cloud computing centers. The processor uses different types of cores, and each type of core has a different microarchitecture design.]
Hady, Jiang and Fang are in the same field of endeavor as they are both in the multi-core processing architecture art and, therefore, are combinable/modifiable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include assymetric cores in a central processing unit of a laptop because the system can be optimized for power/performance or different application domains, or can take advantage of instruction-level parallelism (ILP), thread-level parallelism (TLP), or memory-level
parallelism (MLP). Therefore, asymmetric multi-core processors are easier to adapt to diversity and are expected to play a role in a wide range of usage scenarios as disclosed by Fang et al. (Section 1).
As per claim 10, Hady discloses A system comprising: a central processing unit comprising at least a first type of core and a second type of core, wherein the first type of core and the second type of core are heterogeneous core types [Para [0010]-[0012], Figs 1A-1C, heterogeneous cores (CPU + NPU)].
Hady further discloses a shared cache for all cores [Para 0010-0012]. However, Hady does not specifically teach at least two asymmetrical last level caches.
Jiang discloses at least two asymmetrical last level caches [Figs 3-4; Core-2, Core-3 with Small cache, Small LLC]. Jiang teaches asymmetric cache architecture in which different processing resources are intentionally provided different cache resources to improve performance and resource utilization.
Both Hady and Jiang teach assigning processing resources to cache and are therefore combinable.
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Hady’s heterogeneous processor architecture so that the cache associated with one processor group differs from the cache associated with another processor group because Jiang teaches that asymmetric cache organizations improve performance and permit cache resources to be matched to processor requirements.
The resulting system would comprise a first heterogeneous processor cluster having a first LLC and a second heterogeneous processor cluster having a second LLC whose characteristics differ, thereby meeting the claimed asymmetric cache limitation.
Motivation would improve performance by tailoring cache resources to workload characteristics rather than providing identical cache resources.
Fang teaches asymmetric multicore processors exhibit different memory behavior; big and little cores compete differently for LLC resources; and cache management should preferentially retain data for performance cores [Section 1].
Although Fang assumes a shared LLC rather than separate LLCs, it provides additional motivation for allocating different cache resources to different core types since a shared partitioned memory can operate similar to separate memories.
Because heterogeneous cores exhibit different cache behavior, it would have been obvious to provide cache resources tailored to the respective heterogeneous core types rather than identical cache structures, thereby allowing heterogeneous cores to benefit from differentiated cache treatment.
One of ordinary skill in the art would have been motivated before the effective filing date of the claimed invention to modify Hady’s heterogeneous processor groups so that the cache associated with one processor group differs from the cache associated with another processor group in size, associativity, latency, or replacement policy in order to improve area efficiency, power consumption, and workload-specific performance.
As per claim 12, Hady discloses the system of claim 10, wherein the first type of core comprises a high-performance core and the second type of core comprises an efficiency core [Para [0012], [0020], CPUs (high performance), NPUs (specialized/efficient for networking). NPUs are specialized/efficient for certain tasks.].
As per claim 13, Jiang discloses the system of claim 12, wherein the at least two asymmetrical last level caches include at least a first last level cache and a second last level cache [Figs 3-4; Core-2, Core-3 with Small cache, Small LLC]. Jiang teaches asymmetric cache architecture in which different processing resources are intentionally provided different cache resources to improve performance and resource utilization.
As per claim 14, Jiang discloses the system of claim 13, wherein the first last level cache is associated with the high-performance core and the second last level cache is associated with the efficiency core [see rejection of claim 10 above].
As per claim 16, Jiang discloses the system of claim 13, wherein the at least two asymmetrical last level caches include at least a third last level cache [Figs. 3- 4; Large Cache, Small cache, Big LLCs, Small LLCs].
As per claim 17, Jiang discloses the system of claim 16, further comprising a third core that is associated with the third last level cache [Fig 4; Big LLCs, Small LLCs].
As per claim 19, Hady, Jiang and Fang disclose the claimed invention as detailed above for claim 1.
Jiang further discloses a method comprising:
scheduling a first instruction for execution on a first core of a set of a first type of cores based on characteristics of cores of the set of the first type of cores and based on characteristics of a first last level cache associated with the set of cores [Section 3.3, pgs 532-533; When a thread arrives, the scheduler decides where to map the thread by comparing the following six cases (keep in mind that number of threads on each core/cache needs to be roughly the same to maintain fairness in terms of CPU time a thread can get)]; and
scheduling a second instruction for execution on a second core of a set of a second type of cores based on characteristics of cores of the set of the second type of cores and based on characteristics of a second last level cache associated with the set of the second type of cores [Section 3.3, pgs 532-533; When a thread arrives, the scheduler decides where to map the thread by comparing the following six cases (keep in mind that number of threads on each core/cache needs to be roughly the same to maintain fairness in terms of CPU time a thread can get)].
As per claim 20, the claim is rejected the same rationale as per claims 5 and 6 above.
As per claim 23, Jiang discloses The method of claim 19, wherein the first instruction and the second instruction are scheduled based on at least one prediction by one or more machine learning models [Abstract; OS scheduler support to make use of the prediction capability and appropriately schedule applications on to core with suitable cache capacity; Section 3.3, one way to improve overall thread performance using the OS scheduler is to use training based approach].
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hady et Al. (US 20160188466 A1) and "Access: Smart Scheduling for Asymmetric Cache CMPs", Xiaowei Jiang et al., 2011 IEEE 17th International Symposium on High Performance Computer Architecture (2011, Page(s): 527-538) and Fang et al. (a Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures, Micromachines 2022) and Chisholm et al., “Cache Sharing and Isolation Tradeoffs in Multicore Mixed-Criticality Systems”, 2015 IEEE Real-Time Systems Symposium (2015, Page(s): 305-316).
As per claim 18, Hady, Jiang and Fang disclose the invention as detailed above. However, Jiang et al. does not teach the system of claim 17, wherein the third core comprises a low priority core.
Chisholm et al. discloses a core comprises a low priority core [pg. 306, MC2. Our examination of LLC allocation tradeoffs in MC systems is based upon the MC2 (mixed-criticality on multicore) framework [10, 18, 20], which has been the subject of continuing research by our group.2 In MC2, four criticality levels exist, denoted A (highest) through D (lowest), as shown in Fig. 2. Higher-criticality tasks are statically prioritized over lower-criticality ones.]
Hady, Jiang, Fang and Chisholm are in the same field of endeavor as they are both in the multi-core processing architecture art and, therefore, are combinable/modifiable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include a third core as a low priority core because a mixed criticality on multicore framework can better utilize available resources and would have resulted in significant schedulability improvements, lower cost and improved resource allocation as taught by Chisholm et al. (pg. 305).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hady et Al. (US 20160188466 A1) and "Access: Smart Scheduling for Asymmetric Cache CMPs", Xiaowei Jiang et al., 2011 IEEE 17th International Symposium on High Performance Computer Architecture (2011, Page(s): 527-538) and Fang et al. (a Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures, Micromachines 2022) and Murali Dadi et al., “Performance Study of Partitioned Caches in Asymmetric Multi-Core Processors”, 2023.
As per claim 21, Hady, Jiang and Fang disclose the invention as detailed above. However, the combination of references does not teach the system of claim 14, wherein the high performance core operates at a higher frequency than the efficiency core.
Murali Dadi discloses the high performance core operates at a higher frequency than the efficiency core [Page 4, Para 1; In these configurations, cores 0-7 are In-order cores running at 1GHz (i.e., efficiency cores), whereas cores 8-15 are Out-of-order cores running at 2.66GHz (i.e., performance cores). When Out-of-Order and In-order cores share a cache memory, there is a chance that Out-of-order cores may occupy a large portion of the cache, which further degrades the performance of In-order cores (i.e., efficiency cores) running at a lower frequency.]
Hady, Jiang, Fang and Murali Dadi are in the same field of endeavor as they are both in the multi-core processing architecture art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Hady, Jiang and Fang with the teachings of Murali Dadi in order to include high performance cores operating at a higher frequencies to introduce heterogeneity and asymmetry in the system.
Modification would improve the performance of the system by helping achieve the desired power values and optimal cache miss penalties as taught by Murali Dadi (Abstract).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hady et al. (US 20160188466 A1) and "Access: Smart Scheduling for Asymmetric Cache CMPs", Xiaowei Jiang et al., 2011 IEEE 17th International Symposium on High Performance Computer Architecture (2011, Page(s): 527-538) and Fang et al. (a Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures, Micromachines 2022) and Blagodurov (US 9,965,329 B2).
As per claim 22, Hady, Jiang and Fang disclose the invention as detailed above. However, the combination of references does not explicitly disclose that the first and second instructions correspond to heterogeneous workloads.
Blagodurov teaches assigning workloads to heterogeneous processing resources based on workload characteristics and processor characteristics. The reference discloses analyzing different workloads and mapping those workloads to different classes of heterogeneous processor cores according to processor metrics and workload attributes. Thus, the reference teaches that instructions associated with different heterogeneous processing resources based on the characteristics of the workloads and the processing resources (Col. 3, lines 3-49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the scheduling technique of Jiang so that the first and second instructions correspond to heterogeneous workloads as taught by Blagodurov. Doing so would have enabled workload-aware scheduling, improving utilization of heterogeneous processor resources and increasing overall system performance by matching workload characteristics to the most suitable processing resources.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hady et Al. (US 20160188466 A1) and "Access: Smart Scheduling for Asymmetric Cache CMPs", Xiaowei Jiang et al., 2011 IEEE 17th International Symposium on High Performance Computer Architecture (2011, Page(s): 527-538) and Fang et al. (a Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures, Micromachines 2022) and Mills et al. (US 8,578,387 B1).
As per claim 24, Hady, Jiang and Fang disclose the invention as detailed above. However, the combination of references does not expressly describe selecting instructions according to instruction-specific attributes or instruction type.
Mills teaches dynamically assigning instructions to heterogeneous processing engines according to instruction characteristics or instruction type. Specifically, Mills discloses determining the characteristics of instructions and dispatching different instruction types to processing resources that are best suited to execute those instructions (Col. 1, line 33- Col. 2, line 29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the instruction-level scheduling techniques of Mills into the modified system of Hady, Jiang and Fang because instruction-level classification provides finer grained scheduling decisions than workload level classification alone. Combining these teachings would have predictably improved execution efficiency by allowing individual instructions within heterogeneous workloads to be mapped to heterogeneous cores according to instruction attributes while considering the characteristics of the associated last level caches, thereby improving processor throughput, cache efficiency, and overall utilization.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a) Lai et al. US 10852810 B2 discloses a processing system having a plurality of processor cores includes, based at least in part on a first set of last-level caches of a plurality of last-level caches being in a first power-consumption mode, using a first set of links to route accesses by a first processor core of the plurality of processor cores to the first set of last-level caches. The method also includes, based at least in part on a second set of last-level caches of the plurality of last-level caches being in the first power-consumption mode, using a second set of links to route accesses by the first processor core to the second set of last-level caches (Col. 1, lines 48-59).
b) Kruglick US 8904114 B2 discloses distinct and/or separate higher level (or upper level) caches, such as level 2 (L2) and/or level 3 (L3) caches, may be shared by different groups of processor cores. Thus, for example, in various implementations, independent upper level caches may be associated with or shared by specific groups of processor cores within a multicore processor system (Col. 2, lines 33-39).
c) Rotithor US 20090248976 A1 discloses in some alternative embodiments, each core 110 has a separate LLC (instead of a shared LLC 116) and the cores 110 share a number of resources downstream from the LLC (e.g., interconnect 118, memory controller 120, DRAM 122, and the like) (Para [0017]).
d) Wang et al. US 20160342514 A1 discloses massive memory accesses from one or more first cores (e.g., GPU cores) degrade the performance of one or more second cores (e.g., CPU cores). Cache partitioning is a commonly used technique for LLC management in such multi-core computing systems (Para [0005]).
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE M. VITAL whose telephone number is (571) 272-4215. The examiner can normally be reached on Monday-Friday 8:00 AM - 4:00 PM.
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July 15, 2026
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2162
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