DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/21/2026 has been entered.
Response to Amendment
The office action is responding to the amendments filed on 01/21/2026. Claims 1-10, 14-18 and 20-22 have been amended. Claims 11-13 were previously cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 8, 10 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] and in further view of Dally et al. [US 2023/0315651 A1].
Claim 1 is rejected over Kim, Patel and Dally.
Kim teaches “A system comprising:” as “Although not illustrated in FIG. 1, the test system 1000 may further include a communication device which communicates with an external host requesting a test, a memory that temporarily stores various information related with various tests, and a power supply circuit (not illustrated) for supplying power to various devices included in the test system 1000.” [¶0021]
“a processor” as “an application processor (AP)” [¶0022]
“a storage array having a plurality of storage circuits implemented on different dies in a stack of dies; and” as “the semiconductor device 1200 may include a plurality of semiconductor dies having a stacked structure, and the plurality of semiconductor dies may include a buffer die 1210 communicating with the test logic 1100 outside or an external memory controller (not illustrated), and first through N.sup.th stack dies 1220_1 through 1220_N stacked on the buffer die 1210.” [¶0022]
“receive responses from the storage circuits in reply to cache requests forwarded through the stack of dies; and” as “This test method includes receiving, in a test mode of the semiconductor device, by the buffer die, test inputs for testing the plurality of stack dies from an external test logic, and then delaying, by a delay control circuit provided in the buffer die, the test inputs according to a delay amount set in response to a delay control signal.” [¶0008]
Kim does not explicitly teach a cache controller implemented on a same semiconductor die as the processor and as a first storage circuit in the stack of dies, the cache controller operable to:
set respective latencies for communicating with each of the storage circuits;
output each response to the processor according to a respective latency of a storage circuit of the plurality of storage circuits that provides the response.
However, Patel teaches “a cache controller implemented on a same semiconductor die as the processor and as a first storage circuit in the stack of dies, the cache controller operable to:” as “Any number of N level caches can be used. The next level cache, such as N level cache 212 (e.g., last level cache) and N level cache controller 210 can be in communication with and shared by caches of multiple processors, such as for example, caches of a CPU or GPU (not shown), which may be located on the same die,” [¶0030]
Kim and Patel are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim and Patel before him/her, to modify the teachings of Kim to include the teachings of Patel with the motivation of the cache is dynamically controlled to switch between a mode in which the cache is associatively mapped and a mode in which a portion of the cache is directly mapped and another portion of the cache is associatively mapped. [Patel, ¶0018]
The combination of Kim and Patel does not explicitly teach set respective latencies for communicating with each of the storage circuits;
output each response to the processor according to a respective latency of a storage circuit of the plurality of storage circuits that provides the response.
However, Dally teaches “set respective latencies for communicating with each of the storage circuits;” as “the tile network 214 provides flat (uniform) bandwidth within each die stack 220 and also provides reduced memory access latency for nearby tile stacks 200 within each die stack 220.” [¶0057]
“output each response to the processor according to a respective latency of a storage circuit of the plurality of storage circuits that provides the response.” as “the tile network 214 provides flat (uniform) bandwidth within each die stack 220 and also provides reduced memory access latency for nearby tile stacks 200 within each die stack 220.” [¶0057] (If each die has different latency, they will output data according to respective latency)
Kim, Patel and Dally are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel and Dally before him/her, to modify the teachings of combination of Kim and Patel to include the teachings of Dally with the motivation of the memory bandwidth advantage resulting from the hierarchical, stacked memory system comprising a die stack (or the die stack) is utilized by co-locating threads and data so that most of the memory accesses made by a given thread access the local memory tile(s). [Dally, ¶0068]
Claim 3 is rejected over Kim, Patel and Dally.
Kim teaches “wherein the different characteristics including different stack position with the stack of dies.” as “the timings of providing the test inputs may be set differently depending on positions of the core dies 1420, or the timings of providing the test inputs may be set differently per channel for the first through eighth channels CH1 through CH8.” [¶0057]
Claim 8 is rejected over Kim, Patel and Dally.
Kim teaches “wherein the cache controller is further operable to: receive the cache requests from the processor; and” as “the test logic 1100 may be implemented as a semiconductor chip, such as a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC), and an application processor (AP), and may transmit and receive various information according to a parallel communication method between each of the semiconductor devices 1200.” [¶0022]
“forward the cache requests through the stack of dies.” as “as the first through N.sup.th stack dies 1220_1 through 1220_N of the semiconductor device 1200 sequentially perform processing operations by using the first through N.sup.th delayed test inputs Input_1 through Input_N, the test logic 1100 may receive sequentially test results Outputs from the first through N.sup.th stack dies 1220_1 through 1220_N and determine whether the first through N.sup.th stack dies 1220_1 through 1220_N are defective based on a certain logic process. ” [¶0034]
Claim 10 is rejected over Kim, Patel and Dally.
Kim teaches “wherein the cache controller is operable to maintain, within storage of the cache controller, a record of the respective latencies for communicating with each of the storage circuits; and set the respective latencies based on the record.” as “The wafer level test may correspond to a test on an individual semiconductor die at a wafer level.” [¶0023] and “in the plurality of delay circuits included in each of the first through N.sup.th delay chains 1213_21 through 1213_2N, the number of delay circuits through which the test inputs Input pass according to the above-described delay control signal may be adjusted, and based thereon, the delay amounts of the first through N.sup.th delay chains 1213_21 through 1213_2N may be set to be different from each other. ” [¶0036]
Claim 14 is rejected over Kim, Patel and Dally under the same rationale of rejection of claim 1.
Claim 15 is rejected over Kim, Patel and Dally under the same rationale of rejection of claim 2.
Claim 16 is rejected over Kim, Patel and Dally.
Kim teaches “wherein the different characteristics include different stack positions within the stacked storage array.” as “the timings of providing the test inputs may be set differently depending on positions of the core dies 1420, or the timings of providing the test inputs may be set differently per channel for the first through eighth channels CH1 through CH8.” [¶0057] and “the delay amount of the test input for the first channel CH1 may be relatively less than the delay amount of the test input for the second channel CH2.” [¶0069]
Claim 17 is rejected over Kim, Patel and Dally.
Kim teaches “wherein respective latency of a second storage circuit in the stacked storage array is longer than a respective latency of a first storage circuit in the stacked storage array and shorter different than a respective latency of a last storage circuit in the stacked storage array.” as “the delay amount of the test input for the first channel CH1 may be relatively less than the delay amount of the test input for the second channel CH2.” [¶0069]
Claim 18 is rejected over Kim, Patel and Dally under the same rationale of rejection of claim 10.
Claim 19 is rejected over Kim, Patel and Dally.
Kim does not explicitly teach wherein the cache controller is implemented on a same semiconductor die as a first storage circuit in the stacked storage array.
However, Patel teaches “wherein the cache controller is implemented on a same semiconductor die as a first storage circuit in the stacked storage array.” as “Any number of N level caches can be used. The next level cache, such as N level cache 212 (e.g., last level cache) and N level cache controller 210 can be in communication with and shared by caches of multiple processors, such as for example, caches of a CPU or GPU (not shown), which may be located on the same die,” [¶0030]
Claim 20 is rejected over Kim, Patel and Dally under the same rationale of rejection of claim 1.
Claim(s) 2, 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] in further view of Dally et al. [US 2023/0315651 A1] and yet in further view of Dwork [US 6,615,378 B1].
Claim 2 is rejected over Kim, Patel and Dally and Dwork.
The combination of Kim, Patel and Dally does not explicitly teach wherein the cache controller is further operable to set the respective latencies to cause a different response latency between two or more storage circuits in the stack of dies based on different characteristics of the two or more storage circuits.
However, Dwork teaches “wherein the cache controller is further operable to set the respective latencies to cause a different response latency between two or more storage circuits in the stack of dies based on different characteristics of the two or more storage circuits.” as “When a different type of SRAM is used, such as a zero byte turnaround SRAM, the latency concerns may be different.” [Col 9, lines 19-21]
Kim, Patel and Dally and Dwork are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel and Dally and Dwork before him/her, to modify the teachings of combination of Kim, Patel and Dally to include the teachings of Dwork with the motivation of it is advantageous for the network interface controller to incorporate a large amount of storage. [Dwork, Col 1, lines 34-35]
Claim 4 is rejected over Kim, Patel and Dally and Dwork.
The combination of Kim, Patel and Dally does not explicitly teach wherein the different characteristics include different storage circuit materials that cause the two or more of the storage circuits to have different response latencies.
However, Dwork teaches “wherein the different characteristics include different storage circuit materials that cause the two or more of the storage circuits to have different response latencies.” as “When a different type of SRAM is used, such as a zero byte turnaround SRAM, the latency concerns may be different.” [Col 9, lines 19-21]
Kim, Patel and Dally and Dwork are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel and Dally and Dwork before him/her, to modify the teachings of combination of Kim, Patel and Dally to include the teachings of Dwork with the motivation of it is advantageous for the network interface controller to incorporate a large amount of storage. [Dwork, Col 1, lines 34-35]
Claim 5 is rejected over Kim, Patel and Dally and Dwork.
The combination of Kim, Patel and Dally does not explicitly teach wherein the different characteristics include different storage circuit technologies that cause the two or more of the storage circuits to have different response latencies.
However, Dwork teaches “wherein the different characteristics include different storage circuit technologies that cause the two or more of the storage circuits to have different response latencies.” as “When a different type of SRAM is used, such as a zero byte turnaround SRAM, the latency concerns may be different.” [Col 9, lines 19-21]
Kim, Patel and Dally and Dwork are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel and Dally and Dwork before him/her, to modify the teachings of combination of Kim, Patel and Dally to include the teachings of Dwork with the motivation of it is advantageous for the network interface controller to incorporate a large amount of storage. [Dwork, Col 1, lines 34-35]
Claim 6 is rejected over Kim, Patel and Dally and Dwork.
The combination of Kim, Patel and Dally does not explicitly teach wherein the different characteristics include different capacities with or different data transfer rates that cause the two or more of the storage circuits to have different response latencies.
However, Dwork teaches “wherein the different characteristics include different capacities with or different data transfer rates that cause the two or more of the storage circuits to have different response latencies.” as “When a different type of SRAM is used, such as a zero byte turnaround SRAM, the latency concerns may be different.” [Col 9, lines 19-21]
Kim, Patel and Dally and Dwork are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel and Dally and Dwork before him/her, to modify the teachings of combination of Kim, Patel and Dally to include the teachings of Dwork with the motivation of it is advantageous for the network interface controller to incorporate a large amount of storage. [Dwork, Col 1, lines 34-35]
Claim 7 is rejected over Kim, Patel and Dally and Dwork.
The combination of Kim, Patel and Dally does not explicitly teach wherein the different characteristics include different circuit layout types with different crossing latencies or timing margins that cause the two or more of the storage circuits to have different response latencies.
However, Dwork teaches “wherein the different characteristics include different circuit layout types with different crossing latencies or timing margins that cause the two or more of the storage circuits to have different response latencies.” as “When a different type of SRAM is used, such as a zero byte turnaround SRAM, the latency concerns may be different.” [Col 9, lines 19-21]
Kim, Patel and Dally and Dwork are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel and Dally and Dwork before him/her, to modify the teachings of combination of Kim, Patel and Dally to include the teachings of Dwork with the motivation of it is advantageous for the network interface controller to incorporate a large amount of storage. [Dwork, Col 1, lines 34-35]
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] in further view of Dally et al. [US 2023/0315651 A1] and yet in further view of Gutierrez et al. [US 2022/0188208 A1].
Claim 9 is rejected over Kim, Patel Dally and Gutierrez.
The combination of Kim, Patel and Dally does not explicitly teach wherein the cache controller is operable to: determine respective worst-case latencies for communicating with the storage circuits; and set the respective latencies to be the respective worst-case latencies.
However, Gutierrez teaches “wherein the cache controller is operable to: determine respective worst-case latencies for communicating with the storage circuits; and set the respective latencies to be the respective worst-case latencies.” as “Since the memory dies 411-415 are connected to the logic die 403 via signal pathways having different lengths, the memory stack 400 is designed to accommodate the worst-case latency to ensure a uniform view of all dies in the stack.” [¶0038]
Kim, Patel, Dally and Gutierrez are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel, Dally and Gutierrez before him/her, to modify the teachings of combination of Kim, Patel, Dally to include the teachings of Gutierrez with the motivation of when the cache capacity is increased, a snooping based coherency mechanism is used. At normal temperatures, when the cache capacity is smaller, a probe filter mechanism is used. [Gutierrez, ¶0047]
Claim(s) 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] in further view of Dally et al. [US 2023/0315651 A1] and yet in further view of Balakrishnan et al. [US 2010/0275049 A1].
Claim 21 is rejected over Kim, Patel, Dally and Balakrishnan.
The combination of Kim, Patel, Dally does not explicitly teach wherein the storage array is a cache for the processor, and the cache controller controls processor access to data located at the cache.
However, Balakrishnan teaches “wherein the storage array is a cache for the processor, and the cache controller controls processor access to data located at the cache.” as “A cache memory is a very fast buffer comprising an array of local storage cells used by one or more processors to hold frequently requested copies of data.” [¶0002]
Kim, Patel, Dally and Balakrishnan are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel, Dally and Balakrishnan before him/her, to modify the teachings of combination of Kim, Patel and Dally to include the teachings of Balakrishnan with the motivation of having the benefit of this disclosure, will realize that the present disclosure contemplates conserving power in non-uniform cache access (NUCA) caches by sequentially turning off groups of banks according to a hierarchy of increasing access latencies. [Balakrishnan, ¶0080]
Claim 22 is rejected over Kim, Patel, Dally and Balakrishnan under the same rationale of rejection of claim 21.
Claim 23 is rejected over Kim, Patel, Dally and Balakrishnan under the same rationale of rejection of claim 21.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/MASUD K KHAN/Primary Examiner, Art Unit 2132
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