DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 06/24/2026. Claims 1-3, 9-10, 14-15 and 17-20 have been amended. Claims 4-7 are cancelled. Claims 11-13 were previously cancelled. Claims 24-27 are new.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 8, 10 and 14, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] and in further view of Nossenson et al. [US 2023/0106208 A1].
Claim 1 is rejected over Kim, Patel and Nossenson.
Kim teaches “A system comprising:” as “Although not illustrated in FIG. 1, the test system 1000 may further include a communication device which communicates with an external host requesting a test, a memory that temporarily stores various information related with various tests, and a power supply circuit (not illustrated) for supplying power to various devices included in the test system 1000.” [¶0021]
“a processor” as “an application processor (AP)” [¶0022]
“a storage array having a plurality of storage circuits implemented on different dies in a stack of dies; and” as “the semiconductor device 1200 may include a plurality of semiconductor dies having a stacked structure, and the plurality of semiconductor dies may include a buffer die 1210 communicating with the test logic 1100 outside or an external memory controller (not illustrated), and first through N.sup.th stack dies 1220_1 through 1220_N stacked on the buffer die 1210.” [¶0022]
“receive responses from the plurality of storage circuits in reply to cache requests forwarded through the stack of dies; and” as “This test method includes receiving, in a test mode of the semiconductor device, by the buffer die, test inputs for testing the plurality of stack dies from an external test logic, and then delaying, by a delay control circuit provided in the buffer die, the test inputs according to a delay amount set in response to a delay control signal.” [¶0008]
Kim does not explicitly teach a cache controller implemented on a same semiconductor die as the processor and as a first storage circuit in the stack of dies, the cache controller operable to:
set latencies for communicating with each of the plurality of storage circuits;
delay output of each response to the processor for a latency set for a corresponding storage circuit of the plurality of storage circuits that provides the response.
However, Patel teaches “a cache controller implemented on a same semiconductor die as the processor and as a first storage circuit in the stack of dies, the cache controller operable to:” as “Any number of N level caches can be used. The next level cache, such as N level cache 212 (e.g., last level cache) and N level cache controller 210 can be in communication with and shared by caches of multiple processors, such as for example, caches of a CPU or GPU (not shown), which may be located on the same die,” [¶0030]
Kim and Patel are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim and Patel before him/her, to modify the teachings of Kim to include the teachings of Patel with the motivation of the cache is dynamically controlled to switch between a mode in which the cache is associatively mapped and a mode in which a portion of the cache is directly mapped and another portion of the cache is associatively mapped. [Patel, ¶0018]
The combination of Kim and Patel does not explicitly teach set latencies for communicating with each of the plurality of storage circuits;
delay output of each response to the processor for a latency set for a corresponding storage circuit of the plurality of storage circuits that provides the response.
However, Nossenson teaches “set latencies for communicating with each of the plurality of storage circuits;” as “One method includes predicting an IOPS limit for a plurality of storage pools based on a maximum allowed latency of each storage pool” [Abstract]
“delay output of each response to the processor for a latency set for a corresponding storage circuit of the plurality of storage circuits that provides the response.” as “a total number of IOPS (e.g., 228, FIG. 2D) directed towards all the storage volumes associated with each storage pool, wherein the latency indicates a delay in processing input/output (I/O) requests and is based on a delay associated with storage volumes of each storage pool without assigned QoS limits;” [¶0106]
Kim, Patel and Nossenson are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel and Nossenson before him/her, to modify the teachings of combination of Kim and Patel to include the teachings of Nossenson with the motivation of queuing theory and machine learning to build a model for each resource of a networked storage system, including storage resources. The model is built overtime and defines optimum use limit of each resource. [Nossenson, ¶0024]
Claim 3 is rejected over Kim, Patel and Nossenson.
Kim teaches “wherein the different characteristics including one or more of: different stack position with the stack of dies; different storage circuit materials; different storage circuit technologies; different capacities or different data transfer rates; and different circuit layout types with different crossing latencies or timing margins.” as “the timings of providing the test inputs may be set differently depending on positions of the core dies 1420, or the timings of providing the test inputs may be set differently per channel for the first through eighth channels CH1 through CH8.” [¶0057]
Claim 8 is rejected over Kim, Patel and Nossenson.
Kim teaches “wherein the cache controller is further operable to: receive the cache requests from the processor; and” as “the test logic 1100 may be implemented as a semiconductor chip, such as a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC), and an application processor (AP), and may transmit and receive various information according to a parallel communication method between each of the semiconductor devices 1200.” [¶0022]
“forward the cache requests through the stack of dies.” as “as the first through N.sup.th stack dies 1220_1 through 1220_N of the semiconductor device 1200 sequentially perform processing operations by using the first through N.sup.th delayed test inputs Input_1 through Input_N, the test logic 1100 may receive sequentially test results Outputs from the first through N.sup.th stack dies 1220_1 through 1220_N and determine whether the first through N.sup.th stack dies 1220_1 through 1220_N are defective based on a certain logic process. ” [¶0034]
Claim 10 is rejected over Kim, Patel and Nossenson.
Kim teaches “wherein the cache controller is operable to: maintain, within storage of the cache controller, a record of the latencies to use for communicating with each of the plurality of storage circuits; and set the latencies based on the record.” as “The wafer level test may correspond to a test on an individual semiconductor die at a wafer level.” [¶0023] and “in the plurality of delay circuits included in each of the first through N.sup.th delay chains 1213_21 through 1213_2N, the number of delay circuits through which the test inputs Input pass according to the above-described delay control signal may be adjusted, and based thereon, the delay amounts of the first through N.sup.th delay chains 1213_21 through 1213_2N may be set to be different from each other. ” [¶0036]
Claim 14 is rejected over Kim, Patel and Nossenson under the same rationale of rejection of claim 1.
Claim 18 is rejected over Kim, Patel and Nossenson under the same rationale of rejection of claim 10.
Claim 19 is rejected over Kim, Patel and Nossenson.
Kim does not explicitly teach wherein the cache controller is implemented on a same semiconductor die as a first storage circuit in the stacked storage array.
However, Patel teaches “wherein the cache controller is implemented on a same semiconductor die as a first storage circuit in the stacked storage array.” as “Any number of N level caches can be used. The next level cache, such as N level cache 212 (e.g., last level cache) and N level cache controller 210 can be in communication with and shared by caches of multiple processors, such as for example, caches of a CPU or GPU (not shown), which may be located on the same die,” [¶0030]
Claim 20 is rejected over Kim, Patel and Nossenson under the same rationale of rejection of claim 1.
Claim(s) 2, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] in further view of Nossenson et al. [US 2023/0106208 A1] and yet in further view of Dwork [US 6,615,378 B1].
Claim 2 is rejected over Kim, Patel and Nossenson and Dwork.
The combination of Kim, Patel and Nossenson does not explicitly teach wherein the cache controller is further operable to set the latencies to cause a different response latency between two or more storage circuits of the plurality of storage circuits based on different characteristics of the two or more storage circuits.
However, Dwork teaches “wherein the cache controller is further operable to set the latencies to cause a different response latency between two or more storage circuits of the plurality of storage circuits based on different characteristics of the two or more storage circuits.” as “When a different type of SRAM is used, such as a zero byte turnaround SRAM, the latency concerns may be different.” [Col 9, lines 19-21]
Kim, Patel and Nossenson and Dwork are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel and Nossenson and Dwork before him/her, to modify the teachings of combination of Kim, Patel and Nossenson to include the teachings of Dwork with the motivation of it is advantageous for the network interface controller to incorporate a large amount of storage. [Dwork, Col 1, lines 34-35]
Claim 15 is rejected over Kim, Patel and Nossenson and Dwork under the same rationale of rejection of claim 2.
Claim 16 is rejected over Kim, Patel and Nossenson and Dwork.
Kim teaches “wherein the different characteristics include different stack positions within the stacked storage array.” as “the timings of providing the test inputs may be set differently depending on positions of the core dies 1420, or the timings of providing the test inputs may be set differently per channel for the first through eighth channels CH1 through CH8.” [¶0057] and “the delay amount of the test input for the first channel CH1 may be relatively less than the delay amount of the test input for the second channel CH2.” [¶0069]
Claim 17 is rejected over Kim, Patel and Nossenson and Dwork.
Kim teaches “wherein a second latency of a second storage circuit in the plurality of storage circuits is longer than a first latency of a first storage circuit in the plurality of storage circuits, and different than a last latency of a last storage circuit in the plurality of storage circuits.” as “the delay amount of the test input for the first channel CH1 may be relatively less than the delay amount of the test input for the second channel CH2.” [¶0069]
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] in further view of Nossenson et al. [US 2023/0106208 A1] and yet in further view of Gutierrez et al. [US 2022/0188208 A1].
Claim 9 is rejected over Kim, Patel, Nossenson and Gutierrez.
The combination of Kim, Patel and Nossenson does not explicitly teach wherein the cache controller is operable to: determine worst-case latencies for communicating with the plurality of storage circuits; and set the latencies to be the respective worst-case latencies.
However, Gutierrez teaches “wherein the cache controller is operable to: determine worst-case latencies for communicating with the plurality of storage circuits; and set the latencies to be the respective worst-case latencies.” as “Since the memory dies 411-415 are connected to the logic die 403 via signal pathways having different lengths, the memory stack 400 is designed to accommodate the worst-case latency to ensure a uniform view of all dies in the stack.” [¶0038]
Kim, Patel, Nossenson and Gutierrez are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel, Nossenson and Gutierrez before him/her, to modify the teachings of combination of Kim, Patel, Nossenson to include the teachings of Gutierrez with the motivation of when the cache capacity is increased, a snooping based coherency mechanism is used. At normal temperatures, when the cache capacity is smaller, a probe filter mechanism is used. [Gutierrez, ¶0047]
Claim(s) 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] in further view of Nossenson et al. [US 2023/0106208 A1] and yet in further view of Balakrishnan et al. [US 2010/0275049 A1].
Claim 21 is rejected over Kim, Patel, Nossenson and Balakrishnan.
The combination of Kim, Patel, Nossenson does not explicitly teach wherein the storage array is a cache for the processor, and the cache controller controls processor access to data located at the cache.
However, Balakrishnan teaches “wherein the storage array is a cache for the processor, and the cache controller controls processor access to data located at the cache.” as “A cache memory is a very fast buffer comprising an array of local storage cells used by one or more processors to hold frequently requested copies of data.” [¶0002]
Kim, Patel, Nossenson and Balakrishnan are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel, Nossenson and Balakrishnan before him/her, to modify the teachings of combination of Kim, Patel and Nossenson to include the teachings of Balakrishnan with the motivation of having the benefit of this disclosure, will realize that the present disclosure contemplates conserving power in non-uniform cache access (NUCA) caches by sequentially turning off groups of banks according to a hierarchy of increasing access latencies. [Balakrishnan, ¶0080]
Claim 22 is rejected over Kim, Patel, Nossenson and Balakrishnan under the same rationale of rejection of claim 21.
Claim 23 is rejected over Kim, Patel, Nossenson and Balakrishnan under the same rationale of rejection of claim 21.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. [US 2020/0049767 A1] in view of Patel et al. [US 2021/0406177 A1] in further view of Nossenson et al. [US 2023/0106208 A1] and yet in further view of Butcher et al. [US 2019/0004971 A1].
Claim 24 is rejected over Kim, Patel, Nossenson and Butcher.
The combination of Kim, Patel, Nossenson does not explicitly teach wherein the cache controller delays output of the response to the processor by checking an interconnect of the stack of dies for the response after waiting for the latency set for the corresponding storage circuit that provides the response.
However, Butcher teaches “wherein the cache controller delays output of the response to the processor by checking an interconnect of the stack of dies for the response after waiting for the latency set for the corresponding storage circuit that provides the response.” as “the timing analysis may reveal that a latency between cache controller 311 and I/O device 334 is as long as the latency between the cache controller and DIMM 352 connected to processor die 350, and so, BIOS/UEFI 390 can store a proximity number of 3 in the associated correlation between the cache controller and the I/O device, instead of storing the proximity number of 4, to show that the latency is approximately the same as for transactions with the DIMM.” [¶0035]
Kim, Patel, Nossenson and Butcher are analogous arts because they teach memory architecture and storage system control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kim, Patel, Nossenson and Butcher before him/her, to modify the teachings of combination of Kim, Patel and Nossenson to include the teachings of Butcher with the motivation of handling system may be configured to provide an optimal level of system performance at a minimum cost, and so my be configured with only one DIMM module per memory channel, leaving 1-3 DIMM sockets unpopulated and available for future expansion. [Butcher, ¶0029]
Allowable Subject Matter
Claims 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, considered individually and in combination, fails to teach or suggest a cache controller that sets a response timer based on a latency specifically assigned to the corresponding storage circuit providing a response, checks for that response upon expiration of the response timer, and outputs the response to the processor after waiting for the assigned latency without waiting for responses from the other storage circuits to become ready.
Although Kim et al. [US 2020/0049767 A1], Patel et al. [US 2021/0406177 A1] and Nossenson et al. [US 2023/0106208 A1] generally disclose cache or storage-system techniques involving memory access, latency, or the handling of responses, the cited references do not disclose the claimed coordinated response mechanism in which different storage circuits may have respective predetermined latencies and the cache controller uses the latency associated with the particular responding storage circuit both to time the response check and to determine when that circuit’s response may be independently forwarded to the processor. In particular, the references do not teach forwarding an available response after expiration of a storage-circuit-specific latency while intentionally proceeding without synchronization with, or waiting for, responses from the other storage circuits.
Accordingly, the particular combination of storage-circuit-specific response timing and independent response output recited in the claims is neither taught nor suggested by Kim et al., Patel et al., or Nossenson et al., alone or in any combination. This arrangement permits the cache controller to accommodate differing response latencies among the plurality of storage circuits while avoiding delay attributable to slower or otherwise unready storage circuits. Therefore, the foregoing limitations, in combination with the remaining limitations of the claims, are considered to distinguish the claimed invention over the prior art of record.
Response to Arguments
Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
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