DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08/26/2026 have been fully considered but they are not persuasive. Examiner believes that the previously cited prior art reads on the amended claims (though the previously cited matching and analysis will be changed):
1. “groove” in Claim 1, at least to examiner, is too open-ended (with very few details about the groove structure/shape or purpose) and can be interpreted broadly. Examiner, in the last rejection, was using the leftward U-shape (around 23a) in US20220262759 as the groove. The foam layer and configuring the foam layer is already disclosed in the secondary reference in similar form to the application drawings so rejection would be obvious. Similarly, the structure reinforcing component is disclosed is in the first reference. The term “located between” is broad (other direction/axes/position than intended are possible” and is not treated as “directly between” or “stacked between” or “directly adjacent and touching”).
2. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Also, it has been held that rearranging parts of an invention involved only routine skill in the art. In re Japikse, 86 USPQ 70 (CCPA 1950). Since the reference disclose the structural limitations and rearranging parts of the invention is routine/obvious, examiner believes that the above references would disclose the claimed subject matter.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuchida (US20220262759).
Regarding Claim 21. (New) Tsuchida teaches, in Fig. 3A, an electronic assembly, comprising: a substrate (17); a chip (11), configured on the substrate; a cover component (50), configured on the chip; a capacitance element (16), configured on the substrate; and a sealing structure (33,15), surrounding the chip, and sealing a gap between the cover component and the substrate (Fig.3A ),wherein the sealing structure comprises an insulating gel ([0046], 15), and the insulating gel encapsulates the capacitance element (Fig. 3A), wherein the electronic assembly further comprises a structure reinforcing component (14), the structure reinforcing component is supported between the substrate and the cover component (see Fig. 3A,3B), and the insulating gel is located between (in the X1 direction) the chip and the structure reinforcing component (see Fig. 3A).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida (US20220262759).
Regarding Claim 1. Tsuchida teaches, in Fig.1A-9B, an electronic assembly, comprising: a substrate (17); a chip (11), configured on the substrate (Fig. 1A-9B); a cover component (50), configured on the chip (Fig. 1A-9B); a capacitance element (16), configured on the substrate (17); and a sealing structure (33,15), surrounding the chip (Fig. 1A-9B), and sealing a gap between the cover component and the substrate (see Fig. 1A-9B), wherein the sealing structure comprises an insulating gel ([0046], 15), and the insulating gel encapsulates the capacitance element (see Fig. 1A-9B); but does not disclose a groove is formed between the insulating gel and the chip.
However, Tsuchida teaches, under BRI, a groove (left U-shape area formed by 23a or E1 in Fig. 5B) is formed between the insulating gel (115M) and the chip (11) (see Tsuchida, Fig. 8).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified an electronic assembly embodiment as disclosed by Tsuchida with another electronic assembly embodiment as disclosed by Tsuchida in order to reduce the amount of insulating material needed while providing appropriate adhesion of the insulating sheet to the substrate as it is known in the art.
Regarding Claim 5. Tsuchida teaches, in Fig. 1A-9B, the electronic assembly according to claim 1, further comprising a structure reinforcing component (Tsuchida, 14), wherein the structure reinforcing component is supported between the substrate (Tsuchida, 17) and the cover component (Tsuchida, 50), and the insulating gel is located between (in the X1 direction) the chip and the structure reinforcing component. (Tsuchida, Fig. 1A-9B).
Regarding Claim 6. Tsuchida teaches the electronic assembly according to claim 5, wherein a groove (Tsuchida, see Claim 1) is formed between the insulating gel (Tsuchida, 115M) and the structure reinforcing component (Tsuchida,14) (see Fig. 5B).
Regarding Claim 7. Tsuchida teaches the electronic assembly according to claim 1, further comprising a liquid metal layer (Tsuchida, 31), wherein the liquid metal layer is configured between the chip (Tsuchida, 11) and the cover component (Tsuchida, 50).
Regarding Claim 8. Tsuchida teaches the electronic assembly according to claim 1, wherein the insulating gel is a light-curable gel or a heat-curable gel (Tsuchida, 115M, [0073], [0042]).
Regarding Claim 9. Tsuchida teaches the electronic assembly according to claim 1, wherein the cover component is a heat sink (Tsuchida, 50).
Regarding Claim 10. Tsuchida teaches the electronic assembly according to claim 1, wherein the insulating gel is a removable gel (implicit as all gel can be removable provided with the right methods).
Claim(s) 1-3 and 11, 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stuck (US5977621) in view of Tsuchida (US20220262759).
Regarding Claim 1. Stuck teaches, in Fig. 1-2, an electronic assembly, comprising: a substrate (11); a chip (6), configured on the substrate (see Fig. 1-2); a cover (4) component, configured on the chip; and a sealing structure (10,9), surrounding the chip, and sealing a gap between the cover component and the substrate, wherein the sealing structure comprises an insulating gel (10), and the insulating gel encapsulates the capacitance element (when combined), but does not teach a capacitance element, configured on the substrate.
Tsuchida teaches, in Fig. 1A-9B, a capacitance element (16), configured on the substrate (17) (see Tsuchida, Fig. 8) and, under BRI, a groove (left U-shape area formed by 23a or E1 in Fig. 5B) is formed between the insulating gel (115M) and the chip (11).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the electronic assembly as disclosed by Stuck with the capacitance element as disclosed by Tsuchida in order for the capacitor perform the necessary filtering functions of signal transmission as it is known in the art.
Regarding Claim 11. Stuck teaches, in Fig.1-2, a manufacturing method of an electronic assembly, comprising: providing a substrate (11), wherein a chip (6) is provided on the substrate (see ; providing a sealing structure (10,9) on the substrate to surround the chip; and configuring a cover component (4) on the chip, so that the sealing structure seals a gap between the cover component and the substrate (see Fig.1-2), wherein the sealing structure comprises an insulating gel (9) and the sealing structure further comprises a foam layer (Stuck, 9), and the step of providing the sealing structure further comprises: configuring the foam layer on the insulating gel (Stuck, Fig. 1-2) such that the foam layer surrounds the chip (the prior art placement of the foam layer is similar to placement of the foam layer in Fig. 1 of the application, so examiner believes that the limitation is met), but does not teach a capacitance element are provided on the substrate and the step of providing the sealing structure comprises: encapsulating the capacitance element using the insulating gel; and defining a shape of the insulating gel by a jig and curing the insulating gel.
Tsuchida teaches, in Fig. 1A-9B, a capacitance element (16) are provided on the substrate (17) and the step of providing the sealing structure comprises: encapsulating the capacitance element using the insulating gel (see Fig. 1A-9B); and defining a shape of the insulating gel by a jig (not described but 15 has a unique shape so can be done by a jig- see MPEP 2144.01 in order to set the height lower than the chip so that the chip can be properly adhered to the cover and provide proper thermal conductivity as it is known in the art (see also [0095]) and curing the insulating gel ([0042]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the electronic assembly as disclosed by Stuck with the capacitance element as disclosed by Tsuchida in order for the capacitor perform the necessary filtering functions of signal transmission as it is known in the art.
Regarding Claim 2. Stuck and Tsuchida teaches the electronic assembly according to claim 1, wherein the sealing structure further comprises a foam layer (Stuck, 9), and the foam layer is configured between the insulating gel and the cover component (Stuck, Fig. 1-2).
Regarding Claim 3. Stuck and Tschuida teaches the electronic assembly according to claim 2, wherein the sealing structure further comprises an insulating film (Tsuchida, 225), and the insulating film is configured between the foam layer (Stuck ,9) and the cover component (50) (when combined, the order will be met).
Regarding Claim 13. Stuck and Tschuida teaches the manufacturing method of the electronic assembly according to claim 12, wherein the sealing structure further comprises an insulating film (Tsuchida, 225), and the step of providing the sealing structure further comprises: configuring the insulating film on the foam layer (Stuck, 9) (when combined, the order will be met).
Regarding Claim 14. Stuck and Tschuida teaches the manufacturing method of the electronic assembly according to claim 11, but does not directly teach forming a (defined) groove between the insulating gel and the chip.
However, Tsuchida teaches, under BRI, a groove (left U-shape area formed by 23a or E1 in Fig. 5B) is formed between the insulating gel (115M) and the chip (11) (see Tsuchida, Fig. 8).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified an electronic assembly embodiment as disclosed by Tsuchida with another electronic assembly embodiment as disclosed by Tsuchida in order to act as an adhesive to adhere structures to the substrate as it is known in the art.
Regarding Claim 15. Stuck and Tschuida teaches the manufacturing method of the electronic assembly according to claim 11, wherein a structure reinforcing component (Tsuchida, 14) is provided on the substrate (Tsuchida, 17), and the manufacturing method further comprises: supporting the structure reinforcing component to be between the substrate and the cover component (Tsuchida, 50), and making the insulating gel be located between (in the X1 direction) the chip and the structure reinforcing component (Tsuchida, Fig. 1A-9B) (see also Claim 21 rejection).
Regarding Claim 16. Stuck and Tschuida teaches the manufacturing method of the electronic assembly according to claim 15, further comprising: forming a groove (Tsuchida, left U-shape area formed by 23a or E1 in Fig. 5B) between the insulating gel (Tsuchida, 115M) and the structure reinforcing component (Tsuchida,14, not directly shown but forming a groove is a well-known step in manufacturing electronics devices) (see also claim 6 rejection) (see Fig. 5b).
Regarding Claim 17. Stuck and Tschuida teaches the manufacturing method of the electronic assembly according to claim 11, further comprising: configuring a liquid metal layer (Tsuchida, 31) on the chip (Tsuchida, 11), before configuring the cover component (Tsuchida, 50) on the chip (based on the verticality/top position, limitations is shown if not directly).
Regarding Claim 18. Stuck and Tschuida teaches the manufacturing method of the electronic assembly according to claim 11, wherein the step of curing the insulating gel comprises: light curing the insulating gel or heat curing the insulating gel (Tsuchida, 115M, [0073]).
Regarding Claim 19. Stuck and Tschuida teaches the manufacturing method of the electronic assembly according to claim 11, wherein the cover component is a heat sink (Tsuchida, 50).
Regarding Claim 20. Stuck and Tschuida teaches the manufacturing method of the electronic assembly according to claim 11, wherein the insulating gel is a removable gel (implicit as all gel can be removable provided with the right methods).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is presented in the Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMED AZAM whose telephone number is (571)270-0593. The examiner can normally be reached Mon-Fri 11:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MA/Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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