DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 7/23/26, which has been entered.
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 7/23/26, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dolan (US 8935493) in view of Wang (US 20220138156).
With respect to claim 1, the Dolan reference teaches a tiered memory device, comprising:
a first memory; (e.g. fig. 8a, tier A)
a second memory; (e.g. fig. 8a, tier B)
a monitoring circuit (e.g. fig. 3; and column 11, line 55 to column 12, line 14, where the service processor 22a uses performance data monitoring software 134 which gathers performance data about the data storage system 12 through the connection 132. The performance data monitoring software 134 gathers and stores performance data and forwards this to the optimizer 138) to monitor the first memory to generate a heat map and a miss map based at least in part on a request received from a processor; (column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation) and
a policy circuit to evict a first data from the first memory to the second memory and to prefetch a second data from the second memory to the first memory based at least in part on the heat map. (column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier; and column 23, line 53 to column 24, line 19, where data of the sequential stream may be pre-fetched from the physical device and placed in cache prior to usage in connection with a subsequent I/O operation. In connection with a portion of data at a first point in a sequential stream associated with a current I/O operation, data subsequent to the first point may be pre-fetched such as when obtaining the portion from a physical device in anticipation of future usage with subsequent I/Os.)
However, the Dolan reference does not explicitly teach the policy circuit to evict a first data from the first memory to the second memory and to prefetch a second data from the second memory to the first memory based at least in part on the miss map. (emphasis added)
The Wang reference teaches it is conventional to have the policy circuit to evict a first data from the first memory to the second memory and to prefetch a second data from the second memory to the first memory based at least in part on the miss map. (paragraph 74, where the caching and prefetching circuitry 802 uses information in the map stored in the example mapping storage 822 to determine how to categorize files and/or data for caching, evicting, and/or prefetching purposes. As further described below, the mapping storage 822 may include historical information related to how often and/or when a file and/or data was accessed and/or from where. For example, the example caching and prefetching circuitry 802 may use the historic data to determine which data to evict by selecting less relevant files (based on the historic data of the files). In another example, the caching and prefetching circuitry 802 may prefetch a first file (e.g., from storage on the cloud or the edge) when a second file is accessed when the caching and prefetching circuitry 802 determines that the first file is often accessed after a second file (e.g., based on the historic data of the first and second filed)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Dolan reference to have wherein the policy circuit to evict a first data from the first memory to the second memory and to prefetch a second data from the second memory to the first memory based at least in part on the miss map, as taught by the Wang reference.
The suggestion/motivation for doing so would have been to have the prefetching circuitry 816 and the cache circuitry 814 consider multiple aspects (e.g., parameters) and/or historical data from the map to determine whether to evict and/or promote data from one storage device to another. (Wang, paragraph 74)
Therefore it would have been obvious to combine the Dolan and Wang references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the Dolan and Wang references teaches the tiered memory device according to claim 1, wherein: the tiered memory device exposes an address range to the processor; the address range is divided into a first region and a second region based at least in part on a region size; the heat map includes a first heat information for the first region and a second heat for the second region; and the miss map includes a first miss information for the first region and a second miss for the second region. (Dolan, column 22, lines 46-65, where example 250 includes a thin device address space or range 252 which, as described elsewhere herein, includes chunks mapped to physical storage locations. The thin device address space or range 252 may be partitioned into one or more extents 254a-254n; and column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation; and Wang, paragraph 74, where the caching and prefetching circuitry 802
uses information in the map stored in the example mapping storage 822 to determine how to categorize files and/or data for caching, evicting, and/or prefetching purposes. As further described below, the mapping storage 822 may include historical information related to how often and/or when a file and/or data was accessed and/or from where. For example, the example caching and prefetching circuitry 802 may use the historic data to determine which data to evict by selecting less relevant files (based on the historic data of the files). In another example, the caching and prefetching circuitry 802
may prefetch a first file (e.g., from storage on the cloud or the edge) when a second file is accessed when the caching and prefetching circuitry 802 determines that the first file is often accessed after a second file (e.g., based on the historic data of the first and second filed)
With respect to claim 3, the Dolan and Wang references teaches the tiered memory device according to claim 1, wherein: the heat map includes a heat information regarding how often data is accessed by the processor; and the miss map includes a miss information regarding how often data is requested by the processor but is absent from the first memory. (Dolan, column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation; and Wang, paragraph 74, where the caching and prefetching circuitry 802 uses information in the map stored in the example mapping storage 822 to determine how to categorize files and/or data for caching, evicting, and/or prefetching purposes. As further described below, the mapping storage 822 may include historical information related to how often and/or when a file and/or data was accessed and/or from where. For example, the example caching and prefetching circuitry 802 may use the historic data to determine which data to evict by selecting less relevant files (based on the historic data of the files). In another example, the caching and prefetching circuitry 802 may prefetch a first file (e.g., from storage on the cloud or the edge) when a second file is accessed when the caching and prefetching circuitry 802 determines that the first file is often accessed after a second file (e.g., based on the historic data of the first and second filed)
With respect to claim 4, the Dolan and Wang references teaches the tiered memory device according to claim 1, wherein the monitoring circuit is configured to update the heat map and the miss map periodically. (Dolan, column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation; and column 27, lines 10-27, where the long term rates 330 may be included the long term information 304 where such long term rates 330 may be updated with each sampling period. In one embodiment with the arrival of a new sampling period "n", the long term information 304 may include Ar values for the foregoing statistics as determined using EQUATION 3 for a sampling period "n-1")
With respect to claim 5, the Dolan and Wang references teaches a method, comprising:
determining, using a monitoring circuit of a tiered memory device, (Dolan, e.g. fig. 3; and service processor 22a is performance data monitoring software 134 which gathers performance data about the data storage system 12 through the connection 132. The performance data monitoring software 134 gathers and stores performance data and forwards this to the optimizer 138) an access count for a first memory of the tiered memory device, the tiered memory device including the first memory and a second memory, wherein the access count counts how often the first memory of the tiered memory device is read or written; (column 23, lines 1-61, where , the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation; and column 26, where an embodiment may collect short term information 302 as counter values indicating a count or number of each type of operation for a current time period or sampling period "n". The following may represent different "a.sub.n" values as included in the short term information 302 for an extent: read miss count (number of read misses for the extent during the sampling period), pre-fetch count (number of pre-fetches for the extent during the sampling period) and write count (number of writes for the extent during the sampling period)
determining, using the monitoring circuit of the tiered memory device, a miss count for the first memory of the tiered memory device; (Dolan, column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation)
calculating, using the monitoring circuit of the tiered memory device, a heat information for the first memory of the tiered memory device based at least in part on the access count; (Dolan, column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier;
calculating, using the monitoring circuit of the tiered memory device, a miss information for the first memory of the tiered memory device based at least in part on the miss count; (Dolan, column 23, lines 1-61, where , the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation) and
providing the heat information and the miss information to a policy circuit associated with the tiered memory device. (Dolan, column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier)
With respect to claim 6, the Dolan and Wang references teaches the method according to claim 5, wherein: calculating, using the monitoring circuit of the tiered memory device, the heat information for the first memory of the tiered memory device based at least in part on the access count includes calculating, using the monitoring circuit of the tiered memory device, the heat information for the first memory of the tiered memory device based at least in part on the access count and an average access rate, wherein the average access rate measures an average rate of reads or writes of the first memory of the tiered memory device; and calculating, using the monitoring circuit of the tiered memory device, the miss information for the first memory of the tiered memory device based at least in part on the miss count includes calculating, using the monitoring circuit of the tiered memory device, the miss information for the first memory of the tiered memory device based at least in part on the miss count and an average miss rate. (Dolan, column 19, line 44 to column 20, line 20, where for each TD, and/or portions thereof, an average number of reads occurring within a given time period may be determined, an average number of writes occurring within a given time period may be determined, an average number of read misses occurring within a given time period may be determined, and the like. It should be noted that the operations of read and write with respect to a TD may be viewed as read and write requests or commands from the DA, controller or other backend physical device interface; and column 23, lines 1-61, where , the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation)
With respect to claim 7, the Dolan and Wang references teaches the method according to claim 6, wherein: calculating, using the monitoring circuit of the tiered memory device, the heat information for the first memory of the tiered memory device based at least in part on the access count and an average access rate includes applying a first weight to the access count and a second weight to an average access rate, wherein the average access rate measures an average rate of reads or writes of the first memory of the tiered memory device; and calculating, using the monitoring circuit of the tiered memory device, the miss information for the first memory of the tiered memory device based at least in part on the miss count and an average miss rate includes applying a third weight to the miss count and a fourth weight to an average miss rate. (Dolan, column 19, line 44 to column 20, line 20, where for each TD, and/or portions thereof, an average number of reads occurring within a given time period may be determined, an average number of writes occurring within a given time period may be determined, an average number of read misses occurring within a given time period may be determined, and the like. It should be noted that the operations of read and write with respect to a TD may be viewed as read and write requests or commands from the DA, controller or other backend physical device interface; and Dolan, column 37, lines 51-67, where an embodiment may select values for coefficients or weights P7-P12 when determining various promotion and demotion scores in connection with following techniques based on the target storage tier. The target storage tier may be the tier for which processing is performed to select data portions for movement to the target tier)
With respect to claim 9, the Dolan and Wang references teaches the method according to claim 5, further comprising: receiving, at a controller of the tiered memory device, an access request from a processor; incrementing, by the monitoring circuit, the access count based at least in part receiving the access request from the processor, the access request requesting to read or write data from the tiered memory device; and incrementing, by the monitoring circuit, the miss count based at least in part on a data requested by the access request being in the first memory of the tiered memory device. (Dolan, column 19, line 44 to column 20, line 20, where for each TD, and/or portions thereof, an average number of reads occurring within a given time period may be determined, an average number of writes occurring within a given time period may be determined, an average number of read misses occurring within a given time period may be determined, and the like. It should be noted that the operations of read and write with respect to a TD may be viewed as read and write requests or commands from the DA, controller or other backend physical device interface; Dolan, column 28, where as an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3)
With respect to claim 10, the Dolan and Wang references teaches the method according to claim 9, wherein: receiving, at the controller of the tiered memory device, the access request from a processor includes determining a region identifier for a first region in the first memory of the tiered memory device based at least in part on the access request, the first memory including the first region and a second region; incrementing, by the monitoring circuit, the access count based at least in part receiving the access request from the processor includes incrementing, by the monitoring circuit, a first access count associated with the region identifier associated with the first region in the first memory of the tiered memory device based at least in part on receiving the access request from the processor; and incrementing, by the monitoring circuit, the miss count based at least in part on a data requested by the access request being in the first memory includes incrementing, by the monitoring circuit, a first miss count associated with the region identifier associated with the first region in the first memory of the tiered memory device based at least in part on the data requested by the access request being in the first region in first memory of the tiered memory device. (Dolan, column 64, where for obtaining the baseline RTs, the read I/Os may be based on a predetermined pattern such as proximity in logical addresses between consecutive I/Os which causes cache hits on the data storage systems. Issuing consecutive I/Os to read data from the same logical address on the LUN may result, for example, in an initial cache miss on the data storage system for the first read thereby causing the read data to be brought into cache from physical storage. The second and subsequent reads to the same logical address are expected to be cache hits whereby the read is serviced using the cached copy of the data. Thus, in such a manner, the read operations issued in connection with obtaining baseline RTs may be based on I/Os having a predetermined pattern which are expected to result in cache hits after the first read request in such an embodiment of the data storage system that performs data caching)
With respect to claim 11, the Dolan and Wang references teaches the method according to claim 10, wherein: the first region includes a first set of addresses exposed to the processor by the tiered memory device; the second region includes a second set of addresses exposed to the processor by the tiered memory device; and the first set of addresses is distinct from the second set of addresses. (Dolan, column 65, lines 1-33, where above-mentioned adjusted RT for a LUN representing the difference in RT values (e.g., between the baseline RT and RT in the second set) may then be used to assign a performance classification to the LUN thereby representing the performance classification of the underlying PDs configured to stored the LUN's data. For example, consider an embodiment having three storage tiers as the performance classifications as described above in connection with FIG. 20)
With respect to claim 12, the Dolan and Wang references teaches the method according to claim 5, further comprising resetting the access count and the miss count based at least in part on calculating the heat information for the first memory of the tiered memory device and the miss information for the first memory of the tiered memory device. (Dolan, column 104, lines 45-59, where an embodiment may provide for user configurable parameters for setting and/or resetting such attributes for any source and/or target entity)
With respect to claim 13, the Dolan and Wang references teaches the method according to claim 5, wherein: calculating, using the monitoring circuit of the tiered memory device, the heat information for the first memory of the tiered memory device based at least in part on the access count includes: calculating an average access rate for the first memory of the tiered memory device based at least in part on the access count; and calculating the heat information for the first memory of the tiered memory device from the average access rate for the first memory of the tiered memory device wherein the average access rate measures an average rate of reads or writes of the first memory of the tiered memory device; and calculating, using the monitoring circuit of the tiered memory device, the miss information for the first memory of the tiered memory device based at least in part on the miss count includes: calculating an average miss rate for the first memory of the tiered memory device based at least in part on the miss count; and calculating the miss information for the first memory of the tiered memory device from the average miss rate for the first memory of the tiered memory device. (Dolan, column 19, line 44 to column 20, line 20, where for each TD, and/or portions thereof, an average number of reads occurring within a given time period may be determined, an average number of writes occurring within a given time period may be determined, an average number of read misses occurring within a given time period may be determined, and the like. It should be noted that the operations of read and write with respect to a TD may be viewed as read and write requests or commands from the DA, controller or other backend physical device interface; and column 19, line 44 to column 20, line 20, where for each TD, and/or portions thereof, an average number of reads occurring within a given time period may be determined, an average number of writes occurring within a given time period may be determined, an average number of read misses occurring within a given time period may be determined, and the like. It should be noted that the operations of read and write with respect to a TD may be viewed as read and write requests or commands from the DA, controller or other backend physical device interface)
With respect to claim 14, the Dolan and Wang references teaches the method according to claim 13, wherein: calculating the heat information for the first memory of the tiered memory device from the average access rate for the first memory of the tiered memory device includes calculating the heat information for the first memory of the tiered memory device based at least in part on comparing the average access rate for the first memory of the tiered memory device against a first threshold; and calculating the miss information for the first memory of the tiered memory device from the average miss rate for the first memory of the tiered memory device includes calculating the miss information for the first memory of the tiered memory device based at least in part on comparing the average miss rate for the first memory of the tiered memory device against a second threshold. (Dolan, column 21, lines 4-24, where such evaluation may be performed in connection with determining promotion/demotion thresholds use in evaluating where to locate and/or move data of the different chunks with respect to the different storage tiers in a multi-storage tier environment)
With respect to claim 15, the Dolan and Wang references teaches the method according to claim 5, further comprising prefetching, by the policy circuit, a data from the second memory into the first memory based at least in part on the heat information for the first memory of the tiered memory device. (Dolan, column 23, line 53 to column 24, line 19, where data of the sequential stream may be pre-fetched from the physical device and placed in cache prior to usage in connection with a subsequent I/O operation. In connection with a portion of data at a first point in a sequential stream associated with a current I/O operation, data subsequent to the first point may be pre-fetched such as when obtaining the portion from a physical device in anticipation of future usage with subsequent I/Os.)
With respect to claim 16, the Dolan and Wang references teaches the method according to claim 5, further comprising determining a prefetch priority for a data from the second memory into the first memory based at least in part on the miss information for the first memory of the tiered memory device. (Dolan, column 23, line 53 to column 24, line 19, where data of the sequential stream may be pre-fetched from the physical device and placed in cache prior to usage in connection with a subsequent I/O operation. In connection with a portion of data at a first point in a sequential stream associated with a current I/O operation, data subsequent to the first point may be pre-fetched such as when obtaining the portion from a physical device in anticipation of future usage with subsequent I/Os.)
With respect to claim 17, the Dolan and Wang references teaches the method according to claim 5, further comprising evicting, by the policy circuit, a data from the first memory to the second memory based at least in part on the miss information for the first memory of the tiered memory device. (Dolan, column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier)
With respect to claim 18, the Dolan and Wang references teaches the method according to claim 5, further comprising determining an eviction priority for a data from the first memory to the second memory based at least in part on the heat information for the first memory of the tiered memory device. (Dolan, column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier;)
Claims 19-20 are the non-transitory storage medium implementation of claims 1-7 and 9-18, and rejected under the same rationale as shown in the rejections above.
3. ALLOWABLE SUBJECT MATTER
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 recites the limitations of:
“… the method further comprises:
determining an address range for the tiered memory device;
exposing the address range for the tiered memory device to a processor; and
identifying a first region and a second region in the address range based at least in part on a region size;
determining, using the monitoring circuit of the tiered memory device, the access count for the first memory of the tiered memory device includes determining, using the monitoring circuit of the tiered memory device, a first access count for the first region in the first memory of the tiered memory device and a second access count for the second region in the first memory of the tiered memory device, wherein the first access count counts how often the first region in the first memory of the tiered memory device is read or written, and wherein the second access count counts how often the second region in the first memory of the tiered memory device is read or written;
determining, using the monitoring circuit of the tiered memory device, a miss count for the first memory of the tiered memory device includes determining, using the monitoring circuit of the tiered memory device, a first miss count for the first region in the first memory of the tiered memory device and a second miss count for the second region in the first memory of the tiered memory device;
calculating, using the monitoring circuit of the tiered memory device, a heat information for the first memory of the tiered memory device based at least in part on the access count includes:
calculating, using the monitoring circuit of the tiered memory device, a first heat information for the first region in the first memory of the tiered memory device based at least in part on the first access count for the first region in the first memory of the tiered memory device; and
calculating, using the monitoring circuit of the tiered memory device, a second heat information for the second region in the first memory of the tiered memory device based at least in part on the second access count for the second region in the first memory of the tiered memory device; and
calculating, using the monitoring circuit of the tiered memory device, a miss information for the first memory of the tiered memory device based at least in part on the miss count includes:
calculating, using the monitoring circuit of the tiered memory device, a first miss information for the first region in the first memory of the tiered memory device based at least in part on the first miss count for the first region in the first memory of the tiered memory device; and
calculating, using the monitoring circuit of the tiered memory device, a second miss information for the second region in the first memory of the tiered memory device based at least in part on the second miss count for the second region in the first memory of the tiered memory device.
However, the closest prior art of record (cited above and below) does not explicitly teach or render obvious the limitations above, particularly in combination with the other limitations within the claims. The dependent claims are allowable for at least the same reasons as its respective independent claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
4. ARGUMENTS CONCERNING CLAIM INTERPRETATION
USC 112, 6th/f Interpretation
Applicant's arguments (see page 13 of the remarks) and amendments with respect to claims 1-4 have been considered, and are persuasive. Thus, the claim interpretation has been withdrawn in view of the amendments.
5. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 13-26) and amendments with respect to claims 1-7 and 9-20 have been considered have been fully considered, and some are persuasive. Therefore, some of the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the Wang reference to teach the amended claim language as recited in independent claims 1 and 19 (see pages 13-15 of the remarks).
The arguments pertaining to the dependent claims (see pages 16-26) have been considered. The Examiner notes that the updated citations of Dolan and Wang in the rejections above may address any arguments pertaining to the Applicant’s concerns. Further, the Examiner notes that applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references; and also applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections. Lastly, in response to applicant's arguments that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e. “miss map” in claim 2 from the applicant’s specification; “access counts” in claim 5 from the applicant’s specification; “access rate” in claim 6 from the application’s specification; and etc) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
6. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
