DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statements, dated 10/22/24, 4/8/25, 4/30/25, 10/7/25, and 12/27/25, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. CLAIM INTERPRETATION
USC 112, f/6th Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a policy engine to evict a first data from the first memory to the second memory and to prefetch a second data from the second memory to the first memory based at least in part on the heat map and the miss map” as recited in claims 1-4. As noted in the top of page 11 of the Applicant’s specification, the “policy engine” may be “implemented using a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), a System-on-a-Chip (SoC), a general processor, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a General Purpose GPU (GPGPU), a Tensor Processing Unit (TPU), or a Neural Processing Unit (NPU), among other possibilities” to perform the recited functions noted above.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
3. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 9-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dolan (US 8935493).
With respect to claim 1, the Dolan reference teaches a tiered memory device, comprising:
a first memory; (e.g. fig. 8a, tier A)
a second memory; (e.g. fig. 8a, tier B)
a monitoring circuit (e.g. fig. 3; and column 11, line 55 to column 12, line 14, where the service processor 22a uses performance data monitoring software 134 which gathers performance data about the data storage system 12 through the connection 132. The performance data monitoring software 134 gathers and stores performance data and forwards this to the optimizer 138) to monitor the first memory to generate a heat map and a miss map based at least in part on a request received from a processor; (column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation) and
a policy engine to evict a first data from the first memory to the second memory and to prefetch a second data from the second memory to the first memory based at least in part on the heat map and the miss map. (column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier; and column 23, line 53 to column 24, line 19, where data of the sequential stream may be pre-fetched from the physical device and placed in cache prior to usage in connection with a subsequent I/O operation. In connection with a portion of data at a first point in a sequential stream associated with a current I/O operation, data subsequent to the first point may be pre-fetched such as when obtaining the portion from a physical device in anticipation of future usage with subsequent I/Os.)
With respect to claim 2, the Dolan reference teaches the tiered memory device according to claim 1, wherein: the tiered memory device exposes an address range to the processor; the address range is divided into a first region and a second region based at least in part on a region size; the heat map includes a first heat information for the first region and a second heat for the second region; and the miss map includes a first miss information for the first region and a second miss for the second region. (column 22, lines 46-65, where example 250 includes a thin device address space or range 252 which, as described elsewhere herein, includes chunks mapped to physical storage locations. The thin device address space or range 252 may be partitioned into one or more extents 254a-254n; and column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation)
With respect to claim 3, the Dolan reference teaches the tiered memory device according to claim 1, wherein: the heat map includes a heat information regarding how often data is accessed by the processor; and the miss map includes a miss information regarding how often data is requested by the processor but is absent from the first memory. (column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation)
With respect to claim 4, the Dolan reference teaches the tiered memory device according to claim 1, wherein the monitoring circuit is configured to update the heat map and the miss map periodically. (column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation)
With respect to claim 5, the Dolan reference teaches a method, comprising:
determining, using a monitoring circuit of a tiered memory device, (e.g. fig. 3; and service processor 22a is performance data monitoring software 134 which gathers performance data about the data storage system 12 through the connection 132. The performance data monitoring software 134 gathers and stores performance data and forwards this to the optimizer 138) an access count for a first memory of the tiered memory device, the tiered memory device including the first memory and a second memory; (column 23, lines 1-61, where , the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation)
determining, using the monitoring circuit of the tiered memory device, a miss count for the first memory of the tiered memory device; (column 23, lines 1-61, where the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation)
calculating, using the monitoring circuit of the tiered memory device, a heat information for the first memory of the tiered memory device based at least in part on the access count; (column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier;
calculating, using the monitoring circuit of the tiered memory device, a miss information for the first memory of the tiered memory device based at least in part on the miss count; (column 23, lines 1-61, where , the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation) and
providing the heat information and the miss information to a policy engine associated with the tiered memory device. (column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier)
With respect to claim 6, the Dolan reference teaches the method according to claim 5, wherein: calculating, using the monitoring circuit of the tiered memory device, the heat information for the first memory of the tiered memory device based at least in part on the access count includes calculating, using the monitoring circuit of the tiered memory device, the heat information for the first memory of the tiered memory device based at least in part on the access count and an average access rate; and calculating, using the monitoring circuit of the tiered memory device, the miss information for the first memory of the tiered memory device based at least in part on the miss count includes calculating, using the monitoring circuit of the tiered memory device, the miss information for the first memory of the tiered memory device based at least in part on the miss count and an average miss rate. (column 19, line 44 to column 20, line 20, where for each TD, and/or portions thereof, an average number of reads occurring within a given time period may be determined, an average number of writes occurring within a given time period may be determined, an average number of read misses occurring within a given time period may be determined, and the like. It should be noted that the operations of read and write with respect to a TD may be viewed as read and write requests or commands from the DA, controller or other backend physical device interface; and column 23, lines 1-61, where , the short term rates 320 for an extent may include a read miss rate (e.g., random read miss (RRM) rate) 322, a write I/O rate 324 and a pre-fetch rate 326 for the extent. The long term rates 330 for an extent may include a read miss rate 332 (e.g., number of read misses/unit of time, where a read miss refers to a cache miss for a read), a write I/O rate 334 (e.g., number of writes/unit of time) and a pre-fetch rate 336 (e.g., number of pre-fetches/unit of time) for the extent. As known in the art, data may be pre-fetched from a physical device and placed in cache prior to reference or use with an I/O operation)
With respect to claim 7, the Dolan reference teaches the method according to claim 6, wherein: calculating, using the monitoring circuit of the tiered memory device, the heat information for the first memory of the tiered memory device based at least in part on the access count and an average access rate includes applying a first weight to the access count and a second weight to an average access rate; and calculating, using the monitoring circuit of the tiered memory device, the miss information for the first memory of the tiered memory device based at least in part on the miss count and an average miss rate includes applying a third weight to the miss count and a fourth weight to an average miss rate. (column 37, lines 51-67, where an embodiment may select values for coefficients or weights P7-P12 when determining various promotion and demotion scores in connection with following techniques based on the target storage tier. The target storage tier may be the tier for which processing is performed to select data portions for movement to the target tier)
With respect to claim 9, the Dolan reference teaches the method according to claim 5, further comprising: receiving, at a controller of the tiered memory device, an access request from a processor; incrementing, by the monitoring circuit, the access count based at least in part receiving the access request from the processor; and incrementing, by the monitoring circuit, the miss count based at least in part on a data requested by the access request being in the first memory of the tiered memory device. (column 28, where as an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3)
With respect to claim 10, the Dolan reference teaches the method according to claim 9, wherein: receiving, at the controller of the tiered memory device, the access request from a processor includes determining a region identifier for a first region in the first memory of the tiered memory device based at least in part on the access request, the first memory including the first region and a second region; incrementing, by the monitoring circuit, the access count based at least in part receiving the access request from the processor includes incrementing, by the monitoring circuit, a first access count associated with the region identifier associated with the first region in the first memory of the tiered memory device based at least in part on receiving the access request from the processor; and incrementing, by the monitoring circuit, the miss count based at least in part on a data requested by the access request being in the first memory includes incrementing, by the monitoring circuit, a first miss count associated with the region identifier associated with the first region in the first memory of the tiered memory device based at least in part on the data requested by the access request being in the first region in first memory of the tiered memory device. (column 64, where for obtaining the baseline RTs, the read I/Os may be based on a predetermined pattern such as proximity in logical addresses between consecutive I/Os which causes cache hits on the data storage systems. Issuing consecutive I/Os to read data from the same logical address on the LUN may result, for example, in an initial cache miss on the data storage system for the first read thereby causing the read data to be brought into cache from physical storage. The second and subsequent reads to the same logical address are expected to be cache hits whereby the read is serviced using the cached copy of the data. Thus, in such a manner, the read operations issued in connection with obtaining baseline RTs may be based on I/Os having a predetermined pattern which are expected to result in cache hits after the first read request in such an embodiment of the data storage system that performs data caching)
With respect to claim 11, the Dolan reference teaches the method according to claim 10, wherein: the first region includes a first set of addresses exposed to the processor by the tiered memory device; the second region includes a second set of addresses exposed to the processor by the tiered memory device; and the first set of addresses is distinct from the second set of addresses. (column 65, lines 1-33, where above-mentioned adjusted RT for a LUN representing the difference in RT values (e.g., between the baseline RT and RT in the second set) may then be used to assign a performance classification to the LUN thereby representing the performance classification of the underlying PDs configured to stored the LUN's data. For example, consider an embodiment having three storage tiers as the performance classifications as described above in connection with FIG. 20)
With respect to claim 12, the Dolan reference teaches the method according to claim 5, further comprising resetting the access count and the miss count based at least in part on calculating the heat information for the first memory of the tiered memory device and the miss information for the first memory of the tiered memory device. (column 104, lines 45-59, where an embodiment may provide for user configurable parameters for setting and/or resetting such attributes for any source and/or target entity)
With respect to claim 13, the Dolan reference teaches the method according to claim 5, wherein: calculating, using the monitoring circuit of the tiered memory device, the heat information for the first memory of the tiered memory device based at least in part on the access count includes: calculating an average access rate for the first memory of the tiered memory device based at least in part on the access count; and calculating the heat information for the first memory of the tiered memory device from the average access rate for the first memory of the tiered memory device; and calculating, using the monitoring circuit of the tiered memory device, the miss information for the first memory of the tiered memory device based at least in part on the miss count includes: calculating an average miss rate for the first memory of the tiered memory device based at least in part on the miss count; and calculating the miss information for the first memory of the tiered memory device from the average miss rate for the first memory of the tiered memory device. (column 19, line 44 to column 20, line 20, where for each TD, and/or portions thereof, an average number of reads occurring within a given time period may be determined, an average number of writes occurring within a given time period may be determined, an average number of read misses occurring within a given time period may be determined, and the like. It should be noted that the operations of read and write with respect to a TD may be viewed as read and write requests or commands from the DA, controller or other backend physical device interface)
With respect to claim 14, the Dolan reference teaches the method according to claim 13, wherein: calculating the heat information for the first memory of the tiered memory device from the average access rate for the first memory of the tiered memory device includes calculating the heat information for the first memory of the tiered memory device based at least in part on comparing the average access rate for the first memory of the tiered memory device against a first threshold; and calculating the miss information for the first memory of the tiered memory device from the average miss rate for the first memory of the tiered memory device includes calculating the miss information for the first memory of the tiered memory device based at least in part on comparing the average miss rate for the first memory of the tiered memory device against a second threshold. (column 21, lines 4-24, where such evaluation may be performed in connection with determining promotion/demotion thresholds use in evaluating where to locate and/or move data of the different chunks with respect to the different storage tiers in a multi-storage tier environment)
With respect to claim 15, the Dolan reference teaches the method according to claim 5, further comprising prefetching, by the policy engine, a data from the second memory into the first memory based at least in part on the heat information for the first memory of the tiered memory device. (column 23, line 53 to column 24, line 19, where data of the sequential stream may be pre-fetched from the physical device and placed in cache prior to usage in connection with a subsequent I/O operation. In connection with a portion of data at a first point in a sequential stream associated with a current I/O operation, data subsequent to the first point may be pre-fetched such as when obtaining the portion from a physical device in anticipation of future usage with subsequent I/Os.)
With respect to claim 16, the Dolan reference teaches the method according to claim 5, further comprising determining a prefetch priority for a data from the second memory into the first memory based at least in part on the miss information for the first memory of the tiered memory device. (column 23, line 53 to column 24, line 19, where data of the sequential stream may be pre-fetched from the physical device and placed in cache prior to usage in connection with a subsequent I/O operation. In connection with a portion of data at a first point in a sequential stream associated with a current I/O operation, data subsequent to the first point may be pre-fetched such as when obtaining the portion from a physical device in anticipation of future usage with subsequent I/Os.)
With respect to claim 17, the Dolan reference teaches the method according to claim 5, further comprising evicting, by the policy engine, a data from the first memory to the second memory based at least in part on the miss information for the first memory of the tiered memory device. (column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier)
With respect to claim 18, the Dolan reference teaches the method according to claim 5, further comprising determining an eviction priority for a data from the first memory to the second memory based at least in part on the heat information for the first memory of the tiered memory device. (column 28, lines 39-51, where as an example use of the activity bitmap is in connection with promotion and demotion [i.e. ‘evict a first data’ as claimed]. As an example use of the activity bitmap, the bitmap may be used to determine selective sub extents which exhibit the highest activity level such as those having counters=3 (e.g., "hot" or active areas of the extent). These sub extents may be candidates for promotion or data movement to a higher performing storage tier and may be given preference for such promotion and data movement over other sub extents having activity bitmap entries which are less than 3. In a similar manner, the activity bitmap may be used to identify the "coldest" or inactive sub extents. For example, sub extents having bit map entries=0 may be candidates for demotion to a lower performing storage tier;
Claims 19-20 are the non-transitory storage medium implementation of claims 5-7 and 9-18, and rejected under the same rationale as shown in the rejections above.
4. ALLOWABLE SUBJECT MATTER
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 recites the limitations of:
“… the method further comprises:
determining an address range for the tiered memory device;
exposing the address range for the tiered memory device to a processor; and
identifying a first region and a second region in the address range based at least in part on a region size;
determining, using the monitoring circuit of the tiered memory device, the access count for the first memory of the tiered memory device includes determining, using the monitoring circuit of the tiered memory device, a first access count for the first region in the first memory of the tiered memory device and a second access count for the second region in the first memory of the tiered memory device;
determining, using the monitoring circuit of the tiered memory device, a miss count for the first memory of the tiered memory device includes determining, using the monitoring circuit of the tiered memory device, a first miss count for the first region in the first memory of the tiered memory device and a second miss count for the second region in the first memory of the tiered memory device;
calculating, using the monitoring circuit of the tiered memory device, a heat information for the first memory of the tiered memory device based at least in part on the access count includes:
calculating, using the monitoring circuit of the tiered memory device, a first heat information for the first region in the first memory of the tiered memory device based at least in part on the first access count for the first region in the first memory of the tiered memory device; and
calculating, using the monitoring circuit of the tiered memory device, a second heat information for the second region in the first memory of the tiered memory device based at least in part on the second access count for the second region in the first memory of the tiered memory device; and
calculating, using the monitoring circuit of the tiered memory device, a miss information for the first memory of the tiered memory device based at least in part on the miss count includes:
calculating, using the monitoring circuit of the tiered memory device, a first miss information for the first region in the first memory of the tiered memory device based at least in part on the first miss count for the first region in the first memory of the tiered memory device; and
calculating, using the monitoring circuit of the tiered memory device, a second miss information for the second region in the first memory of the tiered memory device based at least in part on the second miss count for the second region in the first memory of the tiered memory device.
However, the closest prior art of record (cited above and below) does not explicitly teach or render obvious the limitations above, particularly in combination with the other limitations within the claims. The dependent claims are allowable for at least the same reasons as its respective independent claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
5. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
NATHELLA (US 20220413866), which teaches in response to an instruction decoder decoding a range prefetch instruction specifying first and second address-range-specifying parameters and a stride parameter, prefetch circuitry controls, depending on the first and second address-range-specifying parameters and the stride parameter, prefetching of data from a plurality of specified ranges of addresses into the at least one cache. A start address and size of each specified range is dependent on the first and second address-range-specifying parameters. The stride parameter specifies an offset between start addresses of successive specified ranges. Use of the range prefetch instruction helps to improve programmability and improve the balance between prefetch coverage and circuit area of the prefetch circuitry;
Booss (US 20180150222), which teaches a system for allocating memory (e.g., heap) in multi-core processors is provided. In some implementations, the system performs operations comprising receiving, at a shared cache having a plurality of segments, a first data allocation including a plurality of data blocks, and allocating at least a first and second data block from the first allocation. First and second segments in the shared cache can each comprise a plurality of data slots (e.g., of equal length). Allocating the first and second data blocks can include storing the first data block in a data slot of the first segment and storing the second data block in a data slot of the second segment. The plurality of data slots which do not contain data may contain padding, and/or the data slots to which the first and second data blocks are allocated are not adjacent. Related systems, methods, and articles of manufacture are also described; and
Vaswani (US 20080005208), which teaches providing data structure path profiling. An instrumented version of a program is created that calls a profiler runtime when pointer based data structures are allocated or accessed via pointers. A model of the heap is created and nodes in the model data structures are assigned unique identifiers. Paths traversed through the model data structures are assigned unique identifiers. The paths are counted in order to identify paths through the data structure model that are traversed frequently. The model is useful for providing information about high frequency data paths to the program developer and for various optimization purposes, such as prefetching and or increasing data locality during garbage collection.
6. CLOSING COMMENTS
Conclusion
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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