DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on July 11, 2023. It is noted, however, that applicant has not filed a certified copy of the 10-2023-0090103 application as required by 37 CFR 1.55.
Although the access code was provided with the application, as indicated on the filing receipt, the document was unable to be retrieved under the priority document exchange program.
Information Disclosure Statement
The information disclosure statement (IDS) filed on June 28, 2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is a possible suggestion: Semiconductor Package With Specific Electrical Configuration of Option, Power and Ground, and Connecting Pads and Bumps.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 13-19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "a wire" in line 3, where “a wire” has already been introduced in Claim 1 line 9 and it is unclear if the “a wire” of Claim 2 is a different or same wire as previously introduced in Claim 1 which connects the option pad and the power/ground pad. For examination purposes, Claim 2 has been interpreted as follows based on FIG. 1 and paragraph [0042] of the instant specification:
Claim 2: The semiconductor package of Claim 1, further comprising: a first connecting pad which is spaced apart from the option pad on the package substrate, and is connected to the first power/ground pad by a bonding wire.
Claim 13 similarly recites the limitation “a wire” in line 10 and then introduces another “a wire” in line 12 and it is unclear if the wires are different or the same wire. For examination purposes, Claim 13 has been interpreted as follows based on FIG. 1 and paragraph [0042] of the instant specification:
Claim 13: A semiconductor package comprising: a package substrate; a wiring structure in the package substrate that includes all wiring components that connect between a top of the package substrate and a bottom of the package substrate; a plurality of external connecting terminals below the package substrate; a first semiconductor flip-chip bonded on and is above the package substrate; a second semiconductor chip above the package substrate and horizontally spaced apart from the first semiconductor chip, and wire-bonded on the package substrate; a first pad on an upper face of the second semiconductor chip; a second pad on the package substrate, and connected to the first pad by a first wire; a first connecting pad spaced apart from the second pad on the package substrate, and connected to the first pad by a second wire; an first bump below the first semiconductor chip on the package substrate, and electrically connected to and contacting the second pad; and a second bump spaced apart from the first bump below the first semiconductor chip, and electrically connected to a first external connecting terminal of the plurality of external connecting terminals directly through the wiring structure, wherein the first bump is not electrically connected to any external connecting terminal of the plurality of external connecting terminals directly through the wiring structure, and wherein the first connecting pad is electrically connected to a second external connecting terminal.
Claim 15 similarly recites yet another “a wire” in line 3 and the same lack of clarity remains as discussed with regards to claims 2 and 13. For examination purposes, Claim 15 has been interpreted as follows based on FIG. 6 and paragraph [0074]:
Claim 15: The semiconductor package of claim 13, further comprising: a third semiconductor chip stacked on the second semiconductor chip, and connected to the second semiconductor chip by a third wire.
Claim 17 recites “the wire is a bonding wire” in line 2 and it is unclear which of the previously introduced “a wire”s is a bonding wire, as well as “the same size” in line 3 where there is no previous introduction of “a same size” and lacks antecedent basis. For examination purposes, Claim 17 has been interpreted as follows based on FIGs. 1, 2, and paragraphs [0040, 0042]:
Claim 17: The semiconductor package of claim 13, wherein the second bump is a connecting bump, and first bump is an option bump, the first and second wires [[is a]] are bonding wires, and the second bump and the first bump have [[the]] a same size.
Claim 19, similarly to claims 2, 13, and 15, also again reintroduces “a wire” and it is unclear if this third “a wire” is a new wire, a same wire as one of the two in Claim 13, or some other possibility. For examination purposes, Claim 19 has been interpreted as follows based on FIG. 1 of the instant specification:
Claim 19: The semiconductor package of claim 13, wherein the first pad is a power/ground pad, the second pad is an option pad, the first bump is an option bump, and the second bump is a connecting bump, and further comprising: a signal pad placed on the upper face of the second semiconductor chip, and spaced apart from the power/ground pad; and a second connecting pad spaced apart from the option pad and the first connecting pad on the package substrate, and connected to the signal pad by a third wire, wherein the second connecting pad is not electrically connected to the option bump.
Claim 20 recites “an upper face of the second semiconductor chip stack” in both lines 8 and lines 9, where it is unclear if a signal pad is on a different upper face of the second semiconductor chip stack than an upper face which contains the first power/ground pad, particularly when the second semiconductor chip stack includes “a plurality of stacked memory chips”. For examination purposes, Claim 20 has been interpreted as follows based on FIG. 1 and paragraph [0046] of the instant application:
Claim 20: A semiconductor package comprising: a package substrate including a wiring structure; an external connecting terminal below the package substrate; a first semiconductor chip on and above the package substrate; a second semiconductor chip stack spaced apart from the first semiconductor chip on the package substrate and above the package substrate, and including a plurality of stacked memory chips; a first power/ground pad on an upper face of the second semiconductor chip stack; a signal pad on [[an]] the upper face of the second semiconductor chip stack, and spaced apart from the first power/ground pad; a second power/ground pad on the upper face of the second semiconductor chip stack, and spaced apart from the first power/ground pad and the signal pad; an option pad on the package substrate, and connected to the first power/ground pad by a wire; a first connecting pad spaced apart from the option pad on the package substrate, and connected to the first power/ground pad by the wire; a second connecting pad spaced from the option pad and the first connecting pad on the package substrate, and connected to the second power/ground pad; a third connecting pad spaced apart from the option pad, the first connecting pad, and the second connecting pad on the package substrate, and connected to the signal pad; an option bump below the first semiconductor chip on the package substrate, and electrically connected to the option pad through the wiring structure; a connecting bump spaced apart from the option bump below the first semiconductor chip, and electrically connected to the external connecting terminal; and a molding film which covers the first semiconductor chip and the second semiconductor chip stack on the package substrate, wherein the first semiconductor chip includes a controller that controls the plurality of stacked memory chips, the option bump is not electrically connected to the external connecting terminal directly through the wiring structure, the option pad is not electrically connected to the external connecting terminal directly through the wiring structure, the first connecting pad, the second connecting pad, and the third connecting pad are electrically connected to the external connecting terminal, and the second connecting pad and the third connecting pad are not electrically connected to the option bump.
Claims 3 and 4 depend directly from Claim 2 and do not correct the indefinite issue and therefore, are rejected for the same reasons as Claim 2 due to their dependency therefrom.
Claims 14, and 18 depend directly from Claim 13 and do not correct the indefinite issue and therefore, are rejected for the same reasons as Claim 13 due to their dependency therefrom.
Claim 16 depends directly from Claim 15 and does not correct the indefinite issue and therefore, is rejected for the same reasons as Claim 13 due to its dependency therefrom.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 9-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee, US PGPub 2024/0339435 A1 (hereinafter referred to as “Lee”).
Regarding Claim 1, Lee discloses A semiconductor package comprising (FIG. 1, semiconductor package 1):
a package substrate including a wiring structure (FIG. 1, package substrate 10, first and second substrate interconnections a1, a2, a3, a4, b1, b2, b3, b4 which together form the wiring structure; [0030-0032]);
a plurality of external connecting terminals below the package substrate (FIG. 1, connecting lands 600; [0023]);
a first semiconductor chip flip-chip bonded on and is above the package substrate (FIG. 1, control chip 30; [0027]);
a second semiconductor chip above the package substrate and horizontally spaced apart from the first semiconductor chip, and wire-bonded on the package substrate (FIG. 1, memory chip 21; [0024]);
a first power/ground pad on an upper face of the second semiconductor chip (FIG. 1, chip enable pad 212; [0025]);
an option pad on the package substrate and connected to the first power/ground pad by a wire (FIG. 1, memory chip connecting finger 121; [0026]);
an option bump below the first semiconductor chip and connected to the option pad through the wiring structure (FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131; [0030]);
and a connecting bump below the first semiconductor chip and connected to a first external connecting terminal of the plurality of external connecting terminals (FIG. 1, third chip enable signal control pad 331, solder bump 500, third control chip connecting pad 151 connected through third substrate interconnection c1 to a connecting land 600; [0033]),
wherein the option bump is not electrically connected to any external connecting terminal of the plurality of external connecting terminals through only the wiring structure (FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131 are not connected to any connecting land 600 through only the first or second substrate interconnections).
Regarding Claim 5, Lee discloses the semiconductor package of claim 1 as discussed above.
Lee further discloses wherein the second semiconductor chip is a memory chip (Lee FIG. 1, memory chip 21; [0017]),
and the first semiconductor chip is a controller for controlling the memory chip (Lee FIG. 1, control chip 30; [0017]).
Regarding Claim 9, Lee discloses the semiconductor package of claim 1 as discussed above.
Lee further discloses wherein the first power/ground pad is configured to receive a power signal or a ground signal of the second semiconductor chip (FIG. 1, chip enable pad 212, receives a power (i.e., option or selecting) signal for the second semiconductor chip operation/selection).
Regarding Claim 10, Lee discloses the semiconductor package of claim 1 as discussed above.
Lee further discloses further comprising: a signal pad on the upper face of the second semiconductor chip, and spaced apart from the first power/ground pad (FIG. 2, input/output pad(s) 214; [0036-0037]).
Regarding Claim 11, Lee discloses the semiconductor package of claim 10 as discussed above.
Lee further discloses wherein the signal pad is not electrically connected to the option pad (FIGs. 1, 2, input/output pad(s) 214 have no disclosed (explicitly nor implicitly) electrical connection with memory chip connecting finger 121; the I/O pads 214 of the memory chip 21 as disclosed need only electrical connection between the memory chip and an external terminal/connecting land to receive input and communicate resulting output signals, with no need for electrical connection to the memory chip connecting finger 121 which connects to the control chip 30 for optionally controlling/selecting the appropriate memory chip 21, 22, 23, 24 [0036-0037]).
Regarding Claim 12, Lee discloses the semiconductor package of claim 10 as discussed above.
Lee further discloses wherein the signal pad is configured to receive an input/output signal of the second semiconductor chip (FIG. 2, input/output pads 214 are configured for “data input/output,” i.e., signal input/output; [0036]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, as applied to Claim 1 above, in view of Park et al., US PGPub 2023/0005884 A1 (hereinafter referred to as “Park”).
Regarding Claim 2, Lee discloses the semiconductor package of claim 1 as discussed above.
Lee further discloses further comprising: a first connecting pad which is spaced apart from the option pad on the package substrate (FIG. 1, second memory chip connecting finger 122, connected to chip enable pad 222 through bonding wire 400; [0026]),
Lee does not explicitly disclose and is connected to the first power/ground pad by a wire.
However, Park, which is directed to a similar semiconductor package with stacked memory chips and connections between memory chips and package substrate, discloses where a pad spaced apart from another on the substrate would be connected to a same pad on a memory chip surface by a wire like so: (Park FIG. 8B, bonding pads BP2, BP4, first power/ground pads 113, wherein the bonding pad BP4 is connected to the first power/ground pad 113 through second upper wire UW2; [0041, 0066]). Park teaches that such a wiring configuration results in a shortened length of UW2 (Park [0061]) which one of ordinary skill would appreciate is beneficial for both cost and manufacturing efficiency reasons (shorter bond length would require less material and less time to create the structure).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Lee with the simultaneous multiple pad connection to a single pad, e.g., wherein the first connecting pad is connected to the first power/ground pad by a wire (Park FIG. 8B, bonding pads BP2, BP4, first power/ground pads 113, second upper wire UW2; [0041, 0061, 0066]) for the benefit of a reduced bonding wire length and so increased manufacturing efficiency and reduced cost.
Regarding Claim 3, Lee in view of Park (Lee/Park) discloses the semiconductor package of claim 2 as discussed above.
Lee/Park further disclose wherein the first connecting pad is electrically connected to a second external connecting terminal of the plurality of external connecting terminals through the wiring structure (see annotated Lee FIG. 1 below, with red arrow showing electrical connection path through the wiring structure, second memory chip connecting finger 122 is electrically connected to a second connecting land 600 through second substrate interconnection b2 through the following path in the wiring structure: second memory chip connecting finger 122 through first substrate interconnection a2 to second control chip connecting pad 132 to solder bump 500 to second control pad 312 to control chip 30 to sixth control pad 322 to solder bump 500 to second control chip connecting pad 142 to second substrate interconnection b2 to connecting land 600),
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and the first connecting pad is not electrically connected to the option bump and the connecting bump through only the wiring structure (see second annotated Lee FIG. 1 above, the second memory chip connecting finger 122 is electrically connected to 311/500/131 through control chip 30, not only the first or second substrate interconnections and associated pads (i.e., first control chip connecting pads 131, 132, 133, 134 and second control chip connecting pads 141, 142, 143, 144; second memory chip connecting finger 122 has no direct electrical connection through only the wiring structure in package substrate 10, only being electrically connecting through control chip 30).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, as applied to Claim 1 above, in view of Lee et al. (US PGPub 2012/0018885 A1 (hereinafter referred to as “Lee2012”).
Regarding Claim 6, Lee discloses the semiconductor package of claim 1, as discussed above.
Lee is silent on further comprising: a molding film which covers the first semiconductor chip and the second semiconductor chip on the package substrate.
However, Lee2012, which is directed to a similar semiconductor package with a control chip and memory chips teaches that a molding film is advantageous in semiconductor packaging as it not only protects the assorted chips but also any exposed bonding wires (such as bonding wires 400 in Lee) from unwanted movement and external humidity (Lee2012 FIG. 11 and paragraph [0115]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Lee with the molding film teachings of Lee2012, so that the package further comprising: a molding film which covers the first semiconductor chip and the second semiconductor chip on the package substrate (FIG. 11, molding 410 covering logic chip 100 and first memory chip 200 and second memory chip 300; [0115]) for the benefit of damage prevention and protection from external humidity.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, as applied to Claim 1 above, in view of Jeong et al., US PGPub 2021/0249832 A1 (hereinafter referred to as “Jeong”).
Regarding Claim 7, Lee discloses the semiconductor package of claim 1 as discussed above.
Lee is silent on further comprising: an adhesive layer placed between the second semiconductor chip and the package substrate.
However, Jeong, which is directed to a similar semiconductor package of a logic control chip and at least a memory chip (and up to multiple memory chips in a stacked configuration as in Lee), teaches using adhesive members between second memory chip 400a and the package substrate 100 allows for sequential stacking of multiple memory chips into a stack structure (Jeong FIG. 7 and paragraph [0070]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Lee/ with the adhesive attachment teachings of Jeong, so that the package further comprising: an adhesive layer placed between the second semiconductor chip and the package substrate (FIG. 7, adhesive member 420a; [0070]) to allow for sequential stacking of memory chips as well as the general benefit of securing the second memory chip 400a to the package substrate 100 due to the base nature of an adhesive material.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, as applied to Claim 1 above, in view of Liu et al., US PGPub 2009/0014860 A1 (hereinafter referred to as “Liu”).
Regarding Claim 8, Lee discloses the semiconductor package of claim 1 as discussed above.
Lee is silent on wherein a width of the first semiconductor chip in a first direction is smaller than a width of the second semiconductor chip in the first direction.
However, Liu, which is directed to multi-chip stack packages, teaches that, conventionally in the art, controller chips are known to be “typically much smaller than that of the memory chips” (Liu [0007]) and that, when constructing a multi-chip package similarly to Lee and the instant application, one way to solve the problem of increasing surface area due to a demand to include a greater number of chips in the package, e.g. a multi-chip package or module, (Liu [0002]) is with a controller chip 22 which has a smaller planar size than a memory chip 21 which allows for a reduced height/width of the package, reduced possibilities of short circuits, and reduced difficulty of wire bonding methods (Liu FIG. 2A, paragraphs [0016-0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Lee with the teachings of Liu wherein a width of the first semiconductor chip in a first direction is smaller than a width of the second semiconductor chip in the first direction (FIG. 2A, controller chip 22 smaller in width in a first direction (e.g., horizontally) than memory chip 21; [0002, 0007, 0016-0017]) for the benefits of reducing the surface area of the package, the possibilities of short circuits, and increasing the ease of wire bonding.
Claims 13, 14, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park.
Regarding Claim 13, Lee discloses a semiconductor package comprising (FIG. 1, semiconductor package 1):
a package substrate (FIG. 1, package substrate 10);
a wiring structure in the package substrate that includes all wiring components that connect between a top of the package substrate and a bottom of the package substrate (FIG. 1, first, second, and third substrate interconnections a1, a2, a3, a4, b1, b2, b3, b4, c1 which together form the wiring structure; [0030-0032]);
a plurality of external connecting terminals below the package substrate (FIG. 1, connecting lands 600; [0023]);
a first semiconductor chip flip-chip bonded on and is above the package substrate (FIG. 1, control chip 30; [0027]);
a second semiconductor chip above the package substrate and horizontally spaced apart from the first semiconductor chip, and wire-bonded on the package substrate (FIG. 1, memory chips 21, 22, 23, 24 connected to package substrate 10 through bonding wires 400; [0024]);
a first pad on an upper face of the second semiconductor chip (FIG. 1, chip enable pad 212; [0025]);
a second pad on the package substrate, and connected to the first pad by a wire (FIG. 1, memory chip connecting finger 121 connected to chip enable pad 212 via bonding wires 400; [0026]);
a first connecting pad spaced apart from the second pad on the package substrate (FIG. 1, second memory chip connecting finger 122, connected to chip enable pad 222 through bonding wire 400; [0026]),
an first bump below the first semiconductor chip on the package substrate, and electrically connected to and contacting the second pad (FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131; [0030]);
and a second bump spaced apart from the first bump below the first semiconductor chip, and electrically connected to a first external connecting terminal of the plurality of external connecting terminals directly through the wiring structure (FIG. 1, third chip enable signal control pad 331, solder bump 500, third control chip connecting pad 151 connected through third substrate interconnection c1 to connecting land 600; [0033]),
wherein the first bump is not electrically connected to any external connecting terminal of the plurality of external connecting terminals directly through the wiring structure (FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131 are not electrically connected to any connecting land 600 directly through the first, second, or third substrate interconnections, as they much go through control chip 30),
and wherein the first connecting pad is electrically connected to a second external connecting terminal (FIG. 1, second memory chip connecting finger 122 is electrically connected to a second connecting land 600 through second substrate interconnection b2 through the following path in the wiring structure: second memory chip connecting finger 122 through first substrate interconnection a2 to second control chip connecting pad 132 to solder bump 500 to second control pad 312 to control chip 30 to sixth control pad 322 to solder bump 500 to second control chip connecting pad 142 to second substrate interconnection b2 to connecting land 600).
Lee does not explicitly disclose wherein the first connecting pad is and connected to the first pad by a wire.
However, Park, which is directed to a similar semiconductor package with stacked memory chips and connections between memory chips and package substrate, discloses where a pad spaced apart from another on the substrate would be connected to a same pad on a memory chip surface by a wire (Park FIG. 8B, bonding pads BP2, BP4, first power/ground pads 113, wherein the bonding pad BP4 is connected to the first power/ground pad 113 through second upper wire UW2; [0041, 0066]).
Park teaches that such a wiring configuration results in a shortened length of upper wire UW2 (Park [0061]), which one of ordinary skill would appreciate is beneficial for both cost and manufacturing efficiency reasons (shorter bond length would require less material and less time to create the structure).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Lee with the simultaneous multiple pad connection to a single pad, e.g., wherein the first connecting pad is connected to the first pad by a wire (Park FIG. 8B, bonding pads BP2, BP4, first power/ground pads 113, second upper wire UW2; [0041, 0061, 0066]) for the benefit of a reduced bonding wire length and so increased manufacturing efficiency and reduced cost.
Regarding claim 14, Lee/Park discloses the semiconductor package of claim 13 as discussed above.
Lee/Park further disclose wherein the first bump is electrically connected to the first external connecting terminal of the plurality of external connecting terminals, but is not electrically connected to the first external connecting terminal directly through the wiring structure (FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131 are not electrically connected to any connecting land 600 directly through the first, second, or third substrate interconnections, but is still electrically connected to a first connecting land 600 through the following path: from “first bump,” i.e., 311/500/131, to control chip 30, to third chip enable signal control pad 331 to solder bump 500, to third substrate interconnection c1, to connecting land 600).
Regarding Claim 17, Lee/Park discloses the semiconductor package of claim 13 as discussed above.
Lee/Park further disclose wherein the second bump is a connecting bump (Lee FIG. 1, third chip enable signal control pad 331, solder bump 500, third control chip connecting pad 151 connected through third substrate interconnection c1 to connecting land 600; [0033]; 331/500/151 connects the chip to a path control signal, therefore it is a “connecting” bump),
and first bump is an option bump (Lee FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131; [0030], the first bump is a chip enable signal control pad, i.e., it controls if a signal is sent to the electrically connected memory chip, therefore it is an “option” or “optional” bump),
the wire is a bonding wire (FIG. 1, bonding wires 400),
and the second bump and the first bump have the same size (Lee FIG. 1, all solder bumps 500, control pads 311, 312 are of a same size (e.g., 311/500/131 is of a same size as 331/500/151).
Regarding Claim 18, Lee/Park discloses the semiconductor package of claim 13 as discussed above.
Lee/Park further disclose wherein the second semiconductor chip is a memory chip (Lee FIG. 1, memory chip 21; [0017]),
and the first semiconductor chip is a controller for controlling the memory chip (Lee FIG. 1, control chip 30; [0017]).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Park and further in view of Sano, US PGPub 2022/0068879.
Regarding Claim 15, Lee/Park discloses the semiconductor package of claim 13 as discussed above.
Lee/Park further comprising: a third semiconductor chip stacked on the second semiconductor chip (FIG. 1, memory chip 22 on memory chip 21; [0025]),
Neither Lee nor Park explicitly disclose the third semiconductor chip is and connected to the second semiconductor chip by a wire.
However, Sano, which is directed to a similar semiconductor package containing a stacked configuration of memory chips, teaches just that: supplying a connection between memory chips (such as with a bonding wire) is beneficial for “[enhancing] the wirings of the power supply circuits common to a plurality of semiconductor memory chips” and thereby “[enhancing] the power supply for operating the semiconductor memory chips 2 efficiently and effectively” (Sano FIGs. 1, 2, first pad 4A of semiconductor memory chip 2A connected to second pad 5A of semiconductor memory chip 2B; [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Lee/Park with the teachings of Sano to connect the stacked memory chips together via a wire, i.e., so have the third semiconductor chip is and connected to the second semiconductor chip by a wire (Sano FIGs. 1, 2, first pad 4A of semiconductor memory chip 2A connected to second pad 5A of semiconductor memory chip 2B; [0029]) for the benefits of increasing power supply performance and efficiency.
Regarding Claim 16, Lee/Park/Sano discloses the semiconductor package of claim 15 as discussed above.
Lee/Park/Sano further disclose wherein the second semiconductor chip and the third semiconductor chip include a memory of the same kind (Lee FIG. 1, memory chips 21, 22; [0017, 0024]).
Allowable Subject Matter
Claims 4 and 19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 121 (pre-AIA ) 2nd paragraph, set forth in this office action.
Claim 20 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this office action.
As allowable subject matter has been indicated, applicant’s reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is the Examiner’s statement of reasons for indicating allowable subject matter:
Regarding Claim 4, Lee discloses the semiconductor package of claim 2 as discussed above.
Lee further discloses further comprising: a second power/ground pad on the upper face of the second semiconductor chip, and spaced apart from the first power/ground pad (FIG. 2, power pads 211; [0036]);
Lee is silent, however, on and a second connecting pad on the package substrate and spaced apart from the option pad and the first connecting pad, and connected to the second power/ground pad, wherein the second power/ground pad is not electrically connected to the option pad.
More specifically, Lee does not disclose nor teach that the second power/ground pad on an upper face of the memory chip not [be] electrically connected to the option pad; at best Lee teaches a semiconductor package with a second connecting pad on the package substrate (e.g., third memory connecting finger 123) but which would then be electrically connected to the option pad (e.g., 311/500/131) through the control chip 30.
Regarding claim 19, Lee/Park disclose the semiconductor package of claim 13, as discussed above.
Lee/Park further disclose wherein the first pad is a power/ground pad (Lee FIG. 1, chip enable pad 212, receives a power (i.e., option or selecting) signal for the second semiconductor chip operation/selection),
the second pad is an option pad (Lee FIG. 1, memory chip connecting finger 121 connected to chip enable pad 212 via bonding wires 400; [0026]),
the first bump is an option bump (Lee FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131; [0030], the first bump is a chip enable signal control pad, i.e., it controls if a signal is sent to the electrically connected memory chip, therefore it is an “option” or “optional” bump),
and the second bump is a connecting bump (Lee FIG. 1, third chip enable signal control pad 331, solder bump 500, third control chip connecting pad 151 connected through third substrate interconnection c1 to connecting land 600; [0033]; 331/500/151 connected the chip to a path control signal, therefore it is a “connecting” bump),
and further comprising: a signal pad placed on the upper face of the second semiconductor chip, and spaced apart from the power/ground pad (FIG. 2, input/output pad(s) 214; [0036-0037]);
Similar to Claim 4 as discussed above, neither Lee nor Park explicitly disclose where the semiconductor package further comprises and a second connecting pad spaced apart from the option pad and the first connecting pad on the package substrate, and connected to the signal pad by a wire, wherein the second connecting pad is not electrically connected to the option bump.
While some argument could be made that memory chip connecting finger 123 could be “a second connecting pad spaced apart from the option pad and the first connecting pad on the package substrate,” Lee is silent on any electrical connections or otherwise between the input/output pads 214 and the pads located on the substrate and further, at best Lee teaches a semiconductor package with a second connecting pad on the package substrate (e.g., third memory connecting finger 123) but which would then be electrically connected to the option pad (e.g., 311/500/131) through the control chip 30.
Regarding Claim 20, Lee discloses A semiconductor package comprising (Lee FIG. 1, semiconductor package 1):
a package substrate including a wiring structure (Lee FIG. 1, package substrate 10);
an external connecting terminal below the package substrate (Lee FIG. 1, connecting lands 600; [0023]);
a first semiconductor chip on and above the package substrate (Lee FIG. 1, control chip 30; [0027]);
a second semiconductor chip stack spaced apart from the first semiconductor chip on the package substrate and above the package substrate, and including a plurality of stacked memory chips (Lee FIG. 1, memory chips 21, 22, 23, 24 connected to package substrate 10 through bonding wires 400; [0024]);
a first power/ground pad on an upper face of the second semiconductor chip stack (Lee FIG. 1, chip enable pad 212; [0025]);
a signal pad on an upper face of the second semiconductor chip stack, and spaced apart from the first power/ground pad (Lee FIG. 2, input/output pad(s) 214; [0036-0037]);
a second power/ground pad on the upper face of the second semiconductor chip stack, and spaced apart from the first power/ground pad and the signal pad (Lee FIG. 2, power pads 211; [0036]);
an option pad on the package substrate, and connected to the first power/ground pad by a wire (Lee FIG. 1, memory chip connecting finger 121 connected to chip enable pad 212 via bonding wires 400; [0026]);
a first connecting pad spaced apart from the option pad on the package substrate, and connected to the first power/ground pad by the wire (Lee FIG. 1, second memory chip connecting finger 122, connected to chip enable pad 222 through bonding wire 400, [0026] would be combined/modified with Park FIG. 8B, bonding pads BP2, BP4, first power/ground pads 113, wherein the bonding pad BP4 is connected to the first power/ground pad 113 through second upper wire UW2, [0041, 0066] for the same reasons and motivation as discussed above with respect to claim 13);
an option bump below the first semiconductor chip on the package substrate, and electrically connected to the option pad through the wiring structure (FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131; [0030]);
a connecting bump spaced apart from the option bump below the first semiconductor chip, and electrically connected to the external connecting terminal (FIG. 1, third chip enable signal control pad 331, solder bump 500, third control chip connecting pad 151 connected through third substrate interconnection c1 to connecting land 600; [0033]);
and a molding film which covers the first semiconductor chip and the second semiconductor chip stack on the package substrate (as discussed with Claim 6 above, Lee2012 FIG. 11, molding 410 covering logic chip 100 and first memory chip 200 and second memory chip 300; molding both protects the chips from damage and further protects any exposed bonding wires from unwanted movement and humidity [0115] would apply and be combined with Lee and Park for the same reasons as discussed above with respect to Claim 6),
wherein the first semiconductor chip includes a controller that controls the plurality of stacked memory chips (Lee FIG. 1, control chip 30; [0017]),
the option bump is not electrically connected to the external connecting terminal directly through the wiring structure (FIG. 1, first control pad 311, solder bump 500, first control chip connecting pad 131 are not connected to any connecting land 600 directly through the first, second, or third substrate interconnections),
the option pad is not electrically connected to the external connecting terminal directly through the wiring structure (FIG. 1, memory chip connecting finger 121 does not directly electrically connect to the connecting lands 600, it electrically connects through the control chip 30 instead following the path: 121, a1, 131, 500, 311, 30, 321, 500, 141, b1, 600),
However, for much the same reasoning as already discussed above with respect to claims 4 and 19, none of the prior art (Lee, Lee2012, Jeong, Park, Sano, Liu) taken alone or in combination teach nor disclose:
a second connecting pad spaced from the option pad and the first connecting pad on the package substrate, and connected to the second power/ground pad;
a third connecting pad spaced apart from the option pad, the first connecting pad, and the second connecting pad on the package substrate, and connected to the signal pad;
the first connecting pad, the second connecting pad, and the third connecting pad are electrically connected to the external connecting terminal,
and the second connecting pad and the third connecting pad are not electrically connected to the option bump.
More specifically, as discussed above with respect to Claims 4 and 19, none of the prior art teaches that the second and third connecting pads are not electrically connected to the option bump.
In sum, with respect to Claims 4, 19, and 20, none of the prior art, when taken alone or in combination, teaches or suggests all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the Applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee, US PGPub 2024/0321710, which is directed to a semiconductor package with a controller chip and memory chip stack and similar wiring structure to Lee and the instant application.
GOTO, US PGPub 2020/0303345 A1, which is directed to a semiconductor package with a logic chip and memory chip stack and various bonding schemes therein.
Itoh et al., US PGPub 2008/0122064 A1, which is directed to a semiconductor multi-chip package with a memory chip stack, a controller chip, multiple pads along the package substrate and memory chip surfaces, and explicit description of each pad’s use and possible layouts in detailed plan views.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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