DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment dated 07/29/2026 are acknowledged. Claim 10, 16, 19-20 are amended. No new claims are added. No claims are cancelled. Claims 1-20 remain pending in application.
Response to Arguments
Applicant’s argument dated 07/29/2026 have been acknowledged but arguments regarding claims 19-20 are not persuasive since examiner argues, NOH & Lue still reads on the amended claims ( see claims 19-20 rejections below). However, claims 10-18 are allowed in current office action. Claims 1-9 were allowed in previous office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over NOH et al.(US 2020/0203427 A1) in view of Lue et al (US 8630114 B2)
Regarding claim 19, NOH teaches,
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A semiconductor memory device (Fig. 2A, see annotation above) comprising:
………a first semiconductor pattern (including patterns of CT (70) in direction Y between BL and SL as marked above),……..
……a first direction (Z);
a first gate structure (including 50 & 60 as marked, Figs. 2A, 3A , para[0083]) extending in the first direction (Z), penetrating the first semiconductor pattern (as seen above);
a second gate structure (as marked) extending in the first direction(Z) penetrating the first semiconductor pattern (as seen above)
a first conductive connecting line (BL as marked, Figs. 2A & 3A, para [0083]) connected to the first semiconductor pattern and extending in a second direction (extended in width direction in direction X , Fig. 2A above) different from the first direction (Z); and
a second conductive connecting line (SL as marked, Figs. 2A & 3A, para [0083]) connected to the first semiconductor pattern,
wherein the first gate structure is between the first conductive connecting line and the second conductive connecting line (as seen above),
the first gate structure includes a first gate electrode (50, para [0083]) and a first gate insulating film (60, Fig. 3A, para [0083]),
the first semiconductor pattern extends from the first conductive connecting line to the second conductive connecting line (as seen)
the first gate structure and the second gate structure are spaced apart in a third direction different (direction Y) from the first direction and the second direction,
the second gate structure is between the first conductive connecting line and the second conductive connecting line (as seen above),
the first gate insulating film includes a first charge holding film (considering 62 & 63 as a first charge holding film comprising charge trapping dielectric layer 62, para [0084], Fig. 3A) contacting with the first semiconductor pattern (63 contacting 70, FIG. 3A).
BUT NOH does not explicitly teach,
a peripheral circuit region including peripheral wirings on a substrate
the first semiconductor pattern spaced apart from the peripheral circuit region in the first direction
the first gate structure connected to the peripheral wirings;
But NOH addionally teaches,
gate electrode structure (50 & 60) formed orthogonal to substrate 10 (see FIG. 35) to form a non-volatile memory device (para [0138], [0074]).
Meanwhile, Lue teaches,
Word line WLn formed orthogonal to substrate 10 (Fig. 1) and word line 862 are coupled to row decoder 861 (Fig. 4, Col. 6, ll. 14-15)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify NOH such that gate electrode structures (50, Fig. 35) (as a word line) formed orthogonally on a substrate 10 such that it is coupled to a row decoder formed in the substrate 10 such that a peripheral circuit region (obvious row decoder circuit region) including peripheral wirings (obvious wiring connecting row decoder circuit region to gate electrode 50) on the substrate such that the first gate structure (50) is connected to peripheral wirings and such that the first semiconductor pattern spaced apart from the peripheral circuit region in the first direction , according to teaching of Lue, in order select word lines via row decoder for the purpose of forming a non-volatile memory device, as taught by Lue.
Regarding claim 20, NOH & Lue teaches the semiconductor memory device of claim 19 and further teaches, the second gate structure includes a second gate electrode (50 of second gate structure) and a second gate insulating film (60 of second gate structure) , the second gate insulating film includes a second charge holding film (including 62 & 63 of second gate structure) contacting the first semiconductor pattern (63 of second gate structure contacts corresponding first semiconductor pattern 70) , and the first semiconductor pattern extending from the first conductive connecting line (BL) to the second conductive connecting line (SL) (as seen).
Allowable Subject Matter
Claims 1-18 are allowed.
Claims 1-9 are allowed in previous office action.
With respect to claim 10, the prior art made of record does not teach or suggest either alone or in combination “and an etching stop film between the peripheral wiring and the second semiconductor pattern ………and the second conductive connecting line penetrates the etching stop film and is connected to the peripheral wiring” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
Applicants’ argument dated 07/29/2026 are persuasive. The other cited arts, either alone or in combination, fails to teach above limitation.
Claims 11-18 are allowed being dependent on claim 10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. (FP 7.40)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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