Prosecution Insights
Last updated: July 17, 2026
Application No. 18/757,900

MULTILAYER CERAMIC CAPACITOR

Final Rejection §103
Filed
Jun 28, 2024
Priority
Jun 02, 2022 — JP 2022-090245 +1 more
Examiner
RAMASWAMY, ARUN
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
6m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
678 granted / 802 resolved
+16.5% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
28 currently pending
Career history
836
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
85.8%
+45.8% vs TC avg
§102
11.8%
-28.2% vs TC avg
§112
1.2%
-38.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 802 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see page 6 of Remarks, filed April 6, 2026, with respect to the U.S.C. 112 rejection of claim 16 have been fully considered and are persuasive. The rejection of the aforementioned claim has been withdrawn. Applicant’s arguments with respect to the prior art rejection of claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishisaka et al. (US Publication 2018/0096791) in view of Lee et al. (US Publication 2022/0172895) and in further view of Iguchi et al. (US Publication 2023/0107429). In re claim 1, Nishisaka discloses a multilayer ceramic capacitor, comprising: a multilayer body (11 – Figure 2, ¶24) including at least one dielectric layer (12b – Figure 2, ¶24) and at least one internal electrode (13a, 13b – Figure 2, ¶24) alternately stacked (Figure 2); and a pair of external electrodes (14a, 14b – Figure 2, ¶23) on surfaces of the multilayer body (11 – Figure 2) and electrically conducting with the at least one of of internal electrodes extending to the surfaces of the multilayer body, respectively (Figure 2); wherein the multilayer body includes: a first main surface (16a – Figure 2, ¶26) and a second main surface (16b – Figure 2, ¶26) on opposite sides in a thickness direction that is a lamination direction (‘T’ direction – Figure 1) of the dielectric layers (12b – Figure 2) and the internal electrodes (13a, 13b - Figure 2); a first end surface (15a – Figure 2, ¶26) and a second end surface (15b – Figure 2, ¶26) on opposite sides in a length direction (‘L’ direction – Figure 1) in which the pair external electrodes (14a, 14b – Figure 2) face each other, the pair of external electrodes being provided on the first end surface and second end surface (Figure 2); and a first lateral surface and a second lateral surface (17a, 17b – Figure 1, ¶26) on opposite sides in a width direction (‘W’ direction – Figure 1) orthogonal or substantially orthogonal to both of the thickness direction and the length direction (Figure 1, Figure 2); at least one of the pair of external electrodes include: a metal layer (141a, 141b – Figure 2, ¶44-45) at least one of the first end surface and the second end surface (Figure 2), and covering the at least one internal electrode (13a, 13b – Figure 2) extending to the first end surface and the second end surface, respectively (Figure 2); a glass film (142a, 142b – Figure 2, ¶44) on the at least one of the first end surface and the second end surface, the glass film being adjacent to the metal layer (141a, 141b – Figure 2) and extending around the metal layer (Figure 4); a fired layer (143a, 143b – Figure 2, ¶44) including glass and metal (¶54), and covering the metal layer (141a, 141b – Figure 2); and a plating film (144a, 144b – Figure 2, ¶44) covering the fired layer (Figure 2). Nishisaka does not disclose the glass film extends to a portion of at least one of the first main surface, the second main surface, the first lateral surface, or the second lateral surface. Lee discloses the glass film (152 – Figure 2, ¶34) extends to a portion of at least one of the first main surface (S2 – Figure 2, ¶38), the second main surface, the first lateral surface, or the second lateral surface (Figure 2). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to included the extended glass portions as described by Lee to improve the moisture reliability of the device (¶39: Lee). Nishisaka does not disclose the fired layer includes voids, and at least a portion of the voids includes plating material. Iguchi discloses the fired layer (61 – Figure 2, ¶49) includes voids (62 – Figure 2, ¶48), and at least a portion of the voids includes plating material (64 – Figure 3, ¶49, ¶68, ¶100). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the electrode layer structure Iguchi to provide for a device having increased mounting strength and low ESR characteristics (¶5: Iguchi). In re claim 2, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka does not disclose wherein at least one of the voids is closer to the metal layer than halfway through a thickness of the fired layer from a surface of the fired layer. Iguchi discloses wherein at least one of the voids is closer to the laminate body (62 – Figure 3) than halfway through a thickness of the fired layer (6a – Figure 3, ¶48) from a surface of the fired layer (Figure 3). The combination of Nishisaka and Iguchi discloses wherein at least one of the voids is closer to the metal layer than halfway through a thickness of the fired layer from a surface of the fired layer. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the electrode layer structure Iguchi to provide for a device having increased mounting strength and low ESR characteristics (¶5: Iguchi). In re claim 3, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein at least a portion of the metal layer (141a, 141b – Figure 2) is exposed at the fired layer (143a, 143b – Figure 2). Note that the metal layer is exposed to contact the fried layer directly. In re claim 4, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka does not disclose wherein an area ratio of the plating material at a position three-quarters of a thickness from a surface of the fired layer on either the first end surface or the second end surface is between about 20% and about 90% inclusive. Iguchi discloses that adjusting the amount of the plating material in a region that is three-quarters of a thickness from a surface of the fired layer (¶63-64, Figure 3) is correlated to improving the ESR characteristics of the device (¶10-11). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the total Ni content in the fried layers to achieve a device having desired ESR characteristics, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). In re claim 5, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein a thickness of the metal layer (141a, 141b – Figure 2) is between about 0.1 µm and about 15.0 µm inclusive (¶52). In re claim 6, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein a thickness of the fired layer (143a, 143b – Figure 2) is between about 1.0 µm and about 100.0 µm inclusive (¶57). In re claim 7, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein the glass film (142a, 142b – Figure 2) is in contact with an end portion of the metal layer (141a, 141b – Figure 2) and extends around the metal layer (Figure 4). In re claim 8, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein the multilayer body (11 – Figure 1) has a dimension in the length direction (‘L’ direction – Figure 1) between about 200 µm and about 2000 µm inclusive, a dimension in the thickness direction (‘T’ direction – Figure 1) between about 100 µm and about 1000 µm inclusive, and a dimension in the width direction (‘W’ direction – Figure 1) between about 100 µm and about 1000 µm inclusive (¶28). In re claim 9, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein a number of the plurality of dielectric layers (12b – Figure 2) is between 10 and 1000 inclusive (¶31). In re claim 10, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein a thickness of each of the plurality of dielectric layers (12b – Figure 2) is between about 0.3 µm and about 5.0 µm inclusive (¶94). In re claim 11, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka does not disclose wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Lee discloses wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 (¶35). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the dielectric material as described by Lee to achieve a device having desired capacitance. In re claim 12, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein a number of the plurality of internal electrodes (13a, 13b – Figure 2) is between 10 and 1000 inclusive (¶37). In re claim 13, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein a thickness of each of the plurality of internal electrodes (13a, 13b – Figure 2) is between about 0.3 µm and about 5.0 µm inclusive (¶38). In re claim 14, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein each of the plurality of internal electrodes (13a, 13b – Figure 2) includes Ni, Cu, Ag, Pd, or Au, an alloy of Ni and Cu, or an alloy of Ag and Pd (¶35). In re claim 15, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein the metal layer (141a, 141b – Figure 2) includes at least one of Cu, Ni, Ag, Pd, or Au (¶8). In re claim 16, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein the fired layer (143a, 143b – Figure 2) includes at least one of Cu, Ni, Ag, Pd, or Au (¶56). In re claim 17, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein the plating film (144a, 144b – Figure 2) includes as least one of Cu, Ni, Ag, Pd, or Au (¶66). In re claim 18, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 1, as explained above. Nishisaka further discloses wherein the plating film (144a, 144b – Figure 2) includes a bottom plating film and a top plating film on the bottom plating film (¶66). In re claim 19, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 18, as explained above. Nishisaka further discloses wherein the bottom plating film includes at least one of Cu, Ni, Ag, Pd, or Au, or an alloy of Ag and Pd (¶66). In re claim 20, Nishisaka in view of Lee and in further view of Iguchi discloses the multilayer ceramic capacitor according to claim 18, as explained above. Nishisaka further discloses wherein the top plating film includes Sn (¶66). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Onoue et al. (US Publication 2018/0286583) Figure 8 Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARUN RAMASWAMY/ Primary Examiner, Art Unit 2848
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Prosecution Timeline

Jun 28, 2024
Application Filed
Jan 09, 2026
Non-Final Rejection mailed — §103
Apr 02, 2026
Response Filed
Jun 16, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
97%
With Interview (+12.5%)
2y 6m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 802 resolved cases by this examiner. Grant probability derived from career allowance rate.

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