DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d
Information Disclosure Statement
The information disclosure statement filed on 06/28/2024 has been considered.
Drawings
The drawings filed on 06/28/2024 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 06/28/2024 are acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0381999) in view of Hossain (US 2020/0211969).
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Regarding claim 1, Chen (US 2022/0381999) discloses:
A semiconductor package comprising:
a redistribution layer (130, ¶0026);
a photonic integrated circuit (PIC) chip (192, ¶0028) on the redistribution layer (130);
a buffer chip (120, ¶0026) on the redistribution layer (130);
an electronic integrated circuit (EIC) chip (194, ¶0028) on the PIC chip (192) and the buffer chip (120); and
a stacked structure (180, ¶0028) on the buffer chip (120) wherein a portion of the EIC chip (194) overlaps the PIC chip (192) in a vertical direction, and another portion of the EIC chip (194) overlaps the buffer chip (120) in a vertical direction.
Chen does not disclose “a plurality of stacked structures on the buffer chip, each of the plurality of stacked structures including a plurality of stacked semiconductor chips, wherein the plurality of stacked structures are spaced apart from one another in a horizontal direction”.
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In a similar device, however, Hossain (US 2020/0211969) discloses a semiconductor package (100, ¶0017) comprising a buffer chip (130, ¶0018) and a plurality of stacked structures (150, ¶0020) on the buffer chip (130), each of the plurality of stacked structures including a plurality of stacked semiconductor chips (156, ¶0024), wherein the plurality of stacked structures are spaced apart from one another in a horizontal direction (figure 1a). Hossain discloses that a structure as taught provides an improved package yield (¶0020). Therefore, it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the device of Chen including providing a plurality of stacked structures on the buffer chip, each of the plurality of stacked structures including a plurality of stacked semiconductor chips, wherein the plurality of stacked structures are spaced apart from one another in a horizontal direction in order to improve package yield as taught by Hossain.
Regarding claim 3, Chen in view of Hossain does not disclose “wherein a thickness of the PIC chip is equal to a thickness of the buffer chip”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore, the claimed limitations are considered met.
Regarding claim 4, Chen further discloses:
wherein the PIC chip (192) comprises an active surface, an inactive surface opposite the active surface, and through vias (162) , and wherein the inactive surface of the PIC chip faces the redistribution layer (¶0041).
Regarding claim 5, Chen further discloses:
wherein the buffer chip (130) comprises an active surface, an inactive surface opposite the active surface, and through vias (122), and wherein the active surface of the buffer chip faces the redistribution layer (130).
Regarding claim 6, Chen in view of Hossain does not disclose “wherein a sum of an area of the PIC chip and an area of the buffer chip is less than an area of the redistribution layer”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore, the claimed limitations are considered met.
Regarding claim 7, Chen in view of Hossain does not disclose “wherein a thickness of each of the plurality of stacked structures is equal to a thickness of the EIC chip”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore, the claimed limitations are considered met.
Regarding claim 8, Chen further discloses:
wherein the EIC chip comprises an active surface and an inactive surface opposite the active surface, and wherein the active surface of the EIC chip faces the PIC chip (¶0042).
Regarding claim 9, the modification of Hossain further discloses:
wherein the plurality of semiconductor chips (156) of each of the plurality of stacked structures comprise memory chips (¶0056).
10. The semiconductor package of claim 1, further comprising a plurality of optical fibers (OTYV 145, ¶0026) configured to input/output optical signals to/from the PIC chip, wherein the plurality of optical fibers are positioned on the PIC chip (192).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art does not disclose “, wherein the PIC chip is spaced apart from the buffer chip in a horizontal direction, and wherein at least a portion of the EIC chip is positioned above a space between the PIC chip and the buffer chip” in combination with the remaining claimed features.
Claims 11-20 are allowed.
Regarding claim 11, the prior art does not disclose “
an electronic integrated circuit (EIC) chip above the PIC chip and the buffer chip and having one end portion positioned above the PIC chip and the other end portion positioned above the buffer chip in a first horizontal direction” in combination with the remaining claimed features.
Regarding claim 17, the prior art does not disclose “an electronic integrated circuit (EIC) chip on the PIC chip and the buffer chip and positioned to overlap the PIC chip and the buffer chip;” and “a molding layer on at least a portion of a top surface of the redistribution layer and on side surfaces of the PIC chip, the buffer chip, the EIC chip, and the plurality of stacked structures” in combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899
