Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation - 35 USC § 112
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) are:
means for triggering in claim 20.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-3, 13-15, 20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Flynn et al. (US Pub No. 2004/0153762).
In regard to claims 1, 13, 20, Flynn et al. disclose an apparatus, a method, comprising: triggering, via one or more circuit elements, saving of architecture state information of at least one processing element (PE) to at least one memory prior to the at least one PE transitioning from a first state to a second state (as shown in Fig. 3, which is reproduced below for ease of reference and convenience, Flynn discloses a state saving controller 16 is added to the AHB interface 4 and is responsive to a state saving trigger to cause the scan chains 12 to capture state representing data values from their associated nodes within the processor core 2. The state saving controller 16 then clocks the scan chains 12 to form the state saving data words and generates the appropriate address control signals on the system bus to cause a data transfer from the processor core 2 to the memory 14 to take place. The state saving trigger could be the pressing of a power key, the falling of a battery level below a predetermined level or the like. See ¶ 40-41);
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and triggering, via the one or more circuit elements, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state (in Flynn, when a state restore operation is required, the state saving controller 16 responds to a state restoring trigger to cause a burst read of the stored state data words from the memory 14 back into the scan chains 12 which are serially clocked as each saved state data word arrives. Once all the state has been stored back into the scan chains 12 these are used to apply those data values to the corresponding nodes within the processor core 12 to restore its state and normal processing resumed. See ¶ 42).
In regard to claims 2, 14, Flynn et al. disclose wherein: the at least one PE transitions from the first state to the second state as part of a power down sequence; and the at least one PE transitions from the second state to the first state as part of a power up sequence (in Flynn, state saving controller 16 may response to a state saving trigger in the form of a program instruction executed by the processor core 2, such as a store to a predetermined address dedicated to this function, or a coprocessor instruction for a coprocessor dedicated to this function, or the like. Alternatively, the state saving trigger could be the pressing of a power key, the falling of a battery level below a predetermined level or the like.. See ¶ 23, 41, 44, 47).
In regard to claims 3, 15, Flynn et al. disclose wherein the one or more circuit elements comprise, at least one sequencing element to trigger the saving and restoration; and at least one routing interface to transfer architecture state information between state registers of the at least one PE and the at least one memory (in Flynn, a state saving controller 16 is added to the AHB interface 4 and is responsive to a state saving trigger to cause the scan chains 12 to capture state representing data values from their associated nodes within the processor core 2. The state saving controller 16 then clocks the scan chains 12 to form the state saving data words and generates the appropriate address control signals on the system bus to cause a data transfer from the processor core 2 to the memory 14 to take place. The state saving controller 16 can utilize burst mode transfers in order to improve efficiency. See ¶ 40).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 4-6, 8-12, 16-18 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Flynn et al. in view of Stillwell, Jr. et al. (US Pub No. 2009/0172369).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Flynn reference; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claims 4, 16, Flynn et al. disclose the subjected matter as discussed above rejection except the teaching of wherein: the at least one PE comprises multiple PEs; and the at least one sequencing element comprises: a sequencing element per each of the multiple PEs, or a single sequence element that saves architecture state information for the multiple PEs. In the same field of endeavor, Stillwell, Jr. et al. disclose processing elements 205 and 210 include a core, a hardware thread, a logical processor, or other element capable of holding an architectural state. Core 101 and 102 include destination registers to hold destination addresses for associated architectural states to be stored/saved to, as well as restore registers to hold a restore address to load/restore an architectural state from. The event storage element (EVE) 208 is to hold a representation of save architectural state events. For example, EVE 208 includes a plurality of fields that correspond to save state events. In a specific illustrative embodiment, EVE 208 includes a bitmap of save architectural state events (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Stillwell Jr. discloses saving of an architectural state of core 205 to memory 230 is in response to a save architectural state event. In one embodiment, a save architectural state event includes a physical architectural event. See ¶ 36-41).
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It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Flynn to including hardware for multiple processing elements that save the architectural state information for multiple processing elements, as taught by Stillwel, Jr., in order to move one processing element’s state to another processing element efficiently an quickly utilizing hardware support.
In regard to claims 5, 17, Stillwell Jr. et al. disclose wherein the at least one sequencing element is configurable to trigger or skip the saving and restoration of the architecture state information (in Stillwell, JR., an event register to hold a map of events that may trigger an architectural save state or transfer. See ¶ 28). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Flynn to including hardware for trigger the saving and restoration of the architecture state information, as taught by Stillwel, Jr., in order to move one processing element’s state to another processing element efficiently an quickly utilizing hardware support.
In regard to claims 6, 18, Stillwell Jr. et al. disclose wherein the routing interface allows external access to the architecture state information (in Stillwell Jr., interface module 105 is to communicate with devices external to processor 100, such as system memory 175, a chipset, a northbridge, or other integrated circuit. Memory 175 may be dedicated to processor 100 or shared with other devices in a system. See figure 1, ¶ 20-22). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Flynn to including hardware for communication to external devices, as taught by Stillwel, Jr., in order to move one processing element’s state to another processing element efficiently and quickly utilizing hardware support.
In regard to claim 8, Flynn et al. disclose wherein: the at least one memory comprises at least one architecture state random access memory (RAM); and the routing interface is configured to, while the at least one PE is in the second state, re-route external requests to access the state registers to the architecture state RAM (in Flynn, use a special purpose software routine to save off to memory in response to a sequence of store instructions as much state information from the processor core 2 as was possible and/or desirable, e.g. register contents, program status values, program counter values, configuration register values etc. Once the state data has been safely saved to memory, the system may be powered down with the level shifters in the AHB interface 4. See ¶ 38). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Flynn to including hardware for saving and restore the architectural state information, as taught by Stillwel, Jr., in order to move one processing element’s state to another processing element efficiently and quickly utilizing hardware support.
In regard to claim 9, Stillwell Jr. et al. disclose wherein the architecture state information comprises information associated with different hierarchical levels (in Stillwell, JR., where a saved state held in memory, such as saved state 231, includes a predefined size and a predetermined structure, i.e. location of information for specific saved architectural state registers, no size value is needed as the predetermined structure allows saving of specific architectural state information to set offsets from a base address. Saving of an architectural state of core 205 to memory 230 is in response to a save architectural state event. In one embodiment, a save architectural state event includes a physical architectural event, such as a core failure, a core failure event, a pipeline stall, a long latency event, a mis-predicted path/branch, receiving an interrupt, entering/exiting power, management, or secure environment states, or other known physical architectural event. See ¶ 37-38). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Flynn to including hardware to save the architectural state information for multiple processing elements, as taught by Stillwel, Jr., in order to move one processing element’s state to another processing element efficiently and quickly utilizing hardware support.
In regard to claim 10, Stilwell Jr. et al. disclose wherein the at least one sequencing element comprises a sequencing element per hierarchical level at which architecture state information is saved (in Stillwell, JR., EVE 208 includes a plurality of fields that correspond to save state events. In a specific illustrative embodiment, EVE 208 includes a bitmap of save architectural state events. Each bit essentially operates as a flag to indicate if an associated save architectural save state event has occurred. See ¶ 41-42). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Flynn to including hardware to save the architectural state information for multiple processing elements, as taught by Stillwel, Jr., in order to move one processing element’s state to another processing element efficiently and quickly utilizing hardware support.
In regard to claim 11, Stillwell Jr. et al. disclose wherein the at least one sequencing element comprises a single sequencing element capable of saving architecture state information at different hierarchical levels (in Stillwell, JR., EVE 208 includes a plurality of fields that correspond to save state events. In a specific illustrative embodiment, EVE 208 includes a bitmap of save architectural state events. Each bit essentially operates as a flag to indicate if an associated save architectural save state event has occurred. See ¶ 41-42). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Flynn to including hardware to save the architectural state information for multiple processing elements, as taught by Stillwel, Jr., in order to move one processing element’s state to another processing element efficiently and quickly utilizing hardware support.
In regard to claim 12, Stillwell Jr. et al. disclose wherein the saving comprises: saving architecture state information associated with a first hierarchical level at a memory associated with a second hierarchical level (in Stilwell, Jr., some of registers 206-208, 211-212, 215, and 220 may be referred to as being included with architectural state registers of cores 205 and 210, such as within the architectural states 101a, 101b, 102a, and 102b of FIG. 1. Here, registers, such as destination registers 206 may be replicated in each architectural state for every hardware thread and/or core. See ¶ 33-36). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Flynn to including hardware to save the architectural state information for multiple processing elements, as taught by Stillwel, Jr., in order to move one processing element’s state to another processing element efficiently and quickly utilizing hardware support.
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
7. Claims 7 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 7 and 19 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein the at least one sequencing element is configured to signal the at least one routing interface to block access to the architecture state information while the at least one PE is in the second state.
Conclusion
9. Claims 1-6, 8-18, 20 are rejected. Claims 7 and 19 are objected.
10. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Mukherjee (US Pub No. 2006/0149940) discloses a method and apparatus for enabling a processor to perform a save and restore on a context switch incrementally and on demand.
Laney et al. (US No. 5,710,930) disclose a method includes the step of detecting if the computer system is to be powered off. If the computer system is detected to be powered off, the state of the computer system is then preserved by storing data representing the state of the computer system in a designated area of a nonvolatile memory of the computer system. A system initialization code of the operating system is then replaced with new system initialization code that branches to restart code that accesses to the designated area of the nonvolatile memory such that when the computer system is again powered on, the restart code accesses the designated area of the nonvolatile memory for the data to restore the computer system to the state before the computer system was powered off.
Garcia Redondo (US Pub No. 2023/0376218) disclose in response to a power-loss warning event occurring during data processing, a checkpointing process is performed to save a checkpoint of context data associated with the data processing to non-volatile data storage. In response to detection of a power recovery event occurring when the checkpointing process is still in progress, it is determined whether a checkpoint abort condition is satisfied, based at least on a checkpoint progress indication indicative of progress of the checkpointing process.
Cheng et al (US Pub No. 2018/0329818) disclose in response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.
Booth et al. (US No. 9,830,257) disclose upon normal shutdown or restart of the data storage system, it may save or flush host data from the buffer to the non-volatile memory array along with performing other shutdown operations.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175