DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
This communication is considered fully responsive to the Amendment filed on 3/18/26.
Response to Arguments
Applicant’s 3/18/26 arguments with respect to claims have been considered but are moot in view of new ground(s) of rejection.
Claim Interpretation
With respect to claimed “as a waypoint” in claims 6, 15 and 20: “... receiving input from a user that specifies the source and destination ports and at least one crossbar switch chip as a waypoint on the path, wherein the heuristic to identify the plurality of selected hops selects a connection point on the user-specified crossbar switch chip” based on IFW [0051] disclosure “... the user may want the routed path to include crossbar B as a waypoint and thus can specify crossbar B as a waypoint. In some embodiments, the waypoint can be a specific connection point (SerDes) on a specific crossbar switch chip” is broadly interpretable as merely a particular element (such as crossbar or connection point) indicated by a user.
Furthermore, claims 6, 15 and 20 are rejected below as a well-known design choice because receiving input from a user that specifies the source and destination ports and at least one crossbar switch chip as a waypoint on the path and, subsequently, selecting a connection point on the user-specified crossbar switch chip would not have modified the operation of the device, see In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975). Also see rejection of claim 8
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 9, 14, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2014/0098810 to Frey et al. (“Frey”) in view of U.S. Patent Publication No. 2022/0321499 to DiFerdinando et al. (“DF”) and further in view of U.S. Patent Publication No. 2005/0058128 to Carson et al. (“Carson”).
As to claim 1, Frey discloses a method in a network device for configuring a path between a source port on the network device and a destination port on the network device using a plurality of crossbar switch chips (Frey: fig 1-6, [0004-63]: fig 1 & 5-6 ... network apparatus 100 includes fabric chip 100 including port interfaces112a-n and node chips 130a-n communicatively coupled to ports “0” “1” of and crossbar array 120 which includes control crossbar 122 unicast data crossbar 124 and multicast crossbar 126 also communicatively coupled (... network device using a plurality of crossbar switch chips) [0014] ... packets enter the fabric chip 110 through a down-link port of a source node chip which may comprise the same node chip as the destination node chip ... path index ... selects which of active down-link ports will be used for the packet (see with [0014;39] - for configuring a path between a source port on the network device and a destination port on the network device using a plurality of crossbar switch chips) [0017-18; 41] ...for instance, port interface 112a (source port) containing port 2 of fabric chip FC0 350a may be programmed with node chip NC0 311 as a reachable destination chip (destination port) for that port interface 112a (see with [0014;17-18;41] - for configuring a path between a source port on the network device and a destination port on the network device using a plurality of crossbar switch chips) [0039]), the method comprising the network device:
using a reachability table to confirm that the destination port is reachable from the source port chips (Frey: fig 1-6, [0004-63]: fig 1-2 & 5-6 ... fabric chip 110 performs hardware calculations to determine which up-link port(s) the packets will traverse in order to reach those destination node chips and these calculations are defined as port resolution calculations (see with [0025;39] - using a reachability table to confirm that the destination port is reachable from the source port chips) [0018] ... port resolution module 208 uses interpreted destination and path information to index into a look-up table (reachability table) that determines the correction destination NCI block 202 in a different port interface 112b-n of fabric chip 110 (see with [0018;39] - using a reachability table to confirm that the destination port is reachable from the source port chips) [0025] ... for instance, port interface 112a (source port) containing port 2 of fabric chip FC0 350a may be programmed with node chip NC0 311 as a reachable destination chip (destination port(s)) for that port interface 112a (see with [0018;25] - using a reachability table to confirm that the destination port(s) is reachable from the source port chips)) [0039]).
Frey did not explicitly disclose using a heuristic to identify a plurality of selected hops from a plurality of Layer 1 forwarding tables, wherein each selected hop represents a connection point on one of the crossbar switch chips.
DF discloses using a heuristic to identify a plurality of selected hops from a plurality of Layer 1 forwarding tables, wherein each selected hop represents a connection point on one of the crossbar switch chips (DF: fig 1-20, [0056-140]: ... a single port switch element instantiated on an integrated circuit having input and output connections for communicating with other single port switch elements (a plurality of selected hops from a plurality of Layer 1 ... wherein each selected hop represents a connection point on one of the crossbar switch chips) and with input/output (I/O) transceiver element for transferring (forwarding) data packets there between and configured to reduce the number of transceiver hops needed to progress a data packet (using a heuristic to identify a plurality of selected hops from a plurality of Layer 1 ...) from a source external I/O port to a destination external I/O port ... a single port forwarding engine element co-located with (each of) the single port switch engine element (a plurality of Layer 1 forwarding tables) that forwards the data packet between the I/O transceiver at the external interface and the other switch elements (a plurality of selected hops) at the internal switch interface according to a network address identifier and mapping table (using a heuristic to identify a plurality of selected hops from a plurality of Layer 1 forwarding tables) [0047] ... the I/O switch module comprises a sequencer module configured to interface with an external controller according to a predetermined protocol to obtain routing information and LAN topology for data packet routing out of the I/O switch flow module [0049]).
Frey and DF are analogous art because they are from the same field of endeavor with respect to crossbar switch elements.
Before the effective filing date, for AIA , it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by DF into the method by Frey. The suggestion/motivation would have been to provide steps for sending data packets through semiconductor crossbar switch elements and electrical mesh interconnects (DF: [0128]).
Frey and DF further disclose wherein the plurality of selected hops represents a first connection point on a first crossbar switch chip to which the source port is connected, a second connection point on a second crossbar switch chip to which the destination port is connected, and one or more intermediate connection points on respective intermediate crossbar switch chips between the first and second crossbar switch chips (DF: fig 1-20, [0056-140]: ... the term “hop” represents a single physical hop that includes a direct physical connection between two devices and, similarly stated, a single physical hop can be defined as traversing or routing a data packet traversing through an integrated circuit e.g. FPGA or other programmable device and any one set of its transceivers or SERDES on a switching element [0092] ... fig 6C is an example showing a LUT (lookup table) wherein 11 bit field is stored, including 4 bits for line card identification e.g. line card 1-16, 2 bits for FPGA identification on the line card e.g. FPGA 1-3 (1st 2nd ... n crossbar switch chips) and 5 bits of I/O in order to map to 32 different I/O ports (1st 2nd ... n connection points on 1st 2nd ... n crossbar switch chips) and a 2 bit field identifying whether the packet at that particular FPGA is to be routed via direct electrical mesh (see with [0092] - plurality of selected hops represents ...) or whether routing is merely internal to the particular FPGA and/or line card associated with that FPGA and therefore not sent via the electrical mesh fabric interconnect e.g. source and destination on one of the FPGA’s on the same line card [0131];
Frey: fig 1-6, [0004-63]: fig 1-2 & 5-6 ... port interfaces 112a-n are communicatively coupled to a crossbar array 1208 (1st 2nd ... n crossbar switch chips) depicted as including control crossbar 122, unicast data crossbar 124 and multicast crossbar 126 (1st 2nd ... n connection points on 1st 2nd ... n crossbar switch chips) ... thus, for instance, the another network apparatus 150 may include a plurality of node chips 130a-n communicatively coupled to fabric chip 110 of network apparatus 100 may be connected to another to fabric chip 110 of another network apparatus 150 through respective port interfaces 112a in various manners as discussed (1st 2nd ... n connection points on 1st 2nd ... n crossbar switch chips) ... node chips 130a-n comprise ASICs that enable user-ports and fabric chip 110 to interface each other and, although not shown, each of node chips 130a-n include user-port through which data, such as packets, may be inputted to and/or outputted from node chips 130a-n (plurality of selected hops represents ...) [0014-15]); and
programming the first, second, and intermediate crossbar switch chips to create a path between the source and destination ports (DF: fig 1-20, [0056-140]: fig 2A-D ... vertical backplane electrical mesh interconnect structure is configured as (programming ...) having 72 differential pairs of signals Tx/Rx (between the source and destination ports) and each semiconductor switch element associated with each line card has 3 FPGAs per line card (programming the first, second, and intermediate crossbar switch chips ...), thus, 48 FPGA chips may be accessed such that for 72 differential pairs, the pathways traverse various connectors (...to create a path between the source and destination ports) [0114]).
Same motivation applies as mentioned above to make the proposed modification.
Frey did not explicitly disclose connection points on one or more crossbar switch chips between the first and second crossbar switch chips selected from among the plurality of crossbar switches in the network device.
Carson discloses connection points on one or more crossbar switch chips between the first and second crossbar switch chips selected from among the plurality of crossbar switches in the network device (Carson: fig 1-18, [0011-92]: fig 3 ... simplified block diagram of an NxN crossbar switch 112 implemented in crosspoint arrangement with switching elements located at each node or crosspoint 113 (connection points on one or more crossbar switch chips between 1st 2id ... n crossbar switch chips selected from among the plurality of crossbar switches in the network device) [0022] fig 7-12 ... three-stage switching network 600 ... there are three stacks - two stacks of switch modules 621, 622 and one stack 623 of switch/scheduler modules and each stack 621, 622 and 623 contains sixteen IC switching layers that have a crossbar chip 642 (see with [0022;92; 74; 67] - connection points on one or more crossbar switch chips between the first and second crossbar switch chips selected from among the plurality of crossbar switches in the network device) and switch/scheduler stack 623 includes suitable circuitry for implementing the controlled traversal of the switching network 600 (... selected from among the plurality of crossbar switches in the network device) [0077] ... individual I/O pads (connection points) of switching element circuits 142 are routed to the edge of one or more IC switching layers 113 of a stack using metalized traces 205 to form a T-connect structure 200 (see with [0022;77;74] above - connection points on one or more crossbar switch chips between the first and second crossbar switch chips) [0092] ... interconnecting first and second stacks 140, 160 of IC switching layers 113 where the layers are situated parallel to a common substrate 151 and where the switching layers 113 of each stack are connected to the switching layers of the other stack via “area connections” that ripple down through the layers 113 to the bottom of each stack 140, 160 and suitable traces 152 on the common substrate 151 (see with [0022;77;92] above - connection points on one or more crossbar switch chips between the first and second crossbar switch chips) [0074] ... compact switching network 100 of this embodiment is formed from first and second stacks 140, 160 of IC switching layers 113 stacked in physical contact with one another, each IC switching layer 113 containing at least one switching element circuit e.g. 142, 162 of fig 10 and the compact switching network 100 further comprises means 150 for interconnecting the interface conductors of the first stack 140 of IC layers to the interface conductors of the second stack 160 of IC layers to form the overall, compact multi-stage switching network 100 [0067]).
Frey, DF and Carson are analogous art because they are from the same field of endeavor with respect to switches.
Before the effective filing date, for AIA , it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Carson into the method by Frey and DF. The suggestion/motivation would have been to provide a data switch that offer many ports (hundreds or thousands) while being compactly constructed with short interconnects and a data switch that operates at very high data rates (Carson: [0040]).
As to claim 5, Frey, DF and Carson disclose wherein the heuristic to identify the plurality of selected hops is based on minimizing rerouting of previously programmed paths between pairs of ports on the network device (DF: fig 1-20, [0056-140]:... CLOS switching embodiment includes multi-chassis link aggregation group (MLAG or MCLAG) and servers can be connected to two different leaf 110’ or TOR 101 switches in order to have redundancy and load balancing capability (i.e. as is known by ordinary persons of the art, MLAG or MCLAG allows two or more physical switches to appear as a single logical switch to other network devices and If one of the physical switches in the MLAG group fails, traffic can continue to flow through the other active switch(es) over the remaining active links without requiring a change in the routing (i.e. minimizing rerouting) or forwarding paths from the perspective of pairs of ports connected) [0088]).
For motivation, see rejection of claim 1.
As to claims 9 and 16, see similar rejection to claim 1, where the device and storage device, respectively, is/are taught by the method.
As to claims 14 and 19, see similar rejection to claim 5, where the device and storage device, respectively, is/are taught by the method.
Claims 2-4, 12-13 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2014/0098810 to Frey et al. (“Frey”) in view of U.S. Patent Publication No. 2022/0321499 to DiFerdinando et al. (“DF”), U.S. Patent Publication No. 2005/0058128 to Carson et al. (“Carson”) and further in view of U.S. Patent No. 6160811 to Partridge et al. (“PT”) incorporating by reference of U.S. Patent No. 5734649 to Carvey et al. (“CV”).
As to claim 2, Frey, DF and Carson disclose the method of claim 1.
For motivation, see rejection of claim 1.
Frey did not explicitly disclose wherein using a heuristic to identify the plurality of selected hops comprises: [ a ] identifying a set of one or more candidate hops that are connected to a current hop using the Layer 1 forwarding tables; [ b ] using the heuristic to select a hop from the set of candidate hops as the next current hop; and repeating [ a ] and [ b ] until the current hop reaches the second connection point.
PT incorporating by reference CV discloses wherein using a heuristic to identify the plurality of selected hops comprises: [ a ] identifying a set of one or more candidate hops that are connected to a current hop using the Layer 1 forwarding tables (PT: fig 1-5, col 2-col 8 ll 1-7: ... function cards 33-35 are so-called forwarding engines (FE) ... each of the port or line interface cards 20-32 comprise both a to-switch-unit (TSU) and a from-switch (FSU) ... it is the function of crossbar switch 10 to connect any TSU to any FSU and connect input and output paths on forwarding engines 33-35 (identifying ... using the Layer 1 forwarding tables) (col 3 ll 8-34) ... a main function of each of the forwarding engines is to make so-called “next hop” determinations i.e. determine the data link through which a packet should be next sent .. each of the forwarding engines employs a processor ...the data structure given to a TSU “bids”, each of which identifies a data packet seeking to utilize a particular crossbar switch point (current hop) (... identify the plurality of selected hops comprises: [ a ] identifying a set of one or more candidate hops that are connected to a current hop using the Layer 1 forwarding tables) ... network processor loads into each interface card a table of information which allows each TSU to identify (using a heuristic ...) those types of incoming packets or ATM cells which may arrive at that particular unit ... identifies, for each type of packet expected, a particular one of the forwarding engines which should make the next hop decisions for the particular type of packet (wherein using a heuristic to identify the plurality of selected hops comprises: [ a ] identifying a set of one or more candidate hops that are connected to a current hop using the Layer 1 forwarding tables) (col 4 ll 21-67 & col 5 ll 1-2));
[ b ] using the heuristic to select a hop from the set of candidate hops as the next current hop (PT: fig 1-5, col 2-col 8 ll 1-7: ... the principle task of each of the forwarding engines is to determine which output port (FSU) each incoming packet should be sent ... the TSU can formulate a “bid” do the switch allocator seeking connection to a FSU in the selected outgoing port ( see with CV col 6 ll 61-67 & col 7 ll 1-9 & col 4 ll 65-67 & col 5 ll 1-6 - [ b ] using the heuristic to select a hop from the set of candidate hops as the next current hop) (col 5 ll 3-18);
CV: fig 1-8, col 2-col 8 ll 1-12: ... the shuffling or random assigning of inputs to rows in a data array and random assigning of outputs to columns is a simple table lookup procedure using a table which is filled with previously calculate pseudo-random assignment patters and using a table lookup allows for very fast determination of a new assignment pattern ... using pre-calculated table facilitates a hierarchical prioritizing of input ports ([b] using the heuristic to identify ...) (col 6 ll 61-67 & col 7 ll 1-9) ... allocator 41 does not merely examine pending bids for each switch point individually or sequentially but, rather, implements a procedure processing a high degree of parallelism so that multiple cells are tested simultaneously to see if there are pending requests with could utilize that point ([b] using the heuristic to identify a next crossbar switch chip) ... the procedure can enforce a selectable degree of fairness in allocation ([b] using the heuristic to identify a next crossbar switch chip) (col 4 ll 65-67 & col 5 ll 1-6)); and
repeating [ a ] and [ b ] until the current hop reaches the second connection point (PT: fig 1-5, col 2-col 8 ll 1-7: ... the processor in that FSU is then tasked with creating a link level appropriate header suitable for transmission over the next link ... the forwarding engine, using the respective routing table information downloaded to it, determines the output port for the packet’s next hop as indicated at block 107 ... as indicated at block 111 that to-switch-unit (TSU) then sends the entire packet with header and the output token to the FSU determined by the forwarding engine (repeating [ a ] and [ b ] until the current hop reaches the second connection point) (col 5 ll 17-34)).
Frey, DF, Carson and PT incorporating by reference CV are analogous art because they are from the same field of endeavor with respect to crossbar switch elements.
Before the effective filing date, for AIA , it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by PT incorporating by reference CV into the method by Frey, DF and Carson. The suggestion/motivation would have been to provide forwarding engines which define the correspondence between network packet addresses and corresponding appropriate connections through crossbar switches (PT: col 3 ll 65-67 & col 4 ll 1-2) and incorporating by reference CV (PT: col 1 ll 50-57)..
As to claim 3, see similar rejection to claim 2 where method is taught by the method.
As to claim 3, Frey, DF, Carson and PT incorporating by reference CV further disclose [a] using the heuristic to identify a next crossbar switch chip (PT: fig 1-5, col 2-col 8 ll 1-7: ... the principle task of each of the forwarding engines is to determine which output port (FSU) each incoming packet should be sent ... the TSU can formulate a “bid” do the switch allocator seeking connection to a FSU in the selected outgoing port ( see with CV col 6 ll 61-67 & col 7 ll 1-9 & col 4 ll 65-67 & col 5 ll 1-6 - [ a ] using the heuristic to select a hop from the set of candidate hops as the next current hop) (col 5 ll 3-18);
CV: fig 1-8, col 2-col 8 ll 1-12: ... the shuffling or random assigning of inputs to rows in a data array and random assigning of outputs to columns is a simple table lookup procedure using a table which is filled with previously calculate pseudo-random assignment patters and using a table lookup allows for very fast determination of a new assignment pattern ... using pre-calculated table facilitates a hierarchical prioritizing of input ports ([a] using the heuristic to identify ...) (col 6 ll 61-67 & col 7 ll 1-9) ... allocator 41 does not merely examine pending bids for each switch point individually or sequentially but, rather, implements a procedure processing a high degree of parallelism so that multiple cells are tested simultaneously to see if there are pending requests with could utilize that point ([a] using the heuristic to identify a next crossbar switch chip) ... the procedure can enforce a selectable degree of fairness in allocation ([a] using the heuristic to identify a next crossbar switch chip) (col 4 ll 65-67 & col 5 ll 1-6)); and
[ b ] identifying a hop that is connected to the next crossbar switch chip using the Layer 1 forwarding tables (PT: fig 1-5, col 2-col 8 ll 1-7: ... function cards 33-35 are so-called forwarding engines (FE) ... each of the port or line interface cards 20-32 comprise both a to-switch-unit (TSU) and a from-switch (FSU) ... it is the function of crossbar switch 10 to connect any TSU to any FSU and connect input and output paths on forwarding engines 33-35 (identifying ... using the Layer 1 forwarding tables) (col 3 ll 8-34) ... a main function of each of the forwarding engines is to make so-called “next hop” determinations i.e. determine the data link through which a packet should be next sent .. each of the forwarding engines employs a processor ...the data structure given to a TSU “bids”, each of which identifies a data packet seeking to utilize a particular crossbar switch point (current hop) ( [ b ] identifying a hop that is connected to the next crossbar switch chip using the Layer 1 forwarding tables) ... network processor loads into each interface card a table of information which allows each TSU to identify (using a heuristic ...) those types of incoming packets or ATM cells which may arrive at that particular unit ... identifies, for each type of packet expected, a particular one of the forwarding engines which should make the next hop decisions for the particular type of packet ([ b ] identifying a hop that is connected to the next crossbar switch chip using the Layer 1 forwarding tables) (col 4 ll 21-67 & col 5 ll 1-2));
repeating [ a ] and [ b ] until the current hop reaches the second connection point (PT: fig 1-5, col 2-col 8 ll 1-7: ... the processor in that FSU is then tasked with creating a link level appropriate header suitable for transmission over the next link ... the forwarding engine, using the respective routing table information downloaded to it, determines the output port for the packet’s next hop as indicated at block 107 ... as indicated at block 111 that to-switch-unit (TSU) then sends the entire packet with header and the output token to the FSU determined by the forwarding engine (repeating [ a ] and [ b ] until the current hop reaches the second connection point) (col 5 ll 17-34)).
For motivation, see rejection of claim 2.
As to claim 4, Frey, DF, Carson and PT incorporating by reference CV disclose wherein the heuristic to identify the plurality of selected hops is based on minimizing latency between hops (PT: fig 1-5, col 2-col 8 ll 1-7: ... the next hop determination is in one sense a simple set of tasks but is demanding in terms of speed and is preferably performed by a high speed microcomputer (the heuristic to identify the plurality of selected hops is based on minimizing latency between hops) (col 4 ll 33-41);
DF: fig 1-20, [0056-140]: ... reduction in the number of physical hops among line cards or integrated circuits on the line cards significantly reduces electrical power consumption and significantly increases speed (latency) [0032] ... switch ... configured to reduce the number of transceiver hops needed to progress a data packet from a source port to destination port (the heuristic to identify the plurality of selected hops is based on minimizing latency between hops)... according to a network address identifier and mapping table [0047]).
For motivation, see rejection of claim 2.
As to claims 12-13, see similar rejection to claims 2 and 4, respectively, where the device is taught by the method.
As to claims 17-18, see similar rejection to claims 2 and 4, respectively, where the storage device is taught by the method.
Claims 6, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2014/0098810 to Frey et al. (“Frey”) in view of U.S. Patent Publication No. 2022/0321499 to DiFerdinando et al. (“DF”), U.S. Patent Publication No. 2005/0058128 to Carson et al. (“Carson”) and further in view of U.S. Patent No. 8687629 to Kompella et al. (“Kompella”).
As to claim 6, Frey, DF and Carson disclose the method of claim 1.
For motivation, see rejection of claim 1.
Frey did not explicitly disclose further comprising receiving input from a user that specifies the source and destination ports and at least one crossbar switch chip as a waypoint on the path, wherein the heuristic to identify the plurality of selected hops selects a connection point on the user-specified crossbar switch chip.
Kompella discloses further comprising receiving input from a user that specifies the source and destination ports and at least one crossbar switch chip as a waypoint on the path (Kompella: fig 1-9, col 5-19 ll 1-60: fig 3 ... administrator 49 interacts with management daemon 54 of SCC 36 via a command line interface (CLI) 52 to perform various management tasks (receiving input from a user ...) ... in one example, administrator 49 may configure LCs as packet line cards and circuit line cards ... administrator 49 may configure individual ports on fabric chips (not shown) (... and at least one crossbar switch chip as a waypoint on the path) of switch fabric 35 as either packet ports or circuit ports ... administrator 49 may configure a multi-chassis router 28 with configuration data to associated a first port on a circuit card with a second port on a circuit line card which may be the same or different circuit line card that contains the first port for purposes of incoming and outgoing traffic (... specifies the source and destination ports), that is, the administrator 49 can designate that circuit-switched data received on one port of a line card are output on a second port of a line card (... specifies the source and destination ports) (col 13 ll 9-36)),
wherein the heuristic to identify the plurality of selected hops selects a connection point on the user-specified crossbar switch chip (Kompella: fig 1-9, col 5-19 ll 1-60: fig 3 ... in response, to receiving configuration data from the administrator 49, management daemon 54 determines which circuit ports of fabric cards within the stages of switch fabric 35 will be associated with each other in order to transmit the packets from the ingress line card to the egress line card (wherein the heuristic to identify the plurality of selected hops selects a connection point on the user-specified crossbar switch chip) ... management daemon 54 provides configuration information for configuring switch fabric 35 to fabric controller 56 ... configures the individual fabric chips of switch fabric 35 ... for example, fabric controller 56 may modify a register and a bit map table of each fabric chip to configure the ports of the fabric chip as either packet ports or circuit ports (col 13 ll 9-43)).
Frey, DF, Carson and Kompella are analogous art because they are from the same field of endeavor with respect to configuration.
Before the effective filing date, for AIA , it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Kompella into the method by Frey, DF and Carson. The suggestion/motivation would have been to provide a command line interface (CLI) by which an administrator interacts with a management daemon to perform various tasks (Kompella: col 13 ll 9-36).
Furthermore, claim 6 is rejected below as a well-known design choice because receiving input from a user that specifies the source and destination ports and at least one crossbar switch chip as a waypoint on the path and, subsequently, selecting a connection point on the user-specified crossbar switch chip would not have modified the operation of the device, see In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).
As to claims 15 and 20, see similar rejection to claim 6 where the device and storage device, respectively, is/are taught by the method.
Claims 7-8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2014/0098810 to Frey et al. (“Frey”) in view of U.S. Patent Publication No. 2022/0321499 to DiFerdinando et al. (“DF”), U.S. Patent Publication No. 2005/0058128 to Carson et al. (“Carson”) and further in view of U.S. Patent No. 11496391 to Przygienda et al. (“Prz”).
As to claim 7, Frey, DF and Carson disclose the method of claim 1.
For motivation, see rejection of claim 1.
Frey did not explicitly disclose receiving a topology description that describes the plurality of crossbar switches and connectivity between connection points on the plurality of crossbar switch chips; generating the reachability table from the topology description; and generating the Layer 1 forwarding tables from the topology description.
Prz disclose receiving a topology description that describes the plurality of crossbar switches and connectivity between connection points on the plurality of crossbar switch chips; generating the reachability table from the topology description; and generating the Layer 1 forwarding tables from the topology description (Prz: fig1-15, col 5-12: fig 6B ... in the example, leaf node A will receive IP prefix alpa/24 as both an L2 prefix and L1-down prefix ... and store IP prefix alpa/24 as both an L2 prefix and L1-down prefix link state information e.g. in a link state database 610 – and see fig 6B – table 610 is “network topology information” with fields “type” “reachable destinations” (generating the reachability table from the topology description) “adjacency” “cost” values based on the topology description having ToF nodes, internal nodes and leaf nodes that are all switches (topology description that describes the plurality of crossbar switches) and connectivity 550a-d (connectivity between connection points on the plurality of crossbar switch chips) and table 620 is “forwarding information e.g. FIB” with fields Dest. And Next Hop (generating the Layer 1 forwarding tables from the topology description) (col 8 ll 5-39)).
Frey, DF, Carson and Prz are analogous art because they are from the same field of endeavor with respect to provisioning.
Before the effective filing date, for AIA , it would have been obvious to a person of ordinary skill in the art to incorporate the strategies by Prz into the method by Frey, DF and Carson. The suggestion/motivation would have been to provide provisioning networks in a manner that is scalable and considers otherwise hidden topology information when computing routes (Prz: col 5 ll 58-67).
As to claim 8, see similar rejection to claim 7 where the method is taught by the method.
As to claim 8, Frey, DF, Carson and Prz further disclose further comprising performing generating the reachability and Layer 1 forwarding tables autonomously absent user intervention (Prz: fig1-15, col 5-12: fig 6A illustrates use of L2 link state advertisements (LSAs) and leaking from L2 to L1 to propagate prefix information (autonomously absent user intervention) in example environment of fig 4 and fig 6B illustrates example network topology information and forwarding information stored in leaf node A (see details in rejection claim 7 of fig 6B - performing generating the reachability and Layer 1 forwarding tables autonomously absent user intervention) (col 5 ll 22-29) ).
For motivation, see rejection of claim 7.
Furthermore, claim 8 is rejected below as a well-known design choice because performing generating the reachability and Layer 1 forwarding tables autonomously absent user intervention would not have modified the operation of the device, see In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).
As to claim 10, see similar rejection to claims 7-8 where the device is taught by the method.
As to claim 11, see similar rejection to claims 1 and 7-8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUNE SISON whose telephone number is (571)270-5693. The examiner can normally be reached 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Emmanuel Moise can be reached at 571-272-3865. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNE SISON/Primary Examiner, Art Unit 2455
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