Prosecution Insights
Last updated: April 19, 2026
Application No. 18/758,015

NONVOLATILE MEMORY INTERFACE CIRCUIT, STORAGE DEVICE HAVING THE SAME AND METHOD OF OPERATING THE SAME

Non-Final OA §112
Filed
Jun 28, 2024
Examiner
KING, DANIEL JOHN
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allow Rate
50 granted / 52 resolved
+28.2% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
19 currently pending
Career history
71
Total Applications
across all art units

Statute-Specific Performance

§103
23.2%
-16.8% vs TC avg
§102
29.2%
-10.8% vs TC avg
§112
46.0%
+6.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 52 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 sets forth “capture a data signal using a data strobe signal delayed based on offset information”, and also sets forth “delaying the data strobe signal using first offset information”, and also sets forth “delaying the data strobe signal using second offset information. This language is indefinite. It is unclear if “offset information” is to be broadly interpreted as including “first offset information” and “second offset information”, if each instance of “offset information”, “first offset information”, and/or “second offset information” is intended to be interpreted as an entirely separate group of “offset information”, or if there is some other intended interpretation. Appropriate clarification is required. Claims 2-10 are rejected as dependent upon claim 1. Claim 6 sets forth “to generate a first error count”. Claim 1 also sets forth “configured to determine a first error count”. This language is unclear. It is unclear if each instance of “a first error count” is intended to be interpreted as the same “error count” or a different error count. Appropriate clarification is required. Claims 7-9 are rejected as dependent upon claim 6. Claim 6 sets forth “to generate a second error count”. Claim 1 also sets forth “and determine a second error count”. This language is unclear. It is unclear if each instance of “a second error count” is intended to be interpreted as the same “error count” or a different error count. Appropriate clarification is required. Claims 7-9 are rejected as dependent upon claim 6. Further search and consideration required upon resolution of indefiniteness issues. Relevant prior art not relied upon is made of record: US8565034 (Lu, et al.) US7323903 (Lee, et al.) Allowable Subject Matter Claims 11-20 allowable. The prior art of record does not appear to teach a nonvolatile memory interface circuit comprising: a first delay line configured to receive a data signal and output a delayed data signal; a second delay line configured to receive a data strobe signal and output a plurality of sampling data strobe signals by delaying the data strobe signal; an output circuit configured to output the delayed data signal as read data in response to the data strobe signal; and an off-chip compensation logic configured to detect off-chip variation in real time by comparing the read data with sampling data corresponding to the plurality of sampling data strobe signals, and to compensate for the off-chip variation; and/or a storage device comprising: at least one nonvolatile memory device; and a controller configured to control the at least one nonvolatile memory device, wherein the controller includes a nonvolatile memory interface circuit configured to communicate with the at least one nonvolatile memory device through at least one channel, wherein the nonvolatile memory interface circuit includes: a margin collector configured to collect margin information by comparing read data with sampling data; an on-chip margin search logic configured to track a valid window margin by adjusting an offset value based on the margin information; and a compensation calculator configured to determine off-chip variation corresponding to the offset value when the valid window margin is in a margin lock state. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL JOHN KING/Examiner, Art Unit 2827 /HUAN HOANG/Primary Examiner, Art Unit 2827
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Prosecution Timeline

Jun 28, 2024
Application Filed
Dec 27, 2025
Non-Final Rejection — §112
Apr 03, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

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READ CIRCUIT AND MEMORY SYSTEM
2y 5m to grant Granted Apr 07, 2026
Patent 12580030
DYNAMIC BIT LINE VOLTAGE DURING PROGRAM VERIFY TO PROVIDE MORE THRESHOLD VOLTAGE BUDGET
2y 5m to grant Granted Mar 17, 2026
Patent 12567448
STORAGE DEVICE
2y 5m to grant Granted Mar 03, 2026
Patent 12562232
NON-VOLATILE MEMORY WITH CONCURRENT PROGRAMMING
2y 5m to grant Granted Feb 24, 2026
Patent 12542164
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2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+5.6%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 52 resolved cases by this examiner. Grant probability derived from career allow rate.

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