DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: Claim 5 currently depends from claim 1. Claim 5 should depend from Claim 4. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fuji et al. (US Publication 2018/0108480) in view of Abe et al. (US Publication 2012/0073129).
In re claim 1, Fuji discloses a multilayer ceramic capacitor comprising:
a multilayer body (12 – Figure 1, ¶38) including a plurality of dielectric layers (14 – Figure 2, ¶38) stacked, and a plurality of internal electrode layers (16, 18 – Figure 2, Figure 3, ¶44) each stacked on an associated one of the dielectric layers (Figure 2, Figure 3), the multilayer body including first and second main surfaces (12a, 12b – Figure 1, Figure 2, ¶40) that face each other in a lamination direction (‘X’ direction – Figure 1)(Figure 2, Figure 3), first and second end surfaces (12c, 12d – Figure 1, Figure 2, ¶40) that face each other in a length direction (‘Y’ direction – Figure 1, Figure 2) orthogonal or substantially orthogonal to the lamination direction (Figure 1, Figure 2, Figure 3), and first and second lateral surfaces (12e, 12f – Figure 1, ¶40) that face each other in a width direction (‘Z’ direction – Figure 1) orthogonal or substantially orthogonal to the lamination direction and the length direction (Figure 1);
the plurality of internal electrode layers further including a plurality of first internal electrode layers (16 – Figure 2, Figure 4) on the plurality of dielectric layers (14 – Figure 2), the first internal electrode layers extending to the first and second end surfaces (12c, 12d – Figure 1), and a plurality of second internal electrode layers (18 – Figure 3, Figure 4) on the plurality of dielectric layers (14 – Figure 3), the second internal electrode layers extending to the first and second lateral surfaces (12e, 12f – Figure 3);
a first external electrode (20 – Figure 2, ¶52) on the first end surface (12c – Figure 2), the first external electrode being connected to the first internal electrode layers (16 – Figure 2);
a second external electrode (22 – Figure 2, ¶53) on the second end surface (12d – Figure 2), the second external electrode being connected to the first internal electrode layers (16 – Figure 2);
a third external electrode (24 – Figure 1, Figure 3, ¶54) on the first lateral surface (12e – Figure 3), the third external electrode being connected to the second internal electrode layers (18 – Figure 3); and
a fourth external electrode (26 – Figure 1, Figure 3, ¶39) on the second lateral surface (12f – Figure 3), the fourth external electrode being connected to the second internal electrode layers (18 – Figure 3);
the first internal electrode layers each including a first counter electrode portion (16a – Figure 4, ¶45) that faces an associated one of the second internal electrode layers (18 – Figure 2, Figure 3) with one of the dielectric layers (14 – Figure 2, Figure 3) interposed between the first counter electrode portion and the associated one of the second internal electrode layers (Figure 4), a first extension portion (16b – Figure 4A, ¶45) extending from the first counter electrode portion (16a – Figure 4A) to the first end surface (12c – Figure 4A), and a second extension portion (16c – Figure 4A, ¶45) extending from the first counter electrode portion to the second end surface (12d – Figure 4A);
the second internal electrode layers (18 – Figure 4B) each including a second counter electrode portion (18a – Figure 4B, ¶46) that faces an associated one of the first internal electrode layers (16 – Figure 2, Figure 3, Figure 4) with one of the dielectric layers (14 – Figure 2, Figure 3, Figure 4) interposed between the second counter electrode portion and the associated one of the first internal electrode layers (16 – Figure 4), a third extension portion (18b – Figure 4B, ¶46) extending from the second counter electrode portion (18a – Figure 4B) to the first lateral surface (12e – Figure 4B), and a fourth extension portion (18c – Figure 4B, ¶46) extending from the second counter electrode portion to the second lateral surface (12f – Figure 4B);
a dimension A of each of the first and second extension portions (dimension of 16b, 16c in the ‘z’ direction – Figure 1, Figure 4A) in the width direction being less than a dimension B (dimension of 16a in the ‘z’ direction – Figure 1, Figure 4A) of the first counter electrode portion in the width direction (Figure 1, Figure 4, ¶45; Note that it is preferable for the extension portions to be smaller in width than the counter electrode portion for the purpose of reducing the occurrence of delamination between dielectric layers as stated in [¶45]).
Fuji does not disclose a dimension W1 from a side of each of the first and second extension portions near the first lateral surface to the first lateral surface in the width direction and a dimension W2 from a side of each of the first and second extension portions near the second lateral surface to the second lateral surface in the width direction being each greater than the dimension A of each of the first and second extension portions in the width direction.
Abe discloses a dimension W1 (combination of Wg and D – Figure 4, Figure 10, ¶20) from a side of the extension portion (25 – Figure 10, ¶48) near the first lateral surface to the first lateral surface (5 – Figure 10, ¶43) in the width direction and a dimension W2 (combination of Wg and D – Figure 4, Figure 10) from a side of the extension portion (25 – Figure 10) near the second lateral surface to the second lateral surface (6 – Figure 10, ¶43) in the width direction being each greater than the dimension A of each of the extension portion in the width direction (¶99, Table 1: Sample 5; Note that D having a value of 0.44 mm and Wg having a value of 0.03 mm with a component body width of 1250 mm provides for a extension portion width of 0.310 mm. Further, this translates into an extension portion having a width that is 24.8% of the width of the component body.).
The combination of Fuji and Abe discloses a dimension W1 from a side of each of the first and second extension portions near the first lateral surface to the first lateral surface in the width direction and a dimension W2 from a side of each of the first and second extension portions near the second lateral surface to the second lateral surface in the width direction being each greater than the dimension A of each of the first and second extension portions in the width direction.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the lead width as described by Abe to reduce the occurrences of cracks and improve the capacitance of the electronic component (¶70: Abe).
In re claim 2, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji further discloses wherein the first external electrode (20 – Figure 2) extends from over the first end surface (12c – Figure 2) to over a portion of the first main surface (12a – Figure 2), a portion of the second main surface (12b – Figure 2), a portion of the first lateral surface (12e – Figure 1), and a portion of the second lateral surface (12f – Figure 1);
the second external electrode (22 – Figure 2) extends from over the second end surface (12d – Figure 2) to over a portion of the first main surface (12a – Figure 2), a portion of the second main surface (12b – Figure 2), a portion of the first lateral surface (12e – Figure 1), and a portion of the second lateral surface (12f – Figure 1);
the third external electrode (24 – Figure 3) extends from over the first lateral surface (12e – Figure 3) to over a portion of the first main surface (12a – Figure 3) and a portion of the second main surface (12b – Figure 3); and
the fourth external electrode (26 – Figure 3) extends from over the second lateral surface (12f – Figure 3) to over a portion of the first main surface (12a – Figure 3) and a portion of the second main surface (12b – Figure 3).
In re claim 3, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji does not disclose wherein the dimensions W1 and W2 are each greater than or equal to about 0.375 × W’, where W’ represents a dimension of the multilayer body in the width direction.
Abe discloses wherein the dimensions W1 and W2 (combination of Wg and D – Figure 4, Figure 10) are each greater than or equal to about 0.375 × W’, where W’ represents a dimension of the multilayer body in the width direction (¶99, Table 1: Sample 5; Note that D having a value of 0.44 mm and Wg having a value of 0.03 mm with a component body width of 1250 mm provides for a extension portion width of 0.310 mm. Further, this translates into an extension portion having a width that is 24.8% of the width of the component body. Each of W1 and W2 has a value of 37.6%, or 0.376 of the width of the body.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the lead width as described by Abe to reduce the occurrences of cracks and improve the capacitance of the electronic component (¶70: Abe).
In re claim 4, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji does not disclose wherein the dimension A is equal to or less than about 0.25 × W’, where W’ represents a dimension of the multilayer body in the width direction .
Abe discloses wherein the dimension A is equal to or less than about 0.25 × W’, where W’ represents a dimension of the multilayer body in the width direction (¶99, Table 1: Sample 5; Note that D having a value of 0.44 mm and Wg having a value of 0.03 mm with a component body width of 1250 mm provides for a extension portion width of 0.310 mm. Further, this translates into an extension portion having a width that is 24.8%, or 0.248, of the width of the component body.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the lead width as described by Abe to reduce the occurrences of cracks and improve the capacitance of the electronic component (¶70: Abe).
In re claim 5, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji further discloses wherein a dimension C of each of the third and fourth extension portions in the length direction (dimension of 18a, 18b in the ‘Y’ direction – Figure 1, Figure 4B) is less than a dimension D of the second counter electrode portion in the length direction (dimension of 18a in the ‘Y’ direction – Figure 1, Figure 4B).
In re claim 5, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji further discloses the element body has a length of 1.0 mm and the dimension C is 0.30 mm (See Table 1: Example 8; ‘L’ is the component body length, and ‘a’ is the dimension ‘C’).
Fuji does not disclose wherein the dimension A is equal to or less than about 1.5 times the dimension C.
Abe discloses the dimension A is 0.248 times the width of the component body (¶99, Table 1: Sample 5; Note that D having a value of 0.44 mm and Wg having a value of 0.03 mm with a component body width of 1250 mm provides for a extension portion width of 0.310 mm. Further, this translates into an extension portion having a width that is 24.8%, or 0.248, of the width of the component body.).
The combination of Fuji and Abe discloses wherein the dimension A is equal to or less than about 1.5 times the dimension C (Note that incorporating the extension width ratio into the invention of Fuji produces first and second extension portions having a width of 0.248 mm. This is smaller than the width of the third and fourth extension portions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the lead width as described by Abe to reduce the occurrences of cracks and improve the capacitance of the electronic component (¶70: Abe).
In re claim 7, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji does not disclose wherein a combined total number of the first internal electrode layers and the second internal electrode layers stacked is 200 or more. However it is well-known in the art that adjusting the number of alternating electrode layers is correlated with the overall capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the total number of internal electrode layers to achieve a device having desired capacitance, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 8, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji does not disclose wherein a dimension from the first end surface to the second end surface of the multilayer ceramic capacitor in the length direction is about 1.0 mm, a dimension from the first lateral surface to the second lateral surface of the multilayer ceramic capacitor in the width direction is about 0.7 mm, and a dimension from the first main surface to the second main surface of the multilayer ceramic capacitor in the lamination direction is about 0.5 mm. However, it is well-known in the art that adjusting the area of the internal electrode layers and number of laminated internal electrode and dielectric layers, and thus, the dimensions of the capacitor body, is correlated to the overall capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the size and number of internal electrode and dielectric layers, and thus, component body dimensions, to achieve a device having desired capacitance and desired miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 9, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji further discloses wherein the multilayer body (12 – Figure 1) has a rectangular or substantially rectangular parallelepiped shape (Figure 1).
In re claim 10, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji does not disclose wherein the multilayer body includes corners and ridges that are rounded.
Abe discloses wherein the multilayer body includes corners and ridges that are rounded (¶20) (Table 1: Sample 5).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the rounded corners and ridges to prevent moisture resistant degradation (¶54: Abe).
In re claim 11, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji further discloses wherein the multilayer ceramic capacitor (10 – Figure 1, ¶37) is a three-terminal capacitor (Figure 1; ¶2).
In re claim 12, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 3, as explained above. Fuji does not disclose wherein about 1/2 of the width of the first extension portion is equal to or less than about 1/8 of W’.
Abe discloses wherein about 1/2 of the width of the first extension portion is equal to or less than about 1/8 of W’ (¶99, Table 1: Sample 5; Note that D having a value of 0.44 mm and Wg having a value of 0.03 mm with a component body width of 1250 mm provides for a extension portion width of 0.310 mm. Further, this translates into an extension portion having a width that is 24.8%, or 0.248, of the width of the component body.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the rounded corners and ridges to prevent moisture resistant degradation (¶54: Abe).
In re claim 13, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 3, as explained above. Fuji further discloses wherein each of the plurality of dielectric layers (14 – Figure 2, Figure 3) includes a dielectric ceramic (¶42).
In re claim 14, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 13, as explained above. Fuji further discloses wherein the dielectric ceramic includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 (¶42).
In re claim 15, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 14, as explained above. Fuji further discloses wherein the dielectric ceramic includes a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound (¶42).
In re claim 16, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji further discloses wherein a thickness of each of the plurality of dielectric layers (14 – Figure 2, Figure 3) is about 0.5 μm and equal to or less than about 3.0 μm (¶43).
In re claim 17, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji does not disclose a total number of the plurality of dielectric layers in the multilayer body is 200 or more. However it is well-known in the art that adjusting the number of alternating dielectric layers with internal electrode layers is correlated with the overall capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the total number of dielectric layers to achieve a device having desired capacitance and desired miniaturization characteristics per user specifications, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 18, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji further discloses wherein each of the plurality of internal electrodes (16, 18 – Figure 2, Figure 3) includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd or Au (¶50).
In re claim 19, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 18, as explained above. Fuji further discloses wherein each of the plurality of internal electrodes further include dielectric particles (¶50).
In re claim 20, Fuji in view of Abe discloses the multilayer ceramic capacitor according to claim 1, as explained above. Fuji further discloses wherein a thickness of each of the plurality of internal electrode layers is about 0.4 μm and equal to or less than about 1.5 μm (¶117).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chung et al. (US Patent 8,451,580) Figure 3
Imaeda et al. (US Publication 2017/0345571) Figure 5
Okuda (US Patent 11,404,214) Figure 5
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARUN RAMASWAMY/Primary Examiner, Art Unit 2848