DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/7/26 has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 14-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gouldey (US 20240184702) in view of Punyamurtula (US 20120131305).
With respect to claim 1, the Gouldey reference teaches a processor, comprising:
prefetching circuitry associated with a cache level of a hierarchy of one or more cache levels, (e.g. fig. 5, where system 500 including prefetch circuitry 520 (e.g., a prefetcher) for prefetching one or more cache blocks in a group; and where there’s multiple levels of caches) the prefetching circuitry configured to:
receive a boundary hint from a workload of an execution unit that accesses the cache level; (paragraph 54, where there is a hint operation that may comprise a single posted message. The hint operation can flow from a client to a server as a priority message; and paragraph 55, where the prefetch message (e.g., “Prefetch1 k”) may be a hint operation that sends the following information to a caching agent: address, mask, read, data, temporal, and ascending; and where the ascending bit may indicate if the prefetch should process the block mask in ascending (1) or descending (0) order. For example, a prefetch with address of 0x400, mask of 0x8003, and an ascending of 1 could first fill address 0x400 followed by 0x440 and finishing with 0x7C0 [i.e. a ‘boundary’]) and
cease the prefetch requests in response to a memory address accessed by the prefetch requests satisfying the comparison. (paragraph 54, where there may be multiple hint operations to transfer information between two agents, which behavior may be defined by the function field in the hint message. For example, hint operations may include a cancel message (e.g., “Cancel1K”), which may indicate that speculatively issued hints of any kind may be cancelled, and/or a prefetch message (e.g., “Prefetch1K”) which may indicate that system performance may benefit if a targeted agent were to pre-fill the cache blocks indicated by the prefetch hint [The Examiner notes the limitation of to “cease prefetch requests” is analogous to cancelling or changing the amount to prefetch next as recited above]; and paragraph 55, where the ascending bit may indicate if the prefetch should process the block mask in ascending (1) or descending (0) order. For example, a prefetch with address of 0x400, mask of 0x8003, and an ascending of 1 could first fill address 0x400 followed by 0x440 and finishing with 0x7C0 [i.e. a ‘comparison’ of the memory address])
However, the Gouldey reference does not explicitly teach the boundary hint including a boundary type specifying a comparison between a memory address accessed by the prefetch requests and a boundary address associated with a boundary condition of the workload.
The Punyamurtula reference teaches it is conventional to have the boundary hint including a boundary type specifying a comparison between a memory address accessed by the prefetch requests and a boundary address associated with a boundary condition of the workload. (paragraph 35, where the page boundary comparator 307 may compare prefetch addresses generated by the stream predictor 303 to ensure that a prefetch address does not cross a page boundary. Accordingly, for each prefetch address generated, the page boundary comparator 307 may use the page size information in the entry corresponding to the current prefetch address to determine whether the current prefetch address is within the page boundary for the current stream. More particularly, the page size value in the page size entry may be used to set the limits within the page boundary comparator 307 for each stream independently)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Gouldey reference to have the boundary hint including a boundary type specifying a comparison between a memory address accessed by the prefetch requests and a boundary address associated with a boundary condition of the workload, as taught by the Punyamurtula reference.
The suggestion/motivation for doing so would have been to provide a prefetch mechanism that enables many types of prefetchers to prefetch addresses within that page size of the page within which the address falls, rather than having to stop at a page boundary of the minimum page size of the system; and thus be more efficient during prefetch operations. (Punyamurtula, paragraph 44)
Therefore it would have been obvious to combine the Gouldey and Punyamurtula references for the benefits shown above to obtain the invention as specified in the claim.
Claim 14 is the system implementation of claim 1 shown above; and rejected under a similar rationale. The Examiner notes the limitations of “a processor including a cache system with a cache level that includes prefetching circuitry” are shown in fig. 5 and corresponding text.
With respect to claim 15, the Gouldey and Punyamurtula references teaches the system of claim 14, wherein the boundary hint is generated from operation code associated with the workload. (Gouldey, paragraph 45, where the message may be encoded as “Prefetch1K” message between agents, which could have a 1 kilobyte aligned base address and a 16-bit mask of 64 byte cache blocks within that 1 kilobyte region)
With respect to claim 16, the Gouldey and Punyamurtula references teaches the system of claim 15, wherein the boundary hint is automatically determined by a compiler when compiling software associated with the workload. (Gouldey, paragraphs 20-21, where software structures are used to implement a system including components that may prefetch one or more cache blocks based on an address for a group of cache blocks and a bit field indicating the one or more cache blocks in the group; and there is a compiler)
Claim 20 is the method implementation of claim 1 shown above; and rejected under a similar rationale. The Examiner notes the Gouldey reference teaches a “hardware prefetcher associated with a cache level of a hierarchy of one or more cache levels” and “disabling” and “enabling” ceasing of prefetching as shown in paragraphs 54-56 and shown in fig. 5 and corresponding text.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-13 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Gouldey (US 20240184702) in view of Punyamurtula (US 20120131305), and further view of Lohman (US 20130232304).
With respect to claim 2, the combination of the Gouldey and Punyamurtula references does not explicitly teach the processor of claim 1, wherein the accesses of the workload include a stride access pattern.
The Lohman reference teaches it is conventional to have wherein the accesses of the workload include a stride access pattern. (paragraph 65, where typical hardware prefetchers search for a recognized pattern of read data and then automatically begin to speculatively preload future data based on the current read pattern. Typical examples of prefetch algorithms are an instruction or data cache fill that will cause the next cache line to be prefetched. A strided data prefetcher will look for a constant address stride between several data reads. It then uses that constant stride and multiplies by a predetermined count to create a prefetch address that it speculates that the CPU will read in the future. The automatic strided prefetch operation stops when the read address stride is broken)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Gouldey and Punyamurtula references to have wherein the accesses of the workload include a stride access pattern, as taught by the Lohman reference.
The suggestion/motivation for doing so would have been to provide further increases in data transfer efficiency, the memory data to be transferred may also be prefetched or preloaded into faster memory (e.g., faster cache memory) before the transfer operation is executed. (Lohman, paragraph 27)
Therefore it would have been obvious to combine the Gouldey, Punyamurtula, and Lohman references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 3, the combination of the Gouldey, Punyamurtula, and Lohman reference teaches the processor of claim 2, wherein the boundary hint includes the boundary type for the boundary condition of the stride access pattern, the boundary address for the boundary condition, and a target indicator identifying a program counter associated with the stride access pattern. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken)
With respect to claim 4, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 3, wherein the boundary type includes instructions to cease prefetch requests with a memory address less than the boundary address, greater than the boundary address, or equal to the boundary address. (Lohman, paragraph 69, where no subsequent preloads are performed, because the copy size is less than the minimum preload size (MinPLDSize) (Section II in FIG. 8). The CPU then copies the read data preloaded into cache memory to the destination memory address starting at 0x2000 (Section III in FIG. 8))
With respect to claim 5, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 3, wherein the processor further includes a register configured to determine the boundary address based on algorithmic metadata associated with the accesses included in one or more operation codes of the processor, the register including an architected register that is interacted with using instructions defined in an instruction set architecture (ISA), the boundary hint being indicated to the prefetching circuitry via an ISA-based interface. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken; and paragraph 12, where the processor may include registers to store a first read address associated with a read data stream and a second address that is associated with a second data stream. The processor may also include system registers including a minimum preload offset, an interleave stride, and an interleave count)
With respect to claim 6, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 3, wherein the boundary address is specified as an offset to the program counter, and the prefetching circuitry is configured to override a confidence threshold or counter threshold of the prefetching circuitry based on the boundary hint. (Lohman, paragraph 27, where a minimum prefetch or preload offset may be employed with the prefetch or preload operation so that data read from slower memory and written to faster memory is completed before the CPU needs access to the data during the transfer operation; and paragraph 65, where a strided data prefetcher will look for a constant address stride between several data reads. It then uses that constant stride and multiplies by a predetermined count to create a prefetch address that it speculates that the CPU will read in the future. The automatic strided prefetch operation stops when the read address stride is broken. The common theory of these existing prefetchers is to prefetch data based on a single stream of reads.)
With respect to claim 7, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 3, wherein the boundary condition is: set before the workload invokes a loop associated with the stride access pattern; and cleared after the workload completes the loop, a separate clear instruction clearing the boundary condition for each exit point of multiple exit points of the loop.. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken; and paragraph 67, where after receiving a software hint or recognizing a pattern, which can be hardware accelerated by embodiments of this invention, the preload data command generation logic 102 will do the equivalent function as block 618 where the logic adds the final PLD_OFFSET to addr1 and issues a data preload command to the memories [i.e. an ‘exit point’ for the loop])
With respect to claim 8, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 3, wherein the prefetch requests are ceased in response to a memory address accessed by a prefetch request satisfying the program counter. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken)
With respect to claim 9, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 8, wherein the boundary condition is applied to each access instruction of a loop associated with the stride access pattern. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken)
With respect to claim 10, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 2, wherein the boundary hint includes: the boundary type for the boundary condition of the stride access pattern; the boundary address as a variable boundary for the boundary condition based on a value of a loop count associated with the stride access pattern; and an exit indicator indicating a program counter of an exit from a loop associated with the stride access pattern. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken)
With respect to claim 11, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 10, wherein the boundary condition is set for each loop associated with the loop count. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken)
With respect to claim 12, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 11, wherein the boundary condition applies to each access instruction until the boundary condition is satisfied. a single boundary hint applying to multiple access instructions within a loop associated with the stride access pattern. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken)
With respect to claim 13, the combination of the Gouldey, Punyamurtula, and Lohman references teaches the processor of claim 10, wherein the prefetch requests are ceased in response to a loop count value associated with a memory address accessed by a prefetch request satisfying the boundary type and the variable boundary. (Lohman, paragraph 36, where data stream address alignment of a 1 (one) KB interleaved address block size at 1 (one) KB boundaries (starting at memory address 0--e.g., boundaries 0x000, 0x400, 0x800, etc.; and the stride of the interleaved memory banks 40 controls the optimal alignment distance between the read memory address and the write memory address; and paragraph 65, where the automatic strided prefetch operation stops when the read address stride is broken)
Claims 17-19 are the system implementation of claims 2-9 of the claims above, and rejected under a similar rationale.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 8-12 of the remarks) and amendments with respect to claims 1-20 have been considered, and some are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Punyamurtula reference to teach the newly amended claim language (see arguments pertaining to claims 1, 14, and 20 on pages 8-11) as shown in the rejections above. The Examiner further notes Applicant's arguments (see pages 11-12) pertaining to claims 2-13 and 15-19 fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. The Examiner notes the rejections above to teach the argued limitations.
3. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Gonion (US 20060004996), which teaches a macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.
4. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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