Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Response to Arguments
- Applicant’s amendment to the Drawings has overcome the previous Drawings objection.
- In response to the 112(b) rejection, the applicants have amended independent claims 1, 10, and 19 to further define the hierarchical levels as “ranging from a level 0 to a level n”.
While this amendment provides a specific range, it does not define what the hierarchical levels represent. However, they are no longer indefinite and the following interpretation will be applied for examination purposes.
When considering the claims in combination with the Specification/Drawings, the different hierarchical levels will be interpreted as different memory locations where architecture information can be stored, with priority or an order of saving being present.
- The amendment to dependent claim 5 has overcome the previous 112(b) rejection to the claim.
- Applicant's arguments filed 5/1/2026 with respect to the independent claims have been fully considered but they are not persuasive. Page 8 of the Remarks comprises the following arguments regarding the 102 rejection (Gendler; U.S. PGPUB No. 2016/0378660) (Emphasis added by Examiner):
“Applicant respectfully traverses this rejection. Gendler has a linear (non-hierarchical) transfer from one specific core internal memory to one specific external memory. Gendler does not disclose (expressly or inherently) a system capable of managing state across different hierarchical levels independently of software execution. In contrast, the Applicant's claims recite an architecture that utilizes circuit elements to autonomously manage state information across a multi-tier hierarchy (up to level n). For example, as stated in claim 1: "A method, comprising: triggering, via one or more circuit elements, saving of architecture state information of at least one processing element (PE) to multiple memories prior to the at least one PE transitioning from a first state to a second state, wherein the architecture state information comprises information associated with different hierarchical levels ranging from a level 0 to a level n." This claim is supported by paragraphs [0075-0078].”
In response to applicant's argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (“independently of software execution” and “autonomously”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The claims only require that the one or more circuit elements trigger the saving of architecture state information. The claims do not preclude software execution from occurring or specifically require that the triggering is “autonomously”.
The Examiner maintains the rejection presented in the NF rejection with respect to the independent claims. With respect to the above “non-hierarchical” comment made in the Remarks, the Examiner notes that the interpretation of the term “hierarchical levels” was previously presented in the NF rejection as merely two different locations to store information.
The Examiner notes that a hierarchy can simply represent an order or priority system. Therefore, if information is stored in a first memory first and then copied or transferred to a second memory in response to a trigger, then a hierarchy exists between the two memory locations.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
- This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure (e.g. “circuit elements”), materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “means for triggering” via one or more circuit elements, in claim 19.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
With respect to claim 14, it is unclear how claim 14 can require “a single sequencing element capable of saving architecture state information at different hierarchical levels”, when claim 13 (which claim 14 is dependent from) already requires there to be a sequencing element per hierarchical level. Therefore, embodiments with more than one level, according to claims 13 and 14, would require both multiple sequencing elements and only a single sequencing element.
- This issue is similar to the previous issue with respect to claim 5 which was corrected by amendment in the claims filed 5/1/2026. For examination purposes, the Examiner will interpret claim 14 as though a similar amendment has been made, however, proper amendment to claim 14 to change the dependency to claim 12 is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-13, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gendler et al. U.S. PGPUB No. 2016/0378660.
Per Claim 1, Gendler discloses a method, comprising:
triggering, via one or more circuit elements (Paragraph 20; power management controller 128; Also, Paragraph 52, power management agent (PMA)),
saving of architecture state information of at least one processing element (PE) (cores 102/104) to multiple memories (Paragraph 27; Save state SRAM 116 and system memory 110)
prior to the at least one PE transitioning from a first state to a second state wherein the architecture state information comprises information associated with different hierarchical levels (Paragraphs 26-41 detail the “Saving and Restoring Processor Core State” process. Specifically, Paragraph 26 states that SRAM 116 is used to save the architectural state of the core 102 when entering the C6 power state. Transitioning between power states triggers saving the contents of SRAM 116 to a memory external to the processor core, such as DRAM 110. Paragraphs 33 and 34 further define that the C6 SRAM contents (which includes the architectural state) are stored at a specific DRAM base address, and this specific DRAM base address is stored in two locations, one inside the processor core itself and one outside the power domain of the processor core. The DRAM base address used to store the architecture state reads on the claimed “architecture state information”.);
and triggering, via the one or more circuit elements, restoration of the architecture state information from the multiple memories to the at least one PE prior to the at least one PE transitioning from the second state to the first state (Paragraph 30, “the processor core needs to restart and restore from the C6 SRAM”. Paragraphs 50-54).
Per Claim 2, Gendler discloses the method of claim 1, wherein: the at least one PE transitions from the first state to the second state as part of a power down sequence (Paragraph 26; The processor core transitions from power saving mode C6 state to a deeper sleep state, C10.); and the at least one PE transitions from the second state to the first state as part of a power up sequence (Paragraph 30; Waking out of the C10 state.).
Per Claim 3, Gendler discloses the method of claim 1, wherein the one or more circuit elements comprise, at least one sequencing element to trigger the saving and restoration (Paragraph 20; power management controller 128); and at least one routing interface to transfer architecture state information between state registers of the at least one PE and the at least one memory (Paragraph 34; “the C6 DRAM base address is stored in a register in the processor core”. Paragraph 13, Fig. 1; Memory controller 106 is considered a routing interface as it controls the transfer of information from core 102 to system memory 110.).
Per Claim 4, Gendler discloses the method of claim 3, wherein the at least one sequencing element comprises a sequencing element per hierarchical level at which architecture state information is saved (Paragraph 19; ACPI 126 represents a sequencing element at the system memory level and Paragraph 20 teaches a power management microcontroller 128 responsible for the core 102 level.).
Per Claim 6, Gendler discloses the method of claim 4, wherein the saving comprises: saving architecture state information associated with a first hierarchical level at a memory associated with a second hierarchical level (Paragraphs 26-41 detail the “Saving and Restoring Processor Core State” process. Specifically, Paragraph 26 states that SRAM 116 is used to save the architectural state of the core 102 when entering the C6 power state. Transitioning between power states triggers saving the contents of SRAM 116 to a memory external to the processor core, such as DRAM 110. Paragraphs 33 and 34 further define that the C6 SRAM contents (which includes the architectural state) are stored at a specific DRAM base address, and this specific DRAM base address is stored in two locations, one inside the processor core itself and one outside the power domain of the processor core. The DRAM base address used to store the architecture state reads on the claimed “architecture state information”.).
Per Claim 7, Gendler discloses the method of claim 3, wherein: the at least one PE comprises multiple Pes (Cores 102 and 104); and the at least one sequencing element comprises: a sequencing element per each of the multiple PEs, or a single sequence element that saves architecture state information for the multiple PEs (Paragraph 20; Power management microcontroller 128 can perform power state transitions for multiple different cores 102/104 of processor 100.).
Per Claim 8, Gendler discloses the method of claim 3, wherein the at least one sequencing element is configurable to trigger or skip the saving and restoration of the architecture state information (Paragraphs 20-25; Power Mgmt Microcontroller 128 controls the entry/exit to/from different power states with respect to the cores 102/104, and therefore the triggering or skipping of the saving/restoration of the architecture state information based on the power states the cores of the processor are transitioning to/from.).
Per Claim 9, Gendler discloses the method of claim 3, wherein the routing interface allows access to the architecture state information (Paragraph 34; “the C6 DRAM base address is stored in a register in the processor core”. Paragraph 13, Fig. 1; Memory controller 106 is considered a routing interface as it controls the transfer of information from core 102 to system memory 110.).
Per Claims 10-13 and 15-18, please refer to the above rejection of claims 1-4 and 6-9 as the limitations are substantially similar and the mapping of the reference is equally applicable.
Per Claims 19 and 20, please refer to the above rejection of claims 1 and 2 as the limitations are substantially similar and the mapping of the reference is equally applicable.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112, 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Note, the combination of claims required for allowance is claims 10, 12, and 14 (similar to above with claims 1, 3, and 5)
- The following is a statement of reasons for the indication of allowable subject matter:
No combination of Gendler and the prior art teaches or suggests the at least one sequencing element comprising a single sequencing element capable of saving architecture state information at different hierarchical levels
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889. The examiner can normally be reached on M-F: 8-4:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
Prosecution Insights