DETAILED ACTION
Response to Amendment
The Amendment filed December 15, 2025 has been entered. Claims 1-8 and 18-20 remain pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 2022/0365879) and Brittain et al. (US 2016/0357688).
Regarding claim 1, Kumar et al. disclose:
An apparatus comprising:
memory control circuitry (Figure 1 Memory Controller 110) configured to control access to at least one array of memory storage cells (Figure 1 Memory Modules 104, Cache 220, and Cache(s) 212; note that data retrieval requests that cannot be satisfied by either of the caches are sent to the memory module where the data is accessed to fulfill the requests)…
utilization status determining circuitry (Figure 2 Throttler 216) configured to determine a utilization status associated with accessing the array of memory storage cells (Figure 7 step 704 Determine a congestion level of the first processing cluster based on an extent to which the plurality of data retrieval requests sent from the one or more processors in the first processing cluster to the cache are not satisfied 704); and
feedback signaling circuitry (Figure 2 Throttler 216) configured to signal to a source (Figure 2 Prefetcher 208; [0037] the prefetch requests are generated and processed by one or more prefetchers 208) of the received memory access requests feedback indicative of the determined utilization status ([0038] throttler 216 determines a congestion level of processing cluster 202 based on an extent to which the plurality of data retrieval requests sent from one or more processors 204 in processing cluster 202 to cluster cache 212 are not satisfied by cluster cache 212. In accordance with a determination that the congestion level of processing cluster 202 satisfies first congestion criteria that require that the congestion level of processing cluster 202 is above a first cluster congestion threshold, throttler 216 causes a first respective processor (e.g., processor 204-1) of one or more processors 204 to limit prefetch requests to cluster cache 212 to prefetch requests of at least a first threshold quality (i.e., to limit the prefetch requests to high quality prefetches). Specifically, in an example, throttler 216 transmits a signal or other information to processors 204 (e.g., prefetcher 208-1 in processors 204-1) to enable prefetch throttling, so that only prefetch requests of at least the first threshold quality are sent to cluster cache 212);
in which the utilization status is indicative of a utilization of a group of memory storage cells in the at least one array of memory storage cells ([0041] on a system level, throttler 216 monitors a system congestion level of a memory system coupled to processing cluster 202 based on a system busy level signal received from the output of cluster cache 212. The system busy level signal includes information of outstanding in-flight requests that are received and not satisfied by cache 220 or memory 104).
Kumar et al. do not appear to explicitly teach “memory control circuitry…to schedule received memory access requests targeting locations in the at least one array of memory storage cells.” However, Brittain et al. disclose:
memory control circuitry…to schedule received memory access requests targeting locations in the at least one array of memory storage cells ([0002] memory controller can then seek to schedule the various access requests in the pending access requests storage so as to seek to optimise performance of the memory device);
Kumar et al. and Brittain et al. are analogous art because Kumar et al. teach prefetch throttling and Brittain et al. teach processing scheduling accesses to memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kumar et al. and Brittain et al. before him/her, to modify the teachings of Kumar et al. with the Brittain et al. teachings of memory access scheduling because doing so would optimize performance of the memory device.
Regarding claim 2, Kumar et al. further disclose:
The apparatus of claim 1, in which the at least one array of memory storage cells comprises DRAM storage ([0020] memory modules 104 (e.g., memory 104 in FIGS. 2-4, second memory in FIG. 8) include high-speed random access memory, such as DRAM).
Regarding claim 3, Kumar et al. further disclose:
The apparatus of claim 1, in which the feedback is indicative of whether the memory control circuitry has capacity to process opportunistic memory access requests ([0034] controls prefetches of instructions and data to core caches 218 and/or cluster cache 212 based on the system and/or cluster congestion levels; [0038] throttler 216 determines a congestion level of processing cluster 202 based on an extent to which the plurality of data retrieval requests sent from one or more processors 204 in processing cluster 202 to cluster cache 212 are not satisfied by cluster cache 212; [0041] throttler 216 obtains a current congestion level of cache 220 based on a number of outstanding in-flight requests received by cache 220), the opportunistic memory access requests being memory access requests not currently demanded by a memory access request initiator but predicted to be required in future (prefetch requests are requests for data predicted to be used in the future).
Regarding claim 4, Brittain et al. further disclose:
The apparatus of claim 1, in which the group of memory storage cells in the at least one array of memory storage cells corresponds to one of: a channel; a rank; a group of banks; a bank; and a row of cells in the at least one array of memory storage cells ([0052] the memory device is a DRAM memory device, the memory devices is organised into a hierarchy of ranks, banks, rows and columns, representing a variety of different sub-structures within the memory device).
Regarding claim 8, Kumar et al. further disclose:
The apparatus of claim 1, in which the feedback signaling circuitry is configured to signal the feedback using an indication separate from a read/write response ([0038] throttler 216 transmits a signal or other information to processors 204 (e.g., prefetcher 208-1 in processors 204-1) to enable prefetch throttling, so that only prefetch requests of at least the first threshold quality are sent to cluster cache 212).
Regarding claim 18, the combination of Kumar et al. and Brittain et al. disclose the apparatus of claim 1, supra. Kumar et al. further discloses:
A non-transitory computer-readable medium storing computer-readable code for fabrication of the apparatus of claim 1 ([0130] Clause 31. A non-transitory computer-readable medium, having instructions stored thereon for performing a method of any of clauses 16-30).
Regarding claim 19, Kumar et al. and Brittain et al. disclose “A system comprising: the apparatus of claim 1,” supra. Kumar et al. further disclose:
…implemented in at least one packaged chip ([0019] System module 100 in this electronic device includes at least a system on a chip (SoC) 102; [0031] SoC 102 is implemented on an integrated circuit that integrates one or more microprocessors or central processing units, memory, input/output ports and secondary storage on a single substrate);
at least one system component ([0031] SoC 102 is configured to receive one or more internal supply voltages provided by PMIC 118); and
a board ([0031] a main logic board),
wherein the at least one packaged chip and the at least one system component are assembled on the board ([0031] both the SoC 102 and PMIC 118 are mounted on a main logic board, e.g., on two distinct areas of the main logic board, and electrically coupled to each other via conductive wires formed in the main logic board).
Regarding claim 20, Kumar et al. further disclose:
A chip-containing product comprising the system of claim 19, wherein the system is assembled on a further board with at least one other product component ([0031] both the SoC 102 and PMIC 118 are mounted on a main logic board, e.g., on two distinct areas of the main logic board, and electrically coupled to each other via conductive wires formed in the main logic board).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. and Brittain et al. as applied to claim 1 above, and further in view of Lepak et al. (US 2012/0144124).
Regarding claim 6, Kumar et al. and Brittain et al. do not appear to explicitly teach while Lepak et al. disclose:
The apparatus of claim 1, in which the memory control circuitry is configured to:
determine that a received memory access request is an opportunistic memory access request based on an encoding associated with the received memory access request indicating that the received memory access request may be ignored ([0040] a processor 110 may label 504 its memory access requests 502 as either "demand" or "prefetch". Further, the label 504 may include a confidence level associated with the request 502; Table 1 2-bit indicator of memory access request type), and determine, based on the utilization status, whether the opportunistic memory access request is to be ignored ([0042] As memory utilization increases even more, the MS-PFU 150 may update its data bank 252 with only demand requests and thereby ignore all prefetch requests from the processors 110 in order to reduce its own utilization of memory access resources and reduce the number of speculative prefetch requests it issues).
Kumar et al., Brittain et al., and Lepak et al. are analogous art because Kumar et al. teach prefetch throttling; Brittain et al. teach processing scheduling accesses to memory; and Lepak et al. disclose prefetching and memory scheduling.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kumar et al., Brittain et al., and Lepak et al. before him/her, to modify the teachings of Kumar et al. and Brittain et al. with the Lepak et al. teachings of ignoring determined opportunistic memory access requests because doing so would reduce the memory controllers utilization of memory access resources and reduce the number of speculative prefetch requests it issues.
Allowable Subject Matter
Claims 5 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as discussed in the Non-Final Office Action mailed September 15, 2025.
Response to Arguments
Applicant's arguments filed December 15, 2025 have been fully considered but they are not persuasive.
Applicant’s remarks have been fully considered. However, the rejection of claim 1 under 35 U.S.C. 103 as unpatentable over Kumar et al. and Brittain et al. is determined to be proper and is, therefore, maintained.
Regarding the substance of the examiner’s obviousness rejection as argued on pages 4-6 of the remarks, the requirements for obviousness are discussed in MPEP § 2142.
First, applicant asserts that the mapping of Kumar et al. to the claims in inconsistent (Remarks page 4). The mapping has been clarified supra to address applicant’s concerns.
Next, applicant argues that the combination of Kumar et al. and Brittain et al. do not disclose “feedback signaling circuitry configured to signal to a source of the received memory access requests feedback indicative of the determined utilization status” (Remarks page 5). The features are disclosed by Kumar et al. as discussed above. With respect to the recited memory control circuitry taught by Brittain et al., the claim limitation requires “memory control circuitry configured…to schedule received memory access requests targeting locations in the at least one array of memory storage cells.” This limitation is taught by Brittain et al. as discussed above. The claim limitations do not recite any particular order in which the received memory access requests occur in relation to the feedback signaling circuitry. Therefore, the rejection of the limitation “feedback signaling circuitry configured to signal to a source of the received memory access requests feedback indicative of the determined utilization status” is maintained, as discussed above.
Finally, applicant asserts that the mapping for the claim feature “in which the utilization status is indicative of a utilization of a group of memory storage cells in the at least one array of memory storage cells” is inconsistent with the mapping of “feedback signaling circuitry configured to signal to a source of the received memory access requests feedback indicative of the determined utilization status” (Remarks pages 5-6). The examiner disagrees because the claim language “indicative of a utilization of a group of memory storage cells” and “indicative of the determined status” provide no guidance of what specifically is being indicated. Because the claim language is so broad, the mapping of Kumar et al. discloses the limitations as discussed above.
The rejection of claim 1 as obvious over Kumar et al. and Brittain et al. is therefore maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRACY A WARREN/Primary Examiner, Art Unit 2137