This action is in response to the amendments filed on 01/29/2024, in which claims 1-20 are presented for the examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 13/31/2025, 01/22/2026, 01/29/2026, 0423/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 01/29/2026 have been fully considered but they are not persuasive.
Applicant argues that Stillwell fails to teach or suggest hardware-based architecture state save and restore mechanisms integrated with processing element (PE) power-state transitions and further fails to disclose hardware-enforced access blocking and re-routing of architecture state information while a PE is in a powered down state.
With respect to independent claims 1, 9 and 17, the examiner disagrees. A previously noted, Stillwell discloses determining whether a save architectural state trigger event has occurred, wherein examples of such trigger events including entering and exiting a power state (Stillwell, [0058]). Thus, Stillwell expressly associates with architectural-state save operations with power-state transitions. Stillwell further discloses restoring architectural state information (Stillwell, [0062]) to enable continued execution following the triggering event. Accordingly, Stillwell teaches triggering save and restore operations before and after transitions between operational states, including power states.
Regarding claim 7, applicant argues that Stillwell fails to disclose “the sequencing element is configured to signal the routing interface to block access to the architecture state information while the Pes are in the second state”. The examiner notes that architectural state information saved to memory for later restoration would necessarily be managed through control logic that governs access to the saved state during the period in which the processing element is unavailable.
Accordingly, the rejections of claims 1, 7, 9 and 17 is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-14, 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stillwell, JR. et al. (US 2009/0172369, referred herein after Stillwell).
As per claim 1, 9, 17, Stillwell discloses a method, comprising:
triggering, via a first circuit element, saving of architecture state information of multiple processing elements (PEs) to at least one memory prior to the multiple PEs transitioning from a first state to a second state (Fig. 3, step 315, [0058], “t is determined if a save architectural state trigger event has occurred…..Examples of a save architectural state trigger event includes a core failure, …., entering/exiting a power state”);
and
triggering, via the first circuit element, restoration of the architecture state information from the at least one memory to the multiple PEs prior to the multiple PEs transitioning from the second state to the first state (Fig. 3, step 330, [0062], “the architectural sate is restored to a second processing element, such as a core, thread, or other context. “).
As per claim 2, 10, 18, Stillwell discloses the method of claim 1, wherein: the PEs transition from the first state to the second state as part of a power down sequence ([0058] power exit- power down as claimed); and
the PEs transition from the second state to the first state as part of a power up sequence ([0058], power enter- power up as claimed).
As per claim 3, 11, 19, Stillwell discloses the method of claim 1, wherein: the first circuit element comprises a sequencing element to trigger the saving and restoration (Fig. 3, step 315, [0055], [0058]).
As per claim 4, 12, 20, Stillwell discloses the method of claim 3, wherein the sequencing element is configurable to trigger or skip the saving and restoration of the architecture state information (Fig. 3 step 315, yes and no arrow, [0055]-[0058]).
As per claim 5, 13, Stillwell discloses the method of claim 3, wherein the sequencing element signals at least one routing interface to transfer architecture state information between state registers of the multiple PEs and the at least one memory ([0013], [0014], [0020], [0032]-[0036]).
As per claim 6, 14, Stillwell discloses the method of claim 5, wherein the routing interface allows access to the architecture state information (Fig. 2, [0031], [0032]).
As per claim 8, 16, Stillwell discloses the method of claim 5, wherein: the at least one memory comprises at least one architecture state random access memory (RAM); and the routing interface is configured to, while the PE are in the second state, re-route requests to access the state registers to the architecture state RAM ([0040], [0041], “the controlling software determines that the workload on processor 205 should be moved to another cooler section of the processor, which includes processor 210. Instead of scrapping execution and restarting on a new core, the current architectural state of core 205 is saved and restored to core 210”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Stillwell in view Govindan et al. (US 2016/0321183, referred herein after Govindan).
As per claim 7, 15, Stillwell does not specifically disclose the method of claim 6, wherein the sequencing element is configured to signal the routing interface to block access to the architecture state information while the PEs are in the second state;
However, Govindan discloses the sequencing element is configured to signal the routing interface to block access to the architecture state information while the PEs are in the second state ([0038], power gating processor is interpreted as blocking the access as claimed);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Govindan’s power management method in computing systems into method of saving and restoring architectural state for processor cores because one of the ordinary skill in the art would have been motivated to secure a system during a low-power, sleep, or blocked state, or when transitioning between different security levels.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAMINI B PATEL whose telephone number is (571)270-3902. The examiner can normally be reached on M-F 8-4:30.
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/KAMINI B PATEL/Primary Examiner, Art Unit 2114
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