DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9-10, 12-17, 19-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hou et al. U.S. Patent Application Publication US2013/0031554A1.
As per claim 1, Hou teaches an apparatus comprising: processing circuitry configured to execute instructions; and accelerator control interface circuitry configured to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task (¶ 0005); in which: the accelerator control interface circuitry is responsive to an accelerator command launch instruction executed by the processing circuitry, to output a command request to a given hardware accelerator associated with command data for configuring the given hardware accelerator to perform the delegated task (¶ 0006); when the accelerator command launch instruction is an accelerator command-with-response launch instruction, the command request comprises a command-with-response request indicating that the given hardware accelerator is to acknowledge the command data associated with the command-with-response request (¶ 0009); and when the accelerator command launch instruction is an accelerator command-without-response launch instruction, the command request comprises a command-without-response request indicating that the given hardware accelerator does not need to acknowledge the command data associated with the command-without-response request (¶ 0010, wherein the response is not needed until an interrupt is sent).
As per claim 9, Hou teaches the apparatus of claim 1, wherein the accelerator command launch instruction comprises a store instruction specifying an address mapped to a launch control storage location of the accelerator control interface circuitry (¶ 0032).
As per claim 10, Hou teaches the apparatus of claim 9, wherein the command data associated with the command request comprises command data obtained, in response to the store instruction, from at least one data register of the accelerator control interface circuitry, the at least one data register being writable by software executing on the processing circuitry (¶ 0059).
As per claim 12, Hou teaches the apparatus of claim 1, wherein, in response to the given hardware accelerator acknowledging the command data associated with the command-with-response request, the accelerator control interface circuitry is configured to set a corresponding response state in a response storage location of the accelerator control interface circuitry, the response storage location being readable by software executing on the processing circuitry (¶ 0029-0030, wherein the state of the time required is stored).
As per claim 13, Hou teaches the apparatus of claim 1, wherein, when the command-with-response request is associated with one or more preceding command-without-response requests, the accelerator control interface circuitry is configured to interpret an acknowledgement of the command data associated with the command-with-response request as an acknowledgement of the command data associated with the one or more preceding command-without-response requests (¶ 0029).
As per claim 14, Hou teaches the apparatus of claim 1, wherein the accelerator control interface circuitry is configured to output the command-with-response request comprising an indication of whether the command-with-response request is associated with one or more preceding command-without-response requests (¶ 0029).
As per claim 15, Hou teaches the apparatus of claim 1, wherein the accelerator control interface circuitry is configured to output the command-without-response request comprising an indication of whether the command-without-response request is a first request of a stream of one or more command requests associated with configuring the given hardware accelerator to perform the delegated task (¶ 0029).
As per claim 16, Hou teaches a hardware accelerator comprising: accelerator processing circuitry configurable, based on instructions executed by a processor, to perform a delegated task on behalf of the processor; and control interface circuitry configured to exchange control signals with the processor; in which: the control interface circuitry is responsive to a command request associated with command data, to configure the hardware accelerator to perform the delegated task based on the command data; when the command request is a command-with-response request, the control interface circuitry is configured to output a signal to the processor indicating an acknowledgement of the command data associated with the command-with-response request; and when the command request is a command-without-response request, the control interface circuitry is configured to suppress outputting the signal to the processor indicating the acknowledgement of the command data associated with the command-without-response request (¶ 0005, 0006, 0009, 0010, see claim 1).
As per claim 17, Hou teaches the hardware accelerator of claim 16, further comprising a task buffer, wherein the control interface circuitry is configured to store the command data in the task buffer (¶ 0004, cache).
As per claim 19, Hou teaches the hardware accelerator of claim 16, wherein when the command-with-response request is associated with one or more preceding command-without-response requests, the control interface circuitry is configured to output the acknowledgement of the command data associated with the command-with-response request which also serves as an acknowledgement of the command data associated with the one or more preceding command-without-response requests ((¶ 0029).
As per claim 20, Hou teaches a system comprising the apparatus of claim 1 and a hardware accelerator, the hardware accelerator comprising: accelerator processing circuitry configurable, based on instructions executed by a processor, to perform a delegated task on behalf of the processor; and control interface circuitry configured to exchange control signals with the processor; in which: the control interface circuitry is responsive to a command request associated with command data, to configure the hardware accelerator to perform the delegated task based on the command data; when the command request is a command-with-response request, the control interface circuitry is configured to output a signal to the processor indicating an acknowledgement of the command data associated with the command-with-response request; and when the command request is a command-without-response request, the control interface circuitry is configured to suppress outputting the signal to the processor indicating the acknowledgement of the command data associated with the command-without-response request (¶ 0005, 0006, 0009, 0010, see claim 1).
As per claim 21, Hou teaches a non-transitory storage medium storing computer-readable code for fabrication of an apparatus according to claim 1 (¶ 0005, 0006, 0009, 0010, see claim 1).
As per claim 22, Hou teaches a system comprising: the apparatus of claim 1, implemented in at least one packaged chip; at least one system component; and a board; wherein the at least one packaged chip and the at least one system component are assembled on the board (¶ 0005, 0006, 0009, 0010, see claim 1; ¶ 0028, wherein the system is comprised on a CPU chip which would be mounted on a motherboard of the computer system which comprises further computing components).
As per claim 23, Hou teaches a chip-containing product comprising the system of claim 22, wherein the system is assembled on a further board with at least one other product component (¶ 0005, 0006, 0009, 0010, see claim 1; ¶ 0028, wherein the system is comprised on a CPU chip which would be mounted on a motherboard of the computer system which comprises further computing components).
As per claim 24, Hou teaches a method comprising: executing instructions using processing circuitry; exchanging control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task; and in response to an accelerator command launch instruction executed by the processing circuitry, the accelerator control interface circuitry outputting a command request to a given hardware accelerator associated with command data for configuring the given hardware accelerator to perform the delegated task; wherein: when the accelerator command launch instruction is an accelerator command-with-response launch instruction, the command request comprises a command-with-response request indicating that the given hardware accelerator is to acknowledge the command data associated with the command-with-response request; and when the accelerator command launch instruction is an accelerator command-without-response launch instruction, the command request comprises a command-without-response request indicating that the given hardware accelerator does not need to acknowledge the command data associated with the command-without-response request (¶ 0005, 0006, 0009, 0010, see claim 1).
As per claim 25, Hou teaches a non-transitory storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising: processing program logic to execute instructions; accelerator control interface program logic to control at least one simulated hardware accelerator configurable, based on instructions executed by the processing program logic, to perform a delegated task; in which: the accelerator control interface program logic is responsive to an accelerator command launch instruction executed by the processing program logic, to output a command request to a given simulated hardware accelerator associated with command data for configuring the given simulated hardware accelerator to perform the delegated task; when the accelerator command launch instruction is an accelerator command-with-response launch instruction, the command request comprises a command-with-response request indicating that the given simulated hardware accelerator is to acknowledge the command data associated with the command-with-response request; and when the accelerator command launch instruction is an accelerator command-without-response launch instruction, the command request comprises a command-without-response request indicating that the given simulated hardware accelerator does not need to acknowledge the command data associated with the command-without-response request (¶ 0005, 0006, 0009, 0010, see claim 1; 0064).
Allowable Subject Matter
Claims 2-8, 11, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
6. Applicant's arguments filed 1/12/26 have been fully considered but they are not persuasive.
With respect to claim 1, the applicant has argued that Hou does not teach a request to indicate whether the accelerator is to acknowledge the command data. The examiner respectfully disagrees. The examiner interprets the claim language of “to acknowledge the command data associated with the… request” as acknowledging the request by sending the data requested. That is, with the command-with-response request, the accelerator returns the result from the cache that was requested (¶ 0009). With the command-without-response request, Hou teaches the request is sent, but a return result is not expected until a later time (¶ 0010). It appears the applicant and the examiner interpret wherein the accelerator does not need to acknowledge the command data associated with request, differently. The applicant has argued that the accelerator does return a result in every case, that may be true with the interpretation that the “not need acknowledgment” comprises no response at any time. The examiner interprets it as no result is sent immediately in response to the request. In the case of Hou, no response/acknowledgement is needed immediately, but data can be obtained at a later time. The applicant appears to disagree with this interpretation as he says the accelerator produces a result regardless of the request, but the data is not obtained until later, in the second condition. The examiner interprets Hou as sending the data in response to the request, as in condition A, but not sending the data, as in condition B, and the data is obtained later. The examiner disagrees with the applicant’s argument of the accelerator produces a result regardless of the type of request as this condition is not explicit in the claim, only the need of an acknowledgement of the request, not whether the accelerator produces a result or not.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER S MCCARTHY whose telephone number is (571)272-3651. The examiner can normally be reached Monday-Friday 8:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER S MCCARTHY/Primary Examiner, Art Unit 2113