DETAILED ACTION
This Office Action is response to the amendment filed on March 3, 2026.
Claims 1, 4 and 11 are amended and claim 20 is canceled. Claims 1-19 are currently pending and have been examined.
In the response to this Office action, the examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the examiner in prosecuting this application.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/22/2026 and 2/9/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-16 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims of co-pending Application No. 18/757,998. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claims 1-3, 5-6 and 11-16 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 7-8, 10 and 14-16 of co-pending Application No. 18/758,136. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claims 1-16 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims of co-pending Application No. 18/758,123 in view of Flynn et al. (USPN: 2004/0153762), hereinafter, “Flynn”. For example, claims 1 and 10 of the co-pending ‘123 application teaches limitations of claims 1 and 11 of the instant application except the “re-routing” limitation. Flynn, however, teaches the “re-routing” limitation as claimed in [0038]. Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to implement the Flynn’s teaching in the claimed invention of the co-pending Application No. 18/758,123, so when the power down mode is exited, the system should return to its previous state unaltered such that processing operations can continue smoothly and efficiently. It would be highly disadvantageous if information/state was lost upon so as to require a full system reboot and initialization upon restart. (see [0004] of Flynn).
These are provisional nonstatutory double patenting rejections because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Stillwell et al. (USPN: 7,996,663), hereinafter, “Stillwell” in view of Flynn.
As per claim 1, Stillwell teaches a method, comprising:
triggering, via at least a first circuit element, saving of architecture state information of at least one processing element (PE) (205 in Fig. 2) to at least one memory (230 in Fig. 2) prior to the at least one PE transitioning from a first state to a second state (i.e. the architecture state info of core 205 gets stored into the memory 230 in response to any of the list of triggering events including “exiting power” listed in Col. 6, lines 49-61);
re-routing, via at least a second circuit element, requests to access the architecture state registers to an architecture state random access memory (RAM), while the at least one PE is in the second state (i.e. while the core 205 is rebooting or in “exiting power” state, any request to access any state info of core 205 is routed to memory 230 or restore storage element 212; see Fig. 2); and
triggering, via the first circuit element, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state (i.e. in response to any of the list of triggering events (listed in Col. 6, lines 49-61) the current architecture state info of core 205 gets restored to core 210; see Col. 7, lines 17-19; Col. 8, lines 51-53, 57-62).
For sake of argument, if it is considered that the re-routing step is not taught by Stillwell, Flynn teaches it in [0038]. Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to implement the Flynn’s teaching in the method taught by Stillwell so when the power down mode is exited, the system should return to its previous state unaltered such that processing operations can continue smoothly and efficiently. It would be highly disadvantageous if information/state was lost upon so as to require a full system reboot and initialization upon restart. (see [0004] of Flynn).
As per claim 2, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that at least one PE transitions from the first state to the second state as part of a power down sequence (i.e. the list of triggering events listed in Col. 6, lines 49-61 includes “existing power”); and the at least one PE transitions from the second state to the first state as part of a power up sequence (i.e. the list of triggering events listed in Col. 6, lines 49-61 includes “entering power”).
As per claim 3, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that the first circuit element comprises at least one sequencing element (i.e. 231 within memory 230 in Fig. 2) to trigger the saving and restoration (i.e. the saving and restoring the architecture state information is performed in the sequence as shown in the flowchart of Fig. 3; See Col. 9, lines 47+. Note that the sequence shown in Fig. 3 is just one example but saving/restoring can be performed in serial, parallel or any other order) and the second circuit element comprises at least one routing interface to transfer architecture state information between state registers of the at least one PE and the at least one memory (i.e. saving the portions of the architecture state information from the (registers) of the first core 205 to the memory 230 [blocks 310-325 in the flowchart of Fig. 3] and restoring it from the memory 230 to the second core 210 [block 330 in the flowchart of Fig. 3]).
As per claim 4, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that the at least one PE comprises multiple PEs (e.g. 205 and 210 in Fig. 2; see Col. 5, lines 48-53); and the at least one sequencing element comprises: a sequencing element per each of the multiple PEs (i.e. 231 and 232 for corresponding PEs 205 and 210 in Fig. 2), or a single sequence element that saves architecture state information for the multiple PEs.
As per claim 5, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that the routing interface allows access to the architecture state information (i.e. accessible when saved the portions of the architecture state information from the (registers) of the first core 205 to the memory 230 [blocks 310-325 in the flowchart of Fig. 3]).
As per claim 6, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that the at least one sequencing element is configured to signal the at least one routing interface to block access to the architecture state information while the at least one PE is in the second state (i.e. when the 205 is powered down, the architecture state info of it is not accessible directly from it until it boots back up (even though it is available from 231; see Fig. 2).
As per claim 7, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that the architecture state information comprises information associated with different hierarchical levels (i.e. architecture state information associated with different cores/PEs; See Figs. 1-2. Note: the claimed ‘different hierarchical levels’ are interpreted as for different cores/processing elements).
As per claim 8, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that the at least one sequencing element comprises a sequencing element per hierarchical level at which architecture state information is saved (i.e. 231 and 232 for corresponding PEs 205 and 210 in Fig. 2).
As per claim 9, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that the at least one sequencing element comprises a single sequencing element capable of saving architecture state information at different hierarchical levels (i.e. the memory ranges corresponding to 231 and 232 within 230 could be contiguous with each other; see Col. 6, lines 10-15 and Fig. 2).
As per claim 10, the combination of Stillwell and Flynn teaches the claimed invention as described above and furthermore, Stillwell teaches that the saving comprises: saving architecture state information associated with a first hierarchical level at a memory associated with a second hierarchical level (i.e. the architecture state information associated with 205 is saved at 231 within the same memory 230 where the architecture state information associated with 210 is also saved; see Fig. 2).
Claims 11-19 are apparatus claims and substantially like claims 1-9, except are drawn to apparatus claims. Claims 11-19 are also rejected for the same reasons as for claims 1-9.
Response to Amendment
In response to amendment to claims 1 and 11, the 112(b) rejection is withdrawn.
With respect to 35 USC 102/103 rejections, Applicant asserted:
Stillwell teaches routing requests to the memory 230 that stores the architecture state info of core 205. Such requests cannot be considered to be "re-routed" since they are being provided to the very location (that is, memory 230) where the architecture state info is stored instead of to a different memory, specifically "an architecture state random access memory (RAM)" like recited in claims 1 and 11 as amended.
Stillwell discloses that "while the core 205 is rebooting or in "exiting power" state, any request to access any state info of core 205 is routed to storage element 212. However, Stillwell discloses that the storage element 212 "may be referred to as being included within architectural state registers and, for at least this reason, Applicant submits that storage element 212 cannot be considered an architecture state random access memory (RAM) to which requests for the architecture state registers are re-routed to as recited in claims 1 and 11.
Applicant submits that re-routing interrupt requests cannot be considered the same as re-routing requests "to access architecture state registers" as recited in claims 1 and 11, because an "interrupt request for a processor core" as taught in Song cannot be considered "requests to access architecture state registers" as recited in claims 1 and 11 as amended.
Even assuming the interrupt requests in Song can be considered "requests to access architecture state registers" (which Applicant does not concede), Applicant further submits that the other cores to which the interrupt requests are routed cannot be considered " an architecture state random access memory (RAM)" as recited in claims 1 and 11.
Applicant’s arguments, with respect to 35 USC 102 rejections, have been fully considered but they are not persuasive for following reasons:
With respect to (a) and (b), first of all, the claims do not specify (i) how the claimed at least one memory” is different from the claimed “architecture state random access memory (RAM)”, and (ii) re-routing from which different memory/location to RAM. Second, in the Stillwell reference, the storage element 212 can be a memory (i.e. RAM). (see Col. 5, lines 54-59). Therefore, it is maintained that Stillwell teaches the “re-routing” limitation as claimed.
With respect to (c) and (d), Examiner agreed that an "interrupt request for a processor core" as taught in Song is different from "requests to access architecture state registers" as recited in claims 1 and 11. Therefore, 103(a) rejection over Stillwell in view of Song is hereby withdrawn.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hetul Patel whose telephone number is (571)272-4184. The examiner can normally be reached M-F 9am-5pm.
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/Hetul Patel/ Supervisory Patent Examiner, Art Unit 3992