DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 13-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 22, 2026.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. At this point in time, Examiner suggests the following title: “LAUNCH OUTCOME INDICATION INDICATING AVAILABILITY OF HARDWARE ACCELERATORS FOR PERFORMING ACCELERATOR OPERATIONS”
The abstract of the disclosure is objected to because of the following informalities:
Delete “[Figure 24]” at the bottom of the abstract
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
Page 100 onward: The example embodiments include language used in the claims. For similar reasoning set forth in the objections/rejections below, these paragraphs should be updated as the claims are updated, particularly where incorrect or unclear.
Examiner makes the following recommendations:
Page 1, Under summary, paragraph 5: Insert a comma before “whilst” and after “present” to improve readability.
Page 2, paragraph 10: Insert a comma before “whilst” and after “present” to improve readability.
Page 3, paragraph 1: Insert a comma before “whilst” and after “present” to improve readability.
Page 20, paragraph 2: Insert a comma before “whilst” and after “present” to improve readability.
Page 21, paragraph 1: Insert a comma before “whilst” and after “present” to improve readability.
Page 101, paragraph 3: Insert a comma before “whilst” and after “present” to improve readability.
Page 101, paragraph 4: Insert a comma before “whilst” and after “present” to improve readability.
Page 104, paragraph 7: Insert a comma before “whilst” and after “present” to improve readability.
Page 104, paragraph 12: Insert a comma before “whilst” and after “present” to improve readability.
Appropriate correction is required.
Drawings
The lengthy set of drawings has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the drawings.
Fig. 27 is objected to for failing to comply with 37 CFR 1.84(i), which requires that words appear in a horizontal, left-to-right fashion when the page is either upright or turned so that the top becomes the right side. Note, from 37 CFR 1.84(f), that the top of the sheet is regarded as one of the shorter sides. The text “VA1”, “VA2”, “PA1”, and “PA2” needs to be rotated 180 degrees.
The drawings are objected for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(I), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawings are pixelated because Applicant did not use black (RGB = 000), despite the drawings appearing black to the naked eye. The dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, Applicant must be sure to use only black and white. Applicant may try the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the process has only been tested in Adobe Acrobat Pro DC);
2. Click "File" and then click "Print";
3. Select "Adobe PDF" as the printer. If not available, "Microsoft Print to PDF" may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck "Print in grayscale (black and white)";
5. Uncheck "Save ink/toner";
6. Click "Advanced";
7. Under "Color Management", for the "Color Profile" field, select "Black & White" near the bottom of the list. The examiner also had "Treat grays as K-only grays" checked, and "Preserve Black" checked.
8. Click "OK" and then click "Print". The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 12, 16, and 22 are objected to because of the following informalities:
Claim 12, line 3: Applicant uses hyphens for the term “accelerator-state-switching-mode” in line 3, but for the same term in claim 10, line 5, Applicant does not use hyphens. Applicant is advised to remove the hyphens in claim 12, line 3, or alternatively, add hyphens in claim 10, line 5.
Claim 16, last line: Insert “selected” before “hardware” to improve clarity.
Claim 22, line 5: Delete “the method comprising” as it’s redundant.
Claim 22, lines 8-10: The “providing” segment does not grammatically fit in the paragraph. Applicant is advised to rewrite the “providing” segment.
Examiner makes the following recommendations:
Claim 1, line 12: Insert a comma before “whilst” and after “present” to improve readability.
Claim 2, line 3: Insert a comma before “whilst” and after “present” to improve readability.
Claim 22, lines 7-8: Insert a comma before “whilst” and after “present” to improve readability.
Claim 23, line 14: Insert a comma before “whilst” and after “present” to improve readability.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of MPEP 2111.04(II):
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.
The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.
Claim 22 recites the contingent limitation “in response to the processing circuitry executing a launch instruction requesting an accelerator operation to be triggered to be performed by a given hardware accelerator” in lines 5-7. The limitation suggests, under BRI, that if the processing circuitry does not execute a launch instruction requesting an accelerator operation to be triggered [and] to be performed by a given hardware accelerator, then the “determining” step is to not occur. Additionally, the claim recites the contingent limitation “whilst the given hardware accelerator is present [and] control storage indicates unavailability of the given hardware accelerator” in lines 7-8. The limitation suggests, under BRI, that if the hardware accelerator is not present or the control storage indicates unavailability of the given hardware accelerator, then the “providing” step does not occur. Applicant is advised to insert “positively occurring” actions within the method claim so that the condition of the contingent limitations may be satisfied and recites the same invention as the independent apparatus claim and independent computing system claim. Note that this does not indicate that the claim is allowable and should not be interpreted in that regard.
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“hardware accelerator… to perform a delegated task… to perform the accelerator operation…” in claims 1, 7, and 22, invoke 112(f). However, Examiner could not find sufficient structure in the specification or drawings. The specification provides support for the structure to perform the function (e.g., page 9, second paragraph; page 23, paragraph 1) but the specification does not describe specific details of what the “hardware accelerator” is exactly. Note that indicating “hardware accelerator” to comprise of “hardware circuit logic” (see page 1, paragraph 2) is not sufficient in a (means/generic placeholder)-plus-function limitation. Therefore, Examiner will interpret the structure as any circuit that performs the limitation. Examiner recommends Applicant to amend the limitation to include “circuitry” to avoid the limitation being interpreted under 112(f) (See MPEP 2181(I)(A), paragraph 3).
“host data processing apparatus to provide an instruction execution environment” in claim 23, invokes 112(f). The structure of the apparatus is indicated to structurally be a processor (see page 99, paragraph 4 and page 100, paragraph 1). Since providing an instruction execution environment is not a coextensive function of a processor, an algorithm needs to be provided (see MPEP 2181(II)(B)). However, Applicant does not describe a particular algorithm to perform the function. Therefore, a processor cannot be used as structure to perform the recited function, resulting in the structure not being sufficient to perform the recited structure.
“simulated hardware accelerator… to perform a delegated task” in claim 23, invokes 112(f). However, Examiner could not find sufficient structure in the specification or drawings. The specification provides support for the structure to perform the function (e.g., page 9, second paragraph) but the specification does not describe specific details of what the “hardware accelerator” is exactly. Note that indicating “hardware accelerator” to comprise of “hardware circuit logic” (see page 1, paragraph 2) is not sufficient in a (means/generic placeholder)-plus-function limitation. Therefore, Examiner will interpret the structure as any circuit that performs the limitation. Examiner recommends Applicant to amend the limitation to include “circuitry” to avoid the limitation being interpreted under 112(f) (See MPEP 2181(I)(A), paragraph 3).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-12, 16-17, and 19-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1, 7, and 22-23, as described below in the 112(b) rejection, the disclosure does not provide adequate structure to perform the claimed functions of performing a delegated task, performing the accelerator operation, or providing an instruction execution environment. The application does not demonstrate that the applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claims 2-12, 16-17, and 19-21 are rejected for inheriting the rejection of the claims in which they depend on.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12, 16-17, and 19-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the same item of control state" in lines 9-10. There is insufficient antecedent basis for this limitation in the claim. There was no prior recitation of “item of control state” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret the limitation to be “a same item of control state”.
Claim 9 is rejected for inheriting the rejection of claim 8.
Claim 8 recites the limitation "the item of control state" in line 13. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to “same item of control state” in claim 8, line 10, or “item of control state” in claim 8, lines 11-12. For the sake of examination, Examiner will interpret the limitation to be referring to “item of control state” in claim 8, lines 11-12.
Claim 9 is rejected for inheriting the rejection of claim 8.
Claim 17 recites the limitation "the result" in line 4. There is insufficient antecedent basis for this limitation in the claim. There was no prior recitation of “the result” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this limitation to be “a result”.
Regarding claims 1, 7, and 22-23, the claims recite claim limitations “hardware accelerator”, “host data processing apparatus”, and/or ”simulated hardware accelerator”, which invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. In particular, the specification states that the claimed functions recited in the “Claim Interpretation” section are done by a “hardware accelerator”, “host data processing apparatus”, and/or “”simulated hardware accelerator”. The use of the terms are not adequate structures for performing the claimed functions mentioned previously because it does not describe a particular structure for performing the functions. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure would perform the claimed functions. Therefore, the claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 2-12, 16-17, and 19-21 are rejected for inheriting the rejection of the claims in which they depend on.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 22 is alternatively rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ben-Kiki et al. (US 20140189426 A1).
Regarding claim 22, Ben-Kiki teaches an apparatus (Fig. 8A and [0017]: Processor architecture), comprising:
executing instructions with processing circuitry (Fig. 8A and [0070]: Processor clusters 804 may execute instructions); and
exchanging control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task (Fig. 8A and [0072-0073]: Register 830 provides communication between processor clusters and accelerator cluster 801, which includes communicating commands, results, and parameters (i.e., control signals) between processor clusters and accelerator clusters. The processing clusters may process an XCALL instruction, which would communicate a command to the accelerator for execution. Registers as the control interface circuitry);
in response to determining, in response to the processing circuitry executing a launch instruction requesting the accelerator control interface circuitry to trigger an accelerator operation to be performed by the given hardware accelerator, that whilst the given hardware accelerator is present the control storage indicates unavailability of the given hardware accelerator, the accelerator control interface circuitry is configured to provide a launch outcome indication indicating to the processing circuitry that the given hardware accelerator is unavailable to perform the accelerator operation (see “Claim Interpretation” section. Limitations are contingent and not required).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 19-20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Nishida et al. (US 20090049219 A1).
Regarding claim 1, Ben-Kiki teaches an apparatus (Fig. 8A and [0017]: Processor architecture), comprising:
processing circuitry to execute instructions (Fig. 8A and [0070]: Processor clusters 804 may execute instructions); and
accelerator control interface circuitry to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task (Fig. 8A and [0072-0073]: Register 830 provides communication between processor clusters and accelerator cluster 801, which includes communicating commands, results, and parameters (i.e., control signals) between processor clusters and accelerator clusters. The processing clusters may process an XCALL instruction, which would communicate a command to the accelerator for execution. Registers as the control interface circuitry);
wherein the accelerator control interface circuitry comprises control storage corresponding to a given hardware accelerator (Fig. 8A and [0072-0073]: The registers 830 is control storage corresponding to the communications of the processor clusters 804 and to at least one accelerator from the accelerator cluster 801); and
in response to determining, in response to the processing circuitry executing a launch instruction requesting the accelerator control interface circuitry to trigger an accelerator operation to be performed by the given hardware accelerator (Fig. 8A and [0072-0073]: Processor clusters 804 may process instructions, such as the XCALL instruction, and send the command to an accelerator from the accelerator cluster 801), that whilst the given hardware accelerator is present , the accelerator control interface circuitry is configured to provide a launch outcome indication indicating to the processing circuitry that the given hardware accelerator is unavailable to perform the accelerator operation (Fig. 8A and [0072-0073, 0085-0089]: The registers 830 receive an indication from the accelerator of the accelerator cluster, in which the processor clusters 804 may access, indicating that the accelerator failed to execute a command (i.e., the accelerator is unavailable to perform the command sent by the processor clusters)).
Ben-Kiki does not teach that the control storage is configured to indicate availability of the given hardware accelerator and could indicate unavailability of the given hardware accelerator.
Nishida teaches control storage indicating availability of an accelerator (Fig. 1 and [0062]: An exception control unit 4 comprises of a register, which may receive busy/idle signals 23 from accelerator 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki with the teachings of Nishida to have the registers of Ben-Kiki indicate that an accelerator is available/busy. By having the accelerator indicate it’s availability and storing that state in a register, a processor could read the accelerators availability rather than waiting for an availability signal from the accelerator, which would provide a faster response to the processor, which may be appreciated by one of ordinary skill.
Regarding claim 3, Ben-KiKi, in view of Nishida, teaches the apparatus according to claim 1, wherein the accelerator control interface circuitry is configured to provide the launch outcome indication in a status storage location accessible to the processing circuitry (Ben-Kiki, Fig. 8A and [0072-0073]: Registers 830 comprise of details indicating the outcome of a command, which may include result data if the processing of a command was successful, or otherwise indicate failure details if the command failed to execute. The registers are accessible by the processor clusters 804).
Regarding claim 19, Ben-Kiki, in view of Nishida, teaches a non-transitory computer-readable storage medium storing computer-readable code for fabrication of the apparatus of claim 1 (Ben-Kiki, [0062-0063]: An embodiment may include non-transitory machine-readable media comprising of instructions to fabricate the embodiment).
Regarding claim 20, Ben-Kiki, in view of Nishida, teaches a system comprising:
the apparatus of claim 1, implemented in at least one packaged chip (Ben-Kiki, Fig. 6 and 8A, [0058]: The processor architecture of Fig. 8A may be implemented as the processor 610 in Fig. 6, which is packaged on an SoC. Therefore, processor is a packaged chip);
at least one system component (Ben-Kiki, Fig. 6: Coprocessors 620 as the system component); and
a board, wherein the at least one packaged chip and the at least one system component are assembled on the board (Ben-Kiki, Fig. 6 and [0058]: The processor 610 and coprocessors 620 are assembled on the same SoC 600).
Regarding claim 22, the claim recites a method similar to the apparatus of claim 1. Therefore the claim is rejected on the same premises.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Nishida et al. (US 20090049219 A1) and Chachad et al. (US 20200371935 A1).
Regarding claim 4, Ben-Kiki, in view of Nishida, teaches the apparatus according to claim 1.
Ben-Kiki, in view of Nishida, does not teach that the control storage is programmable by software to control whether the given hardware accelerator is indicated as available.
Chachad teaches memory-mapped registers programmable by software ([0149]: Control registers memory-mapped so that they are controlled (i.e., programmable) by software executing on a CPU core).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki, in view of Nishida, with the teachings of Chachad to have the register indicating availability of an accelerator be memory-mapped, such that they are programmable by software to control whether the given hardware accelerator is indicated as available. By having the control registers be memory-mapped and controlled by software, one of ordinary skill would have better control over how the accelerator is viewed by the processor through means of software programming, which may be appreciated.
Regarding claim 5, Ben-Kiki, in view of Nishida, teaches the apparatus according to claim 1.
Ben-Kiki, in view of Nishida, does not teach that the control storage is provided in a memory-mapped control register.
Chachad teaches memory-mapped control registers ([0149]: Control register may be memory-mapped registers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Ben-Kiki, in view of Nishida, with the teachings of Chachad to have made the registers be memory mapped registers. By having the registers be memory-mapped, the registers could be controlled by software (see [0149]), in which one of ordinary skill may appreciate.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Nishida et al. (US 20090049219 A1) and Sibert (US 20170103233 A1).
Regarding claim 6, Ben-Kiki, in view of Nishida, teaches the apparatus according to claim 1.
Ben-Kiki, in view of Nishida, does not teach that the apparatus comprises a set of protection level control registers, each protection level control register for controlling operations at a particular protection level, and each protection level control register indicating availability of the given hardware accelerator.
Sibert teaches a set of protection level control registers, each protection level control register for controlling operations at a particular protection level (Fig. 4 and [0089-0090]: A plurality of memory protection registers 151a-z, which correspond to a segment in memory. Each of the memory protection registers controls which privilege levels may access a particular segment in secure memory 102 to read/write from (i.e., controlling operations at a particular protection level). Therefore, the memory protection registers are a set of protection level control registers), and each protection level control register indicating availability of a processor (Fig. 4 and [0089-0090]: When a processor is running at a particular privilege level (e.g., supervisor level, user level, etc.) the memory protection registers 151a-z will indicate the availability of a processor to perform an operation in the particular segment of secure memory 102).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Ben-Kiki, in view of Nishida, with the teachings of Sibert to have implemented memory protection registers for the accelerator clusters, Implementing memory protection registers would prevent unauthorized memory reading/writing by an accelerator if it doesn’t meet the required privilege level, which may be appreciated by one of ordinary skill.
Regarding claim 7, Ben-Kiki, in view of Nishida and Sibert, teaches the apparatus according to claim 6, wherein in response to the processing circuitry executing the launch instruction (Ben-Kiki, Fig. 8A and [0072-0073]: Processor clusters 804 may process instructions, such as the XCALL instruction, and send the command to an accelerator from the accelerator cluster 801), the accelerator control interface circuitry is configured to determine, based on a combination of control state provided by a subset of the protection level control registers for controlling operations at a protection level equal to or higher than a protection level associated with the launch instruction, whether the given hardware accelerator is available to perform the accelerator operation (Ben-Kiki, Fig. 8A and [0072-0073, 0085-0089]; Sibert, Fig. 4 and [0089-0090]: In the current combination, if the XCALL instruction is to have an accelerator from the accelerator cluster access memory, the accelerator would check the memory protection register corresponding to the memory segment (a subset of the memory protection registers) the instruction is trying to access, compare the current privilege level of the accelerator with the allowed privilege levels indicated by the memory protection register, and if the memory protection register indicates that the current privilege level is allowed to access the memory segment (i.e., the protection level is equal to the protection level indicated by the register), the accelerator would be allowed to continue performing the XCALL instruction).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Nishida et al. (US 20090049219 A1) and Song et al. (US 6061711 A).
Regarding claim 10, Ben-Kiki, in view of Nishida, teaches the apparatus according to claim 1.
Ben-Kiki, in view of Nishida, does not teach that, in response to the processing circuitry executing an accelerator-state-switching-mode instruction, the processing circuitry is configured to control the accelerator control interface circuitry to issue to a selected hardware accelerator at least one accelerator-state-switching mode request signal to control the hardware accelerator to enter or exit an accelerator state switching mode in which delegated task progress is halted to support saving or restoration of accelerator state.
Note that the accelerators may perform a context switch through means of performing a save state and restore state instruction in sequence (Ben-Kiki, see [0105]), but does not specify a single instruction that performs either a save instruction followed by a context switch, a context switch followed by a restore instruction, or a save instruction followed by a context switch followed by a restore instruction.
Song teaches a state-switching-mode instruction (Figs. 2 and 6, Col. 8, line 46 to Col. 9, line 12, Col. 10, lines 57-64: conditional context switch instruction, VCCS, is an instruction to indicate state-switching (i.e., a mode of the processor) based on a value read from the VIMSK register 214), in which an interface is to issue a coprocessor a state-switching mode request signal to control the coprocessor to enter a coprocessor state switching mode (Figs. 2 and 6, Col. 8, line 46 to Col. 9, line 12, Col. 10, lines 57-64: coprocessor interface 206 comprises of the register VIMSK 214 which comprises of the bit to indicate context switching. The VCCS instruction causes the coprocessor 204 to read from the bit from the VIMSK register (i.e., the signal would be issued to the coprocessor) to enable context switching (i.e., enter a context-switching mode)) in which task progress is halted to support saving of coprocessor state (Fig. 6, Col. 11, line 40 to Col. 13, line 28: When state switching is to occur, the coprocessor goes through each of steps 608-620, in which the program execution (i.e., a task) of the coprocessor is halted while context (i.e., state) is being saved by the coprocessor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki, in view of Nishida, with the teachings of Song to have the accelerator enter a state-switching mode, in which the mode is to indicate that the accelerator is to halt program execution while saving the accelerator state. By indicating a save internal state and context switch through a single instruction, less instructions would need to be processed in a processing unit as a result to perform the same number of operations, which may be appreciated by one of ordinary skill.
Regarding claim 11, Ben-Kiki, in view of Nishida and Song, teaches the apparatus according to claim 10, wherein in response to issuing the accelerator-state-switching mode request signal, the accelerator control interface circuitry is configured to transfer a portion of internal state to or from the selected hardware accelerator (Ben-Kiki, Fig. 8A and Fig. 11: Song, Fig. 6, Col. 11, line 40 to Col. 13, line 28: In the current combination, the accelerator cluster is to fetch a signal from the registers to perform the command corresponding to the context-switching instruction, in which the instruction is to transfer the internal state of an accelerator to the accelerator save area in memory).
Regarding claim 12, Ben-Kiki, in view of Nishida and Song, teaches the apparatus according to claim 10, wherein the accelerator control interface circuitry is configured to suppress launching of at least a subset of accelerator request signals to a hardware accelerator in the accelerator-state-switching mode (Song, Fig. 6, Col. 11, line 40 to Col. 13, line 28: In the current combination, while an accelerator of the accelerator cluster is in context-switching mode, commands to the accelerator (i.e., accelerator request signals) won’t be processed (i.e., being suppressed) in the meantime).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Nishida et al. (US 20090049219 A1) and Varde et al. (US 20220206825 A1).
Regarding claim 16, Ben-Kiki, in view of Nishida, teaches the apparatus according to claim 1
Ben-Kiki, in view of Nishida, does not teach that, in response to the processing circuitry executing an accelerator reset instruction, the processing circuitry is configured to control the accelerator control interface circuitry to issue to a selected hardware accelerator at least one reset request signal to control the hardware accelerator to clear its internal state.
Note that the accelerators can perform operations corresponding to x86 instructions such as the XRESTORE instruction (Ben-Kiki, see [0133]).
Varde teaches to use the XRESTORE to issue at least one reset request signal to control a processor to clear its internal state (Fig. 10 and [0077-0079]: A processor state may execute the XRSTORE instruction to reset state components (i.e., internal state). The executed XRSTORE instruction will produce signals, which will indicate to first read a mask (EDX:EAX mask) to see which state components are to be initialized without reading from memory. In other words, the state components not read from memory are to be set/cleared to their initial state).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Ben-Kiki, in view of Nishida, with the teachings and techniques of Varde to have the processor execute an accelerator reset instruction to clear its internal state. One of ordinary skill would recognize that if the internal state of the accelerator is active, but the accelerator itself is unused due to a process finishing, for example, power may be consumed and wasted. Therefore, it may be preferred to reset the internal state to reduce power consumption (see [0076]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Nishida et al. (US 20090049219 A1), Stillwell et al. (US 20140007098 A1) and Chachad et al. (US 20200371935 A1).
Felix Cloutier “CPUID — CPU Identification” is cited as extrinsic evidence to explain the details of the CPUID instruction.
Regarding claim 17, Ben-Kiki, in view of Nishida, teaches the apparatus according to claim 1.
Ben-Kiki, in view of Nishida, does not teach that, in response to the processing circuitry executing an accelerator internal state query instruction, the processing circuitry is configured to query an internal size storage location of at least one hardware accelerator and store the result in a software-accessible storage location.
Note that the accelerators can perform operations corresponding to x86 instructions such as the XSAVES instruction (Ben-Kiki, see [0133]), which would indicate an XSAVE area.
Stillwell teaches an accelerator internal state query instruction which queries an internal size storage location of at least one hardware accelerator ([0033]: An accelerator identification instruction may be executed by a processor core to identify details of a single accelerator, which may be a variation of the CPUID instruction in the Intel Core Processor family. The CPUID instruction may indicate the size, in bytes, the XSAVE area of a processor (or in this case, an accelerator) (See Felix Cloutier, Page 7, Table 3-8, EAX Value = 0DH, ECX = 1). Therefore, the XSAVE area as the storage location and the accelerator identification instruction as the accelerator internal state query instruction) and store the result in a storage location ([0033]: “The information may be provided by returning it to or storing it in a particular location in a processor register”; The processor register as the storage location).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki, in view of Nishida, with the teachings of Stillwell to have the processor include an instruction to query the XSAVE area size of the accelerator. One of ordinary skill may appreciate being able to query the size of the XSAVE area as it would indicate the size requirement to store the save state area in memory when performing the XSAVE instruction.
Ben-Kiki, in view of Nishida and Stillwell, still does not teach that storage location is software-accessible.
Chachad teaches memory-mapped registers that are software-accessible ([0149]: Control registers memory-mapped so that they are controlled (i.e., programmable) by software executing on a CPU core. Therefore, the control registers are software accessible).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki, in view of Nishida and Stillwell, with the teachings of Chachad to have the register comprising of the result of the accelerator ID instruction be software-accessible. By having the register be memory-mapped and controlled by software, one of ordinary skill would be able to have better access to the register through software programming.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Song et al. (US 6061711 A).
Regarding claim 18, Ben-Kiki teaches an apparatus (Fig. 8A and [0017]: Processor architecture), comprising:
processing circuitry to perform a delegated task (Fig. 8A and [0070, 0072-0073]: Accelerator clusters 801 may process commands sent from processor clusters 804. The commands being processed by the accelerator clusters as the delegated task); and
interface circuitry to exchange control signals with a processor for configuring the processing circuitry to perform the delegated task (Fig. 8A and [0072-0073]: Register 830 provides communication between processor clusters and accelerator cluster 801, which includes communicating commands, results, and parameters (i.e., control signals) between processor clusters and accelerator clusters. The processing clusters may process an XCALL instruction, which would communicate a command to the accelerator for execution. Registers as the control interface circuitry);
Ben-Kiki does not teach that the interface circuitry is responsive to an accelerator-state-switching mode request signal to control the processing circuitry to:
enter or exit an accelerator state switching mode in which delegated task progress is halted to support saving or restoration of accelerator state; and
transfer a portion of internal state to or from the processor.
Song teaches a state-switching-mode instruction (Figs. 2 and 6, Col. 8, line 46 to Col. 9, line 12, Col. 10, lines 57-64: conditional context switch instruction, VCCS, is an instruction to indicate state-switching (i.e., a mode of the processor) based on a value read from the VIMSK register 214), in which an interface is to issue a coprocessor a state-switching mode request signal to control the coprocessor to enter a coprocessor state switching mode (Figs. 2 and 6, Col. 8, line 46 to Col. 9, line 12, Col. 10, lines 57-64: coprocessor interface 206 comprises of the register VIMSK 214 which comprises of the bit to indicate context switching. The VCCS instruction causes the coprocessor 204 to read from the bit from the VIMSK register (i.e., the signal would be issued to the coprocessor) to enable context switching (i.e., enter a context-switching mode)) in which task progress is halted to support saving of coprocessor state (Fig. 6, Col. 11, line 40 to Col. 13, line 28: When state switching is to occur, the coprocessor goes through each of steps 608-620, in which the program execution (i.e., a task) of the coprocessor is halted while context (i.e., state) is being saved by the coprocessor) and transfer a portion of internal state to or from the processor (Fig. 6, Col. 11, line 40 to Col. 13, line 28: When in the process to store the state information of the coprocessor, the internal state is saved onto memory. In other words, it’s stored away from the processor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki, in view of Nishida, with the teachings of Song to have the accelerator enter a state-switching mode, in which the mode is to indicate that the accelerator is to halt program execution while saving the accelerator state. By indicating a save internal state and context switch through a single instruction, less instructions would need to be processed in a processing unit as a result to perform the same number of operations, which may be appreciated by one of ordinary skill.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Nishida et al. (US 20090049219 A1) and Pant et al. (US 9973187 B1).
Regarding claim 20, Ben-Kiki, in view of Nishida, teaches a chip-containing product comprising the system of claim 20
Ben-Kiki, in view of Nishida, does not teach that the system is assembled on a further board with at least one other product component.
Pant teaches a system assembled on a further board with at least one other product component (Col. 4, lines 38-39: In other words, the SoC may be mounted on a circuit board, the circuit board to be the further board and disposed on a smart phone, which consists of various product components. The SoC as the system).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki, in view of Nishida, with the teachings of Pant to have further assembled the SoC on a further board with at least one other product component. By implementing a system on a further board would allow one of ordinary skill to implement their designs on a plurality of final products.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Ben-Kiki et al. (US 20140189426 A1) in view of Nishida et al. (US 20090049219 A1) and Parker et al. (US 20230176983 A1).
Regarding claim 23, Ben-Kiki teaches processing program logic to execute instructions (Fig. 8A and [0070]: Processor clusters 804 may execute instructions. Processor clusters as the processing program logic); and
accelerator control interface program logic to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing program logic, to perform a delegated task (Fig. 8A and [0072-0073]: Register 830 provides communication between processor clusters and accelerator cluster 801, which includes communicating commands, results, and parameters (i.e., control signals) between processor clusters and accelerator clusters. The processing clusters may process an XCALL instruction, which would communicate a command to the accelerator for execution. Registers as the control interface program logic);
wherein the accelerator control interface program logic comprises control storage corresponding to a given hardware accelerator (Fig. 8A and [0072-0073]: The registers 830 is control storage corresponding to the communications of the processor clusters 804 and to at least one accelerator from the accelerator cluster 801); and
in response to determining, in response to the processing program logic executing a launch instruction requesting the accelerator control interface program logic to trigger an accelerator operation to be performed by the given hardware accelerator (Fig. 8A and [0072-0073]: Processor clusters 804 may process instructions, such as the XCALL instruction, and send the command to an accelerator from the accelerator cluster 801), that whilst the given hardware accelerator is present , the accelerator control interface program logic is configured to provide a launch outcome indication indicating to the processing program logic that the given hardware accelerator is unavailable to perform the accelerator operation (Fig. 8A and [0072-0073, 0085-0089]: The registers 830 receive an indication from the accelerator of the accelerator cluster, in which the processor clusters 804 may access, indicating that the accelerator failed to execute a command (i.e., the accelerator is unavailable to perform the command sent by the processor clusters)).
Ben-Kiki does not teach that the control storage is configured to indicate availability of the given simulated hardware accelerator and could indicate unavailability of the given simulated hardware accelerator.
Nishida teaches control storage indicating availability of an accelerator (Fig. 1 and [0062]: An exception control unit 4 comprises of a register, which may receive busy/idle signals 23 from accelerator 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki with the teachings of Nishida to have the registers of Ben-Kiki indicate that an accelerator is available/busy. By having the accelerator indicate it’s availability and storing that state in a register, a processor could read the accelerators availability rather than waiting for an availability signal from the accelerator, which would provide a faster response to the processor, which may be appreciated by one of ordinary skill.
Ben-Kiki, in view of Nishida, still does not teach a non-transitory computer-readable storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment.
Parker teaches a non-transitory computer-readable storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment (see Fig. 15 and [00171-00175]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Ben-Kiki, in view of Nishida, with the teachings of Parker to have a computer program to control a host data processing apparatus to provide an instruction execution environment. One of ordinary skill would recognize that by generating an instruction execution environment for the computer program, one of ordinary skill would be able to test the program on simulated hardware/features that isn’t currently available on a host device (see [00173]).
Allowable Subject Matter
Claims 8-9 are allowed, over the prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art of record has not taught, either individually or in combination, and together with all other claimed features, control register access circuitry to control access to at least one memory-mapped control register providing control state, wherein for a set of aliasing physical addresses each corresponding to a different physical memory page, the control register access circuitry is configured to treat a first access request issued by the processing circuitry to access a first physical address in the set of aliasing physical addresses and a second access request issued by the processing circuitry to access a second physical address in the set of aliasing physical addresses as access requests to the same item of control state in a given memory-mapped control register, and the control register access circuitry configured to handle an access request to an item of control state using access permissions selected depending on which physical address from the set of aliasing physical addresses is used to access the item of control state.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20030093648 A1: Moyer teaches a processor with multiple coprocessors, in which the coprocessors indicate availability through a “BUSY” signal.
US 20190384726 A1: Murphy teaches a process in which a host communicates with a memory system, in which the memory system comprises of privilege registers and mode registers to restrict memory access.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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