DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 & 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khanna US 20200033533.
With respect to claim 1, Khanna teaches a first photonics integrated circuit (PIC) chip, the first PIC chip having originated from a PIC wafer, the first PIC chip comprising:
a substrate (fig 1, 100);
one or more optical communication components (fig 1, 125 & 135) fabricated on the substrate; and
optical testing components (fig 1, 120 & 110) fabricated on the substrate “forming the test gap between the two test edge couplers” (0005, lines 1-2), the optical testing components configured to, prior to die singulation “prior to dicing” (0005, lines 7-10) of the PIC wafer, transfer light “inject test light” (0048, lines 15-17) “optical coupling therebetween” (0038, lines 1-2) to a second PIC chip (fig 2, 110) on the PIC wafer for testing one or more operational attributes “determining coupling loss” (abstract, lines 8-10) of optical components disposed on the second PIC chip, wherein the second PIC chip (fig 1) was adjacent to the first PIC chip on the PIC wafer prior to die singulation of the PIC wafer “prior to dicing” (0005, lines 7-10).
With respect to claim 2 according to claim 1, Khanna teaches the first PIC chip wherein the optical testing components comprise:
a first edge coupler (fig 1, 125) fabricated “forming the test gap between the two test edge couplers” (0005, lines 1-2) on the substrate, the first edge coupler configured to, prior to die singulation of the PIC wafer “prior to dicing” (0005, lines 7-10), transfer light to a second edge coupler of the second PIC chip for testing at least a first operational attribute “determining coupling loss” (abstract, lines 8-10) among the one or more operational attributes “estimating a coupling loss of one edge coupler” of the optical components disposed on the second PIC chip “two or more test structures on the number of edge coupler pairs therein” (0007, col 2, lines 6-8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 & 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khanna US 20200033533 in view of Traverso US 20180313718.
With respect to claim 3 according to claim 2, Khanna does not teach an optical coupler being configured to receive light from an optical testing probe and a waveguide optically coupled to the optical coupler and the first edge coupler, the waveguide being configured to transfer light between the optical coupler and the first edge coupler.
Traverso, in the same field of endeavor of diced wafer substrates, teaches an optical coupler i.e. grating coupler (fig 2, 240) fabricated on a wafer substrate, wherein the optical coupler is configured to receive light from an optical testing probe (0042, lines 1-2). Traverso further teaches a waveguide (fig 2, 220B) fabricated on the substrate is optically coupled to the optical coupler and a first edge coupler (fig 2, 225B) transferring light from the optical coupler to the edge coupler. At the time prior to the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to combine Traverso’s optical coupler and waveguide with Khanna’s first edge coupler as a known technique to enable light from the outside light source to travel to the edge couplers.
With respect to claim 4 according to claim 3, the combination teaches the optical coupler comprises a grating coupler (fig 2, 240 Traverso).
Allowable Subject Matter
Claims 9-25 are allowed. Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims or to include the limitation(s) and any intervening claims into the base claim. The following is a statement of reasons for the indication of allowable subject matter:
As to claim 5, the prior art of record, taken alone or in combination, fails to disclose or render obvious “a third edge coupler fabricated on the substrate, the third edge coupler configured to, prior to die singulation of the PIC wafer, receive light from a fourth edge coupler of the second PIC chip for testing at least a second operational attribute among the one or more operational attributes of the optical components disposed on the second PIC chip”, in combination with the rest of the limitations of claim 5.
As to claim 8, the prior art of record, taken alone or in combination, fails to disclose or render obvious “generate one or more electrical signals associated with at least a first operational attribute among the one or more operational attributes of the optical components disposed on the second PIC chip; and provide the one or more electrical signals to the one or more electrical pads for output to an electrical testing probe mechanism”, in combination with the rest of the limitations of claim 8.
As to claim 9, the prior art of record, taken alone or in combination, fails to disclose or render obvious “fabricating on the substrate testing components distinct from the one or more optical components and the one or more electrical components corresponding to the at least one of i) the optical communication transmitter, and ii) the optical communication receiver, the testing components configured to, while the PIC chip and another PIC chip adjacent to the PIC chip are integral with the PIC wafer, transfer light to the other PIC chip for testing one or more operational attributes of optical components disposed on the other PIC chip”, in combination with the rest of the limitations of claim 9.
Conclusion
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/MAURICE C SMITH/Examiner, Art Unit 2877