DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's election with traverse of Group I, encompassed by claims 1-14 is acknowledged. Claims 1-20 are pending, of which, claims 15-20 have been withdrawn.
Response to Arguments
Applicant's Remarks filed on 03/12/2026 have been fully considered. In response to Applicant's argument on page 7 of Remarks, Examiner respectfully disagrees for the following reasons. Group I and Group II are independent or distinct for the reasons given in the requirement for restriction/election issued on 01/28/2026. Moreover, each group requires a different field of search including employing different search strategies and queries. A search for Group I has not resulted in finding prior arts pertinent to Group II. As evident in the rejection presented below for Group I, the prior arts applicable to Group I are not applicable to Group II. Thus, there would be a serious search and examination burden if restriction were not required. The requirement is still deemed proper and is therefore made final.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, and 6-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites “the transactions”, however it is unclear whether this term refers to “trust levels of transactions” as recited in claim 1, “trust levels of transitions” recited in claim 2, or some other transactions. For the purpose of examination, “the transactions” has been interpreted as referring to any transactions. Claim 6 also has similar issue.
Dependent claims are also rejected for inheriting the deficiencies of the claims from which they depend on.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, and 9-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jin et al. (US 2025/0077468).
Claim 1, Jin teaches:
A device, comprising:
a plurality of chiplets, wherein at least one pair of chiplets of the plurality of chiplets is coupled to one another; (e.g., fig. 2)
wherein each chiplet of the plurality of chiplets includes a Root-of-Trust (RoT) circuit and a trust level mapping circuit; and (e.g., figs. 1-2, [0060], “The plurality of IP blocks 110_1 to 110_n may be reusable logics, cells, and/or units of integrated circuit layout design. Each of the plurality of IP blocks 110_1 to 110_n may be designed to perform a specific function and functionally combined to implement a complex multifunctional SoC. For example, an IP block may include a processor core, a memory block, a digital signal processor (DSP), a peripheral interface, a graphics device (GPU), an analog block, a communication block, a security block, a power management device, etc.” [0063], “The protocol layer 121 may determine a method of formatting and encoding data for data transmission between chiplets” [0064], “The protocol layer 121 may include a conversion device 123 for implementing a protocol independent chiplet system. The conversion device 123 may include an encoder that generates a payload of a die-to-die interface flit from the received transaction and/or a decoder that generates a transaction from the payload of the received die-to-die interface flit. This will be described in more detail below with reference to FIGS. 4 and 5”)
wherein, for each chiplet of the plurality of chiplets, the trust level mapping circuit of the chiplet is configured to modify trust levels of transactions received from a different chiplet of the plurality of chiplets. (e.g., fig. 10, [0154], “a method for transmitting a first protocol type transaction of a first chiplet 1510 to a second chiplet 1550…The first chiplet 1510 may utilize the first protocol type transaction…In addition, the second chiplet 1550 may utilize the second protocol type transaction” [0155], “The first chiplet 1510 may convert the first protocol type transaction into a die-to-die interface flit and transmit the converted transaction to the second chiplet 1550. In this case, the first chiplet 1510 may modify the first protocol type transaction based on the encoding information…and generate a payload 1540 of the die-to-die interface flit” [0157], “The second chiplet 1550 may generate a second protocol type transaction from the payload 1540. The process of generating the second protocol type transaction using the payload 1540 in the second chiplet 1550 may be referred to as a decoding process in the second chiplet 1550. The payload 1540 includes data for two separate transactions, and the second chiplet 1550 may generate a plurality of second protocol type transactions 1560 and 1570”)
Claim 2, Jin teaches:
wherein each trust level mapping circuit includes a trust level map, and wherein each trust level map specifies a mapping of trust levels of transactions originating from a source chiplet to local trust levels of a local chiplet receiving the transactions. (e.g., figs. 10, 12, 15, [0083], [0085], [0093], [0132])
Claim 3, Jin teaches:
wherein each trust level mapping circuit further comprises: a mapping circuit configured to receive a selected transaction from the source chiplet and, in response to receiving the selected transaction, select a local trust level for the selected transaction based on the trust level map; and a trust level update circuit configured to update the selected transaction by replacing a trust level of the selected transaction with the local trust level for the selected transaction. (e.g., figs. 10, [0154]-[0157])
Claim 4, Jin teaches:
wherein a RoT circuit of a first chiplet of the plurality of chiplets is configured to program each trust level mapping circuit with the trust level map specific to the trust level mapping circuit. (e.g., figs. 10, 12, 15, [0060], [0064], [0085], [0093], [0132])
Claim 5, Jin teaches:
A device, comprising:
a first chiplet including a first Root-of-Trust (RoT) circuit and a first trust level mapping circuit; and a second chiplet coupled to the first chiplet, wherein the second chiplet includes a second RoT circuit and a second trust level mapping circuit; (e.g., figs. 1-2, [0060], “The plurality of IP blocks 110_1 to 110_n may be reusable logics, cells, and/or units of integrated circuit layout design. Each of the plurality of IP blocks 110_1 to 110_n may be designed to perform a specific function and functionally combined to implement a complex multifunctional SoC. For example, an IP block may include a processor core, a memory block, a digital signal processor (DSP), a peripheral interface, a graphics device (GPU), an analog block, a communication block, a security block, a power management device, etc.” [0063], “The protocol layer 121 may determine a method of formatting and encoding data for data transmission between chiplets” [0064], “The protocol layer 121 may include a conversion device 123 for implementing a protocol independent chiplet system. The conversion device 123 may include an encoder that generates a payload of a die-to-die interface flit from the received transaction and/or a decoder that generates a transaction from the payload of the received die-to-die interface flit. This will be described in more detail below with reference to FIGS. 4 and 5”)
wherein the first trust level mapping circuit is configured to modify trust levels of transactions received from the second chiplet; and wherein the second trust level mapping circuit is configured to selectively modify trust levels of transactions received from the first chiplet. (e.g., fig. 10, [0154], “a method for transmitting a first protocol type transaction of a first chiplet 1510 to a second chiplet 1550…The first chiplet 1510 may utilize the first protocol type transaction…In addition, the second chiplet 1550 may utilize the second protocol type transaction” [0155], “The first chiplet 1510 may convert the first protocol type transaction into a die-to-die interface flit and transmit the converted transaction to the second chiplet 1550. In this case, the first chiplet 1510 may modify the first protocol type transaction based on the encoding information…and generate a payload 1540 of the die-to-die interface flit” [0157], “The second chiplet 1550 may generate a second protocol type transaction from the payload 1540. The process of generating the second protocol type transaction using the payload 1540 in the second chiplet 1550 may be referred to as a decoding process in the second chiplet 1550. The payload 1540 includes data for two separate transactions, and the second chiplet 1550 may generate a plurality of second protocol type transactions 1560 and 1570”)
Claim 6, Jin teaches:
wherein each trust level mapping circuit includes a trust level map, and wherein each trust level map specifies a mapping of trust levels of transactions originating from a source chiplet to local trust levels of a local chiplet receiving the transactions. (e.g., figs. 10, 12, 15, [0083], [0085], [0093], [0132])
Claim 7, Jin teaches:
wherein each trust level mapping circuit further comprises: a mapping circuit configured to receive a selected transaction from the source chiplet and, in response to receiving the selected transaction, select a local trust level for the selected transaction based on the trust level map; and a trust level update circuit configured to update the selected transaction by replacing a trust level of the selected transaction with the local trust level for the selected transaction. (e.g., figs. 10, [0154]-[0157])
Claim 9, Jin teaches:
wherein the local trust level is selected from an entry in the trust level map that matches the trust level of the selected transaction. (e.g., figs. 7-9, [0101], [0105], [0107], [0109], [0112])
Claim 10, Jin teaches:
wherein: the first trust level mapping circuit comprises a first trust level map specifying a mapping of trust levels of transactions received from the second chiplet to local trust levels for the first chiplet; and the second trust level mapping circuit comprises a second trust level map specifying a mapping of trust levels of transactions received from the first chiplet to local trust levels for the second chiplet. (e.g., figs. 10, 12, 15, [0083], [0085], [0093], [0132])
Claim 11, Jin teaches:
wherein the first trust level map and the second trust level map are different. (e.g., figs. 7, 12, 15, [0104])
Claim 12, Jin teaches:
wherein the first trust level map is specific to the first trust level mapping circuit and the second trust level map is specific to the second trust level mapping circuit. (e.g., figs. 10, 12, 15, [0064], [0085], [0093], [0132])
Claim 13, Jin teaches:
wherein the first RoT circuit is configured to program the first trust level map into the first trust level mapping circuit and to program the second trust level map into the second trust level mapping circuit. (e.g., figs. 10, 12, 15, [0060], [0064], [0085], [0093], [0132])
Claim 14, Jin teaches:
wherein: the first RoT circuit is configured to assign trust levels to Intellectual Property cores of the first chiplet; and the second RoT circuit is configured to assign trust levels to Intellectual Property cores of the second chiplet. (e.g., fig. 10, [0060]-[0061])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 2025/0077468) in view of Boucard et al. (US 2025/0363248).
Claim 8, Jin teaches wherein the local trust level is a default trust level (see above) and does not appear to explicitly teach but Boucard teaches:
selected in response to detecting that a trust level of a selected transaction does not match any entry in a trust level map. (e.g., [0051])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings described by Boucard into the invention of Jin, and the motivation for such an implementation would be for the purpose of enabling data security while avoiding or reducing an increase in latency, power consumption, and utilization of device resources (Boucard [0069]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2025/0061181 teaches establishing root of trust from multiple chiplet roots of trust.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIE C LIN whose telephone number is (571)272-7752. The examiner can normally be reached M-F 9:00AM -5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GELAGAY SHEWAYE can be reached at (571)272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMIE C. LIN/Primary Examiner, Art Unit 2436
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