DETAILED ACTION
This action is in response to the filing 07/06/2026. Claims 1-20 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-4, 6-9, 11-14, 16-18, and 20 are rejected under 35 U.S.C. 103.
Claims 5, 10, 15, and 19 contain allowable subject matter but are objected to as being dependent upon rejected base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9, 11-14, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fruend et al. (U.S. Patent No. 10747258) in view of Millar et al. (U.S. Patent No. 5297276), further in view of Greenblat (U.S. PGPub No. 20030172190).
Regarding Claim 1, Fruend teaches,
A system comprising: a debug circuit disposed within the system with connectivity to a central processing unit (CPU), the debug circuit coupled to a plurality of logic blocks forming one or more datapaths, the system configured to: transmit a freeze signal the plurality of logic blocks within the system when an error or trigger event is detected in a logic block of the plurality of logic blocks (CPU: [Col. 3; line 26]; where test circuit (330) is used to debug and is coupled to the plurality of logic blocks [Fig. 3; Col. 9, lines 25-26]; where the system synchronously freezes DRO cells (logic blocks) in response to a triggering event in one of the logic blocks [Col. 5, line 66- Col 6, line 1])
and allow each logic block of the plurality of logic blocks to determine how to respond to the freeze signal (each logic block may provide independent support functions [Col. 5, lines 38-41]; including responding to the freeze signal in not-real time, pending the logic block's timing ("determine how to respond") [Col. 5, lines 44-47]);
and generate, by a debug freeze controller, a freeze clock signal provided to a main functional logic of the logic block to freeze datapaths across the plurality of logic blocks for debugging (the enable signal for the logic blocks is turned off ("freeze clock signal") [Col. 11, lines 16-18]; where the freeze interrupt may also freeze part or all of the system in addition to the DRO system [Col. 10, lines 9-13])
while permitting status, trace, and memory content to be read when the logic block enters into the clock freeze mode (status and memory are read when the blocks are in a freeze mode [Col. 11, lines 34-35]; the system further maintains trace logic for system debugging [Col. 10, line 12]).
Fruend does not appear to disclose and Millar teaches,
upon receipt of the freeze signal and prior to entry into a clock freeze mode, … or single-stepping a packet bus interface (See Fig. 2A-2B as corresponds to the following text citations; main system (110) receives a master reset signal (140) ("freeze signal") placing the main system in a pre-initialization first sleep state [Col. 5, lines 45-54]; note that while clocks pulses are paused at step 201(a) [Col. 5, lines 45-54], clocks are restarted at (201b) [Col. 6, lines 1-3]; now, with active clocks, the main system (110) is reconfigured according to initialization data [Col. 6, line 4] where between steps 201(a) and 201(b), the main system can be placed into a single-step mode [Col. 8, lines 22-26]; following, at step (215), the clocks are stopped [Col. 9, lines 34-37]; explicitly, the act of offloading event information occurs before the clock-stop command issued at (215) so as to assure completion of the loading step [Col. 9, lines 54-60]);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the debug circuit allowing independent responses by logic blocks to a freeze signal prior to a freeze clock signal as taught by Fruend to specifically include logic blocks performing an action between a freeze signal and a clock freeze mode as taught by Millar. The resulting combination allows for a system to remain deterministic regardless of a second system that may be attempting to input to the main system during a debugging procedure [Miller; Col. 1, line 52 - Col. 2, line 6; Col. 2, lines 27-42]
Fruend in view of Miller do not appear to disclose and Greenblat teaches [in bold, however, entire limitation reproduced for clarity],
wherein the response, …, comprises controlling a packet interface by at least one of asserting backpressure, dropping packets at a packet boundary, or single-stepping a packet bus interface (where, in a system with adjacent members in a ring, a backpressure signal may be generated that is used at an interface [0194]);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the debug circuit allowing independent responses by logic blocks to a freeze signal prior to a clock freeze as taught by Fruend in view of Millar to incorporate the feature of independent members generating a backpressure signal. The resulting combination of allowing independent logical blocks/members to generate a backpressure signal allows for the message to be carried in a single clock cycle [Greenblat; 0194], therefore allowing rapid independent response to the system freeze signal and preventing input to the now frozen logical blocks/members.
Regarding Claim 2, Fruend teaches,
The system of claim 1, wherein a status freeze signal is generated by the debug freeze controller to stop a trace logic block from tracing incoming data (the system may also generate a freeze signal to maintain existing trace data [Col. 10, lines 9-13]).
Regarding Claim 3, Fruend teaches,
The system of claim 2, wherein a debug status of each of the plurality of logic blocks is collected at a time the error or trigger event was detected (snapshots of the system data for a period of time are provided ("collected"), where the data is collected preceding a triggering event [Col. 6, lines 2-6]).
Regarding Claim 4, Fruend teaches,
The system of claim 2, wherein statistics are collected within a same time sampling window across the system (the statistics are collected across a synchronized time window ("same time window") across the system [Col. 5, lines 14-16])
to perform a debug operation to determine a cause for the error or the trigger event (the collected statistics are used to isolate the trigger event to a location [Col. 9, lines 51-54]; furthermore, debugging may be performed from this information (exiting DRO cell 710) [Col. 9, lines 24-26]).
Regarding Claim 6, Fruend teaches,
The system of claim 1, wherein the debug circuit further includes interface statistics circuitry configured to provide statistics for a packet interface, an Advanced eXtensible Interface (AXI) interface, or other protocol interface to count at least utilization cycles and backpressure cycles (the system may be configured to facilitate packet processing [Col. 11, line 33- Col. 12, line 14], including applicable interfaces [Col. 12, lines 16-17]).
Regarding Claim 7, Fruend teaches,
The system of claim 6, wherein the interface statistics circuitry includes a live counter (counter circuit (420) [Col. 6, lines 23-25]) and a latch counter (storage register (440) [Col. 6, lines 25-26]).
Regarding Claim 8, Fruend teaches,
The system of claim 1, wherein the debug circuit monitors interface counters during a time sampling window across all the logic blocks of the system (the counters are monitored during a pre-set time window [Col. 6, lines 58-61]).
Regarding Claim 9, Fruend teaches,
The system of claim 8, wherein the time sampling window includes a reset window to determine a sample period and a load window to determine a duration of latched values in latch counters (the sampling occurs during a window ("reset window") [Col. 6, lines 58-61]; with a load window [Col. 6, lines 21-25]).
Claims 11-14 and 16-18 recite a shift in statutory category and are rejected under 35 U.S.C. 103 as being unpatentable by Fruend in view of Millar, further in view of Greenblat, by the same grounds of rejection as Claims 1-4 and 6-8, respectively, above.
Regarding Claim 11, Fruend additionally teaches,
An integrated circuit (IC) (IC: [Col. 4, line 45]), comprising …
Claim 20 recites the method of Claim 1’s system and is rejected under 35 U.S.C. 103 as being unpatentable by Fruend in view of Millar, further in view of Greenblat, by the same grounds of rejection as Claim 1, above.
Allowable Subject Matter
Claims 5, 10, 15, and 19 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitation of the base claim and any intervening claims. The following is the Examiner’s statement of reasons for indicating allowable subject matter:
The subject matter of Claims 5, 10, 15, and 19 remain allowable for the reasons previously provided in the Office Action dated 20 August 2025.
Response to Arguments
Applicant’s arguments filed 07/06/2026 have been fully considered.
Applicant’s arguments with respect to amended Claims 1, 11, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The Examiner acknowledges that Fruend in view of Greenblat, alone, do not disclose the amendment reciting, “upon receipt of the freeze signal and prior to entry into a clock freeze mode.” However, Fruend in view of newly cited Miller, further in view of Greenblat, do teach this limitation. Please see the rejection under 35 U.S.C. 103 above for further detail.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takeuchi (U.S. Patent No. 4275441) discloses a flow for debugging a program before starting a clock stop signal at a single-step mode.
Yee (U.S. PGPub No. 20050149892) discloses disabling stepping control logic with a delay before the clock control unit controlling the stepping enable signal is disabled.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.E.W./Examiner, Art Unit 2113
/MARC DUNCAN/Primary Examiner, Art Unit 2113
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