DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 06/28/2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 13-14, 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakano (US Pub 2020/0403609).
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Above modified Fig. is provided to compare with following each and every prior art(s) teaching, under BRI
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Above Fig. 4 is detail of Fig. 1’s ‘driver circuitry, QA’ or driver circuitry, QB’, from Nakano (US Pub 2020/0403609)
Regarding independent claim 1, Nakano teaches (Fig. 1, 4; Abstract and Para 12-50) an apparatus comprising:
a first input (1st input ‘INPUT’ received by 100, which is then eventually drives gate for main switch MOSFET Q) operative to receive a first control signal (i.e., 100 received INPUT and providing gate drive for Q) indicating how to control a main switch (main switch MOSFET Q);
switch driver circuitry (driver circuitry 100 converts taught 1st control signal INPUT, into 2nd control signal, which is output of 100) operative to convert the first control signal (1st control signal INPUT) into a second control signal (2nd control signal is output of 100); and
an output (i.e., combined operation of 102, 104, IR, SW1-2) operative
to output the second control signal to the main switch (2nd control signal is output of 100),
the second control signal
including first current (i.e., when SW1-2 are on, a saturation current of Ir, operative to adjust over time in order to minimize Vgate overcharging for main switch Q) supplied from a first current source (1st current source ‘Ir, SW1-2’) of the switch driver circuitry to the main switch (main switch Q’s gate),
a magnitude of the first current varying (i.e., when SW1-2 are on, a saturation current of Ir, operative to adjust over time in order to minimize Vgate overcharging for main switch Q; wherein SW1-2 operation is based on feedback operation of ‘102, 104’, output of which is used to vary the resistance in 100 and respectively controlling the switching operation duration period for SW1-2)
based on a voltage magnitude of the second control signal (2nd control signal is output of 100).
Regarding claim 13, Nakano teaches (Fig. 1, 4; Abstract and Para 12-50)
a second input (100 receiving 2nd input being 104’s output) operative to receive feedback tracking (i.e., tracked feedback being any one of -input of Amp or 102’s operational input, each input being connected to main switch Q’s output at its source) the voltage magnitude of the second control signal (2nd control signal is output of 100 and its respective voltage magnitude, used to drive Q);
a comparator (i.e., 102’s Cmp or diff Amp) operative to compare the received feedback (i.e., tracked feedback is received in Cmp’s + input, via 102’S Sub output; wherein the tracked feedback being any one of -input of Amp or 102’s operational input, each input being connected to main switch Q’s output at its source) to a threshold level (Er or +input of Amp); and
a signal generator (104) operative to terminate activation (i.e., when 102’s output determines a deactivation signal in 104) of the first current source supplying the first current (i.e., when SW1-2 are on, a saturation current of Ir, operative to adjust over time in order to minimize Vgate overcharging for main switch Q; wherein SW1-2 operation is based on feedback operation of ‘102, 104’, output of which is used to vary the resistance in 100 and respectively controlling the switching operation duration period for SW1-2) to the main switch (Q) in response to detecting (i.e., 102’s Cmp or diff Amp) that the feedback (i.e., tracked feedback is received in Cmp’s + input, via 102’S Sub output; wherein the tracked feedback being any one of -input of Amp or 102’s operational input, each input being connected to main switch Q’s output at its source) is greater than the threshold level (Er or +input of Amp).
Regarding claim 14, Nakano teaches (Fig. 1, 4; Abstract and Para 12-50) a first switch (i.e., SW2 connected between Q’s gate and source node) connected between a gate node of the main switch (Q’s gate) and a source node of the main switch (Q’s source), the first switch (i.e., SW2 connected between Q’s gate and source node) operative to short the gate node of the main switch to the source node of the main switch during startup of the switch driver circuitry (driver circuitry 100 converts taught 1st control signal INPUT into 2nd control signal, which is output of 100) to prevent activation of the main switch (preventing Q1 being on).
Regarding independent claim 18, Nakano teaches (Fig. 1, 4; Abstract and Para 12-50) a method comprising:
via a first input of switch driver circuitry (1st input ‘INPUT’ received by 100, which is then eventually drives gate for main switch MOSFET Q), receiving a first control signal (i.e., 100 received INPUT and providing gate drive for Q) indicating how to control a main switch (main switch MOSFET Q);
via the switch driver circuitry, converting the first control signal into a second control signal (driver circuitry 100 converts taught 1st control signal INPUT, into 2nd control signal, which is output of 100); and
via an output (i.e., combined operation of 102, 104, IR, SW1-2) of the switch driver circuitry (driver circuitry 100 converts taught 1st control signal INPUT, into 2nd control signal, which is output of 100),
outputting the second control signal to the main switch (2nd control signal is output of 100),
the second control signal (2nd control signal is output of 100)
including first current (i.e., when SW1-2 are on, a saturation current of Ir, operative to adjust over time in order to minimize Vgate overcharging for main switch Q) supplied from a first current source (1st current source ‘Ir, SW1-2’) of the switch driver circuitry to the main switch (main switch Q’s gate),
a magnitude of the first current varying i.e., when SW1-2 are on, a saturation current of Ir, operative to adjust over time in order to minimize Vgate overcharging for main switch Q; wherein SW1-2 operation is based on feedback operation of ‘102, 104’, output of which is used to vary the resistance in 100 and respectively controlling the switching operation duration period for SW1-2)
based on a voltage magnitude of the second control signal (2nd control signal is output of 100).
Claims 1, 5-8, 13-14, 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pavlin et al. (“Pavlin”, US Pub 2012/0081092).
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Above Fig. 1-2 are from Pavlin et al. (“Pavlin”, US Pub 2012/0081092).
Regarding independent claim 1, Pavlin teaches (Fig. 1-2; Para 8-12) an apparatus comprising:
a first input operative to receive a first control signal indicating how to control a main switch (1st input to driver is a 1st control signal being PWM to control main switch S1);
switch driver circuitry (switch driver circuitry being ‘+UH, gnd, I1-3 with respective series connected switches, I1’-3’ with respective series connected switches, inverter/driver that receives PWM’; wherein taught switch driver circuitry converts taught 1st control signal PWM into 2nd control signal inverse PWM to control main switch S1) operative to convert the first control signal (1st control signal PWM) into a second control signal (2nd control signal inverse PWM); and
an output (i.e., an output being other element’s combined operation of ‘cmp1-3, AND gate,’ that drives main switch S1, using level shifted driving/varying/programming/trimming, etc. methods of taught switch driver circuitry) operative
to output the second control signal to the main switch (2nd control signal inverse PWM driving main switch S1),
the second control signal
including first current (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1) supplied from a first current source (i.e., 1st current source I1’ and series connected switch, connecting to node 108) of the switch driver circuitry to the main switch (main switch S1’s gate),
a magnitude of the first current varying (saturation current of I1’-3’ being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1)
based on a voltage magnitude of the second control signal (2nd control signal inverse PWM driving main switch S1).
Regarding claim 5, Pavlin teaches (Fig. 1-2; Para 8-12)
a second current source (i.e., 2nd current source I2’ and series connected switch, connecting to node 108) operative to produce second current (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1), the second current source (i.e., 2nd current source I2’ and series connected switch, connecting to node 108) disposed in parallel with the first current source (i.e., 1st current source I1’ and series connected switch, connecting to node 108), the second control signal (2nd control signal inverse PWM driving main switch S1) derived (i.e., using feedback loop operation of taught output, which is other elements combined operation of ‘cmp1-3, AND gate,’ that drives main switch S1, using level shifted driving/varying/programming/trimming, etc. methods of taught switch driver circuitry) based on a combination of the first current (i.e., 1st current source I1’ and series connected switch, connecting to node 108) and the second current (i.e., 2nd current source I2’ and series connected switch, connecting to node 108); and
wherein the second control signal is applied to a gate node of the main switch to control the main switch (2nd control signal inverse PWM driving main switch S1).
Regarding claim 6, Pavlin teaches (Fig. 1-2; Para 8-12)
wherein the first control signal indicates to activate the main switch for a time duration (Fig. 1-2; 1st input to driver is a 1st control signal being PWM to control main switch S1); and
wherein the first current source (i.e., 1st current source I1’ and series connected switch, connecting to node 108) is operative to:
i) supply (i.e., when respective switches are on to adjust respective current of I1’-3’ at node 108 to control main switch S1) the first current to the gate node of the main switch for a first portion of the time duration (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1), and
ii) discontinue supply (i.e., when respective switches are off to adjust respective current of I1’-3’ at node 108 to control main switch S1) of the first current to the gate node of the main switch for a second portion of the time duration (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1),
the second portion (i.e., above steps ii) following the first portion (i.e., above step i).
Regarding claim 7, Pavlin teaches (Fig. 1-2; Para 8-12)
wherein the second current source (i.e., 2nd current source I2’ and series connected switch, connecting to node 108) is operative to supply the second current to the gate node of the main switch (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1) for both the first portion of the time duration (i.e., when respective switches are on to adjust respective current of I1’-3’ at node 108 to control main switch S1) and the second portion of the time duration (i.e., when respective switches are off to adjust respective current of I1’-3’ at node 108 to control main switch S1); and
wherein output of the second control signal for the time duration to the gate node is operative to maintain the main switch in an ON-state for the time duration (2nd control signal inverse PWM driving main switch S1 in a pulling down methods, when involving taught 1st-2nd current sources operation, meaning S1 is in a decreased an ON-state for the time duration).
Regarding claim 8, Pavlin teaches (Fig. 1-2; Para 8-12) wherein a magnitude of the first current (i.e., 1st current source I1’ and series connected switch, connecting to node 108) at an end of the first portion of the time duration (i.e., when respective switches are on to adjust respective current of I1’-3’ at node 108 to control main switch S1) is operative to maintain the main switch to an ON-state (2nd control signal inverse PWM driving main switch S1 in a pulling down methods, when involving taught 1st-2nd current sources operation, meaning S1 is in a decreased an ON-state for the time duration).
Regarding claim 13, Pavlin teaches (Fig. 1-2; Para 8-12)
a second input (i.e., 2nd input being output of AND gate and/or cmp1-3) operative to receive feedback tracking the voltage magnitude (Ug or Ua) of the second control signal (2nd control signal inverse PWM driving main switch S1 in a pulling down methods, when involving taught 1st-2nd current sources operation, meaning S1 is in a decreased an ON-state for the time duration);
a comparator (Cmp1-3) operative to compare the received feedback (Ug or Ua) to a threshold level (Cmp1-2 includes use of their own respective threshold); and
a signal generator (i.e., may be anticipated controller providing 1st control signal PWM or AND gate output) operative to terminate (i.e., when respective switches are off to adjust respective current of I1’-3’ at node 108 to control main switch S1) activation of the first current source (i.e., 1st current source I1’ and series connected switch, connecting to node 108) supplying the first current to the main switch (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1) in response to detecting (using Cmp1-3) that the feedback (Ug or Ua) is greater than the threshold level (Cmp1-2 includes use of their own respective threshold).
Regarding claim 14, Pavlin teaches (Fig. 1-2; Para 8-12)
a first switch (106 connected to S1’s source and gate) connected between a gate node of the main switch and a source node of the main switch, the first switch operative to short the gate node of the main switch to the source node of the main switch (106 connected to S1’s source and gate to perform shorting, using pull down operation) during startup of the switch driver circuitry (start of switch driver circuitry being ‘+UH, gnd, I1-3 with respective series connected switches, I1’-3’ with respective series connected switches, inverter/driver that receives PWM’;wherein taught switch driver circuitry converts taught 1st control signal PWM into 2nd control signal inverse PWM to control main switch S1) to prevent activation of the main switch (2nd control signal inverse PWM driving main switch S1 in a pulling down methods, when involving taught 1st-2nd current sources operation, meaning S1 is in a decreased an ON-state for the time duration, targeted to be fully OFF).
Regarding independent claim 18, Pavlin teaches (Fig. 1-2; Para 8-12) a method comprising:
via a first input (1st input to driver is a 1st control signal being PWM to control main switch S1) of switch driver circuitry (switch driver circuitry being ‘+UH, gnd, I1-3 with respective series connected switches, I1’-3’ with respective series connected switches, inverter/driver that receives PWM’; wherein taught switch driver circuitry converts taught 1st control signal PWM into 2nd control signal inverse PWM to control main switch S1), receiving a first control signal (1st control signal PWM) indicating how to control a main switch (main switch S1);
via the switch driver circuitry (switch driver circuitry being ‘+UH, gnd, I1-3 with respective series connected switches, I1’-3’ with respective series connected switches, inverter/driver that receives PWM’; wherein taught switch driver circuitry converts taught 1st control signal PWM into 2nd control signal inverse PWM to control main switch S1), converting the first control signal (1st control signal PWM) into a second control signal (2nd control signal inverse PWM); and
via an output (i.e., an output being other element’s combined operation of ‘cmp1-3, AND gate,’ that drives main switch S1, using level shifted driving/varying/programming/trimming, etc. methods of taught switch driver circuitry) of the switch driver circuitry, outputting the second control signal to the main switch (2nd control signal inverse PWM driving main switch S1), the second control signal including first current (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1) supplied from a first current source (i.e., 1st current source I1’ and series connected switch, connecting to node 108) of the switch driver circuitry to the main switch(main switch S1’s gate), a magnitude of the first current varying (saturation current of I1’-3’ being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1) based on a voltage magnitude of the second control signal (2nd control signal inverse PWM driving main switch S1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 2-4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pavlin (US Pub 2012/0081092).
Regarding claim 2, Pavlin teaches (Fig. 1-2; Para 8-12) the first current source is a switch including an output node operative to output the first current (i.e., 1st current source I1’ and series connected switch, connecting to node 108) to a gate node of the main switch (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1).
However, Pavlin fails to teach the first current source using field effect transistor, its control node being gate node and its output node being source node to output the first current.
However, Pavlin teaches (Fig. 5; Para 52-58) the first current source (320) using field effect transistor (NMOS 526), its control node being gate node (526’s gate) and its output node being source node (526’s source) to output the first current.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pavlin’s apparatus and/or its method to have the first current source use field effect transistor, its control node being gate node and its output node being source node to output the first current, as disclosed by Pavlin, as doing so would have simply provided a specific circuit design choice for the claimed current source adapted to set the level of a current for charging a control terminal of said power transistor, as disclosed by Pavlin (Para 13-26 and abstract).
Regarding claim 3, Pavlin teaches (Fig. 1-2; Para 8-12)
wherein a supply of the first current from the output node of the switch (i.e., 1st current source I1’ and series connected switch, connecting to node 108) to the gate node of the main switch is operative to reduce a magnitude of the first current over time (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1); and
wherein the magnitude of the first current is operative to decrease over time, the first current being saturation current (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1).
However, Pavlin fails to teach the first current source using field effect transistor, its control node being gate node and its output node being source node to output the first current.
However, Pavlin teaches (Fig. 5; Para 52-58) the first current source (320) using field effect transistor (NMOS 526), its control node being gate node (526’s gate) and its output node being source node (526’s source) to output the first current.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pavlin’s apparatus and/or its method to have the first current source use field effect transistor, its control node being gate node and its output node being source node to output the first current, as disclosed by Pavlin, as doing so would have simply provided a specific circuit design choice for the claimed current source adapted to set the level of a current for charging a control terminal of said power transistor, as disclosed by Pavlin (Para 13-26 and abstract).
Regarding claim 4, Pavlin teaches (Fig. 1-2; Para 8-12) wherein the saturation current decreases over time in response to a decrease in a control node-to-output node voltage between a control node of the field effect transistor and the output node of the switch (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1), the decrease occurring in response to an increase in the voltage magnitude of the second control signal over time (2nd control signal inverse PWM driving main switch S1 in a pulling down methods, when involving taught 1st-2nd current sources operation, meaning S1 is in a decreased an ON-state for the time duration).
However, Pavlin fails to teach the first current source using field effect transistor, its control node being gate node and its output node being source node to output the first current.
However, Pavlin teaches (Fig. 5; Para 52-58) the first current source (320) using field effect transistor (NMOS 526), its control node being gate node (526’s gate) and its output node being source node (526’s source) to output the first current.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pavlin’s apparatus and/or its method to have the first current source use field effect transistor, its control node being gate node and its output node being source node to output the first current, as disclosed by Pavlin, as doing so would have simply provided a specific circuit design choice for the claimed current source adapted to set the level of a current for charging a control terminal of said power transistor, as disclosed by Pavlin (Para 13-26 and abstract).
Regarding claims 19, Pavlin teaches (Fig. 1-2; Para 8-12)
wherein the first current source is a switch including an output node (i.e., 1st current source I1’ and series connected switch, connecting to node 108) operative to output the first current to a gate node of the main switch (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1); and
wherein outputting the second control signal to the main switch (2nd control signal inverse PWM driving main switch S1 in a pulling down methods, when involving taught 1st-2nd current sources operation, meaning S1 is in a decreased an ON-state for the time duration) includes supplying the first current from the output node of the switch to the gate node of the main switch, the supply of the first current reducing a magnitude of the first current over time (saturation current of I1’-3’ with respective series connected switches being output at the output node 108 of respective current sources, each being operative to decrease/vary over time in order to minimize Vgate overcharging for main switch S1).
However, Pavlin fails to teach the first current source using field effect transistor, its control node being gate node and its output node being source node to output the first current.
However, Pavlin teaches (Fig. 5; Para 52-58) the first current source (320) using field effect transistor (NMOS 526), its control node being gate node (526’s gate) and its output node being source node (526’s source) to output the first current.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pavlin’s apparatus and/or its method to have the first current source use field effect transistor, its control node being gate node and its output node being source node to output the first current, as disclosed by Pavlin, as doing so would have simply provided a specific circuit design choice for the claimed current source adapted to set the level of a current for charging a control terminal of said power transistor, as disclosed by Pavlin (Para 13-26 and abstract).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Pavlin (US Pub 2012/0081092), in view of Nguyen et al. (“Nguyen”, US Pub 2024/0022161).
Regarding claim 12, Pavlin teaches the main switch (S1), except being fabricated from Gallium Nitride (GaN).
However, Nguyen teaches fabrication from Gallium Nitride (GaN) for required switch(s) (Para 14).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pavlin’s apparatus and/or its method to use fabrication from Gallium Nitride (GaN) for required switch(s), as disclosed by Nguyen, as doing so would have simply provided a specific circuit design choice for the claimed main switch, as such arrangement reduces electrical power losses, while enabling use of a wide range of current and/or voltage slew rates at the gate of the transistor, which reduces or eliminates gate current dependence on gate path resistance and inductance, as compared with constant voltage source gate driver, as taught by Nguyen (Para 2 and abstract).
Allowable Subject Matter
Claims 9-11, 15-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, cited prior art(s) failed to teach, “wherein the first current supplied by the field effect transistor to the gate node of the main switch increases the voltage magnitude of the second control signal supplied to the gate node of the main switch”.
Claims 10-11 are depending from claim 9.
Regarding claim 15, cited prior art(s) failed to teach, “wherein the switch driver circuitry further includes ‘a second field effect transistor operative to convey a control voltage received from a voltage source to a gate input of the first field effect transistor to activate the first field effect transistor (wherein the first current source is the first field effect transistor)”.
Claims 16-17 are depending from claim 15.
Regarding claim 20 cited prior art(s) failed to teach, “wherein the first current source is a first field effect transistor; and via a second field effect transistor of the switch driver circuitry, conveying a control voltage received from a trimmable voltage source to a control input of the first field effect transistor to activate the first field effect transistor; and wherein a magnitude of the control voltage received from the trimmable voltage source is selected to limit the magnitude of the first current supplied by the first current source to a gate node of the main switch”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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Above Fig. 4 is from Kelley et al. (“Kelley”, US Pub 2012/0218011), can be used to rejected, under 35 U.S.C 102(a)(1) Rejection
(a) Regarding independent claim 1, Kelley et al. (“Kelley”, US Pub 2012/0218011) teaches (Fig. 3-11; abstract and Para 53-80) an apparatus (Fig. 4) comprising: a first input (1st input of pulse generator to receive a 1st control signal, which is any one of Vin or VFB, under BRI) operative to receive a first control signal (1st control signal Vin or Vfb, under BRI, driving gate of JFET) indicating how to control a main switch (JFET’s gate); switch driver circuitry (pulse generator that converts taught 1st control signal ‘Vin or Vfb’ into required corresponding 2nd control signal, which is output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate) operative to convert the first control signal (1st control signal ‘Vin or Vfb’) into a second control signal (output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate); and an output (i.e., taught outputs paths 1-3 driven by taught switch driver circuitry) operative to output the second control signal to the main switch (output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate), the second control signal including first current (when any one of switch S1-3 is on, corresponding saturation currents (i.e., iC1-3) being output at the output node of each switch; wherein each switch/transistor S1-3 operates as a current source, when on, using Ohm’s law (I=V/R) for respective path 1-3, to control JET’s gate charge; wherein, each iC1-3 is operative to decrease/increase/vary over time, using the respective resistance values (i.e., of R1-3), located in respective paths 1-3, in order to minimize Vgate overcharging for main switch JFET) supplied from a first current source (when any one of switch S1-3 is on, corresponding saturation currents (i.e., iC1-3) being output at the output node of each switch; wherein each switch/transistor S1-3 operates as a current source, when on, using Ohm’s law (I=V/R) for respective path 1-3, to control JET’s gate charge) of the switch driver circuitry to the main switch (to minimize Vgate overcharging for main switch JFET), a magnitude of the first current varying (wherein, each iC1-3 is operative to decrease/increase/vary over time, using the respective resistance values (i.e., of R1-3), located in respective paths 1-3, in order to minimize Vgate overcharging for main switch JFET) based on a voltage magnitude of the second control signal (output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate).
(b) Regarding independent claim 18, Kelley et al. (“Kelley”, US Pub 2012/0218011) teaches (Fig. 3-11; abstract and Para 53-80) a method (Fig. 4) comprising: via a first input (1st input of pulse generator to receive a 1st control signal, which is any one of Vin or VFB, under BRI) of switch driver circuitry pulse generator that converts taught 1st control signal ‘Vin or Vfb’ into required corresponding 2nd control signal, which is output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate), receiving a first control signal (1st control signal Vin or Vfb, under BRI, driving gate of JFET) indicating how to control a main switch (JFET’s gate); via the switch driver circuitry (pulse generator that converts taught 1st control signal ‘Vin or Vfb’ into required corresponding 2nd control signal, which is output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate), converting the first control signal (1st control signal ‘Vin or Vfb’) into a second control signal (output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate); and via an output (i.e., taught outputs paths 1-3 driven by taught switch driver circuitry) of the switch driver circuitry, outputting the second control signal to the main switch (output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate), the second control signal including first current (when any one of switch S1-3 is on, corresponding saturation currents (i.e., iC1-3) being output at the output node of each switch; wherein each switch/transistor S1-3 operates as a current source, when on, using Ohm’s law (I=V/R) for respective path 1-3, to control JET’s gate charge; wherein, each iC1-3 is operative to decrease/increase/vary over time, using the respective resistance values (i.e., of R1-3), located in respective paths 1-3, in order to minimize Vgate overcharging for main switch JFET) supplied from a first current source (when any one of switch S1-3 is on, corresponding saturation currents (i.e., iC1-3) being output at the output node of each switch; wherein each switch/transistor S1-3 operates as a current source, when on, using Ohm’s law (I=V/R) for respective path 1-3, to control JET’s gate charge) of the switch driver circuitry to the main switch (to minimize Vgate overcharging for main switch JFET), a magnitude of the first current varying (wherein, each iC1-3 is operative to decrease/increase/vary over time, using the respective resistance values (i.e., of R1-3), located in respective paths 1-3, in order to minimize Vgate overcharging for main switch JFET) based on a voltage magnitude of the second control signal (output of the pulse generator ‘PWM’, which selectively choosing output path 1 (V1, PWM, VC2, S1, R2), path 2 (V2, Vin, S2, current limit resistor R1) or path 3 (Vin, INV, VC3, S3, pull-down resistor R3) to drive main switch JFET’s gate).
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
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