DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 26, 33, 37, and 41 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 22-25, 27-30, 32, 34-36, 38, and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, and 10 of U.S. Patent No. 12026550 in view of He, Adachi, Smith, and Das. See table and rejections below.
Instant Application
12026550 Patent
22. (New) A method comprising:
accessing, by one or more processors, sensor data representing a temperature of each of one or more computer chips of a computer system configured to perform one or more cryptographic operations;
determining, by the one or more processors based on the sensor data, that that the temperature of a first computer chip of the one or more computer chips exceeded a threshold temperature; and
responsive to determining that the temperature of the first computer chip has exceeded the threshold temperature, dynamically adjusting, by the one or more processors, a target computing performance of at least the first computer chip, wherein dynamically adjusting the target computing performance of at least the first computer chip comprises:
decreasing the target computing performance of at least the first computer chip by a first level, subsequent to decreasing the target computing performance of at least the first computer chip by the first level, determining that the temperature of at least the first computer chip is less than the threshold temperature, and
responsive to determining that the temperature of at least the first computer chip is less than the threshold temperature,
incrementally increasing the target computing performance of at least the first computer chip by a second level, wherein the first level is greater than the second level.
1. A method comprising:
accessing, by one or more processors, sensor data representing a temperature of one or more computer chips of a computer system configured to perform a cryptographic operation;
determining, by the one or more processors based on the sensor data, that the temperature has exceeded a threshold temperature; and
responsive to determining that the temperature has exceeded the threshold temperature, dynamically adjusting, by the one or more processors, a target computing performance of the one or more computer chips, wherein dynamically adjusting the target computing performance of the one or more computer chips comprises:
decreasing the target computing performance of the one or more computer chips by a first level, wherein decreasing the target computing performance of the one or more computer chips by the first level comprises:
…
determining that the temperature is less than the threshold temperature, responsive to determining that the temperature is less than the threshold temperature, incrementally increasing the target computing performance of the one or more computer chips by a second level, wherein the first level is greater than the second level …
23. (New) The method of claim 22, wherein the sensor data further represents an ambient temperature of the computer system, wherein the target computing performance of at least the first computer chip is dynamically adjusted based on the ambient temperature.
10. The method of claim 1, wherein the sensor data further represents an ambient temperature of the computer system, and wherein the method comprises dynamically adjusting the target computing performance of the one or more computer chips based on the ambient temperature.
29. (New) The method of claim 22, wherein the one or more cryptographic operations comprise mining a cryptocurrency.
2. The method of claim 1, wherein the cryptographic operation comprises mining a cryptocurrency.
As per claim 24, 550 Patent teaches:
The method of claim 23 (see rejection on claim 23).
550 Patent does not expressly teach:
further comprising controlling a cooling mechanism for at least the first computer chip based on the ambient temperature.
However, He discloses:
further comprising controlling a cooling mechanism for at least the first computer chip based on the ambient temperature (He, Abstract).
Both He and 550 Patent pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use He’s method to use ambient temperature because monitoring ambient temperature around computer systems prevents unexpected hardware failure, stops thermal throttling to maintain peak performance, and avoids costly data center or server downtime. It also optimizes cooling and energy costs by ensuring air conditioning systems do not over-cool spaces.
As per claim 25, 550 Patent/He teaches:
The method of claim 24 (see rejection on claim 24).
550 Patent/He does not expressly teach:
wherein controlling the cooling mechanism comprises at least one of: activating one or more fans of the cooling mechanism, or increasing a speed of the one or more fans of the cooling mechanism.
However, Adachi discloses:
wherein controlling the cooling mechanism comprises at least one of: activating one or more fans of the cooling mechanism, or increasing a speed of the one or more fans of the cooling mechanism (Adachi, [0027]).
Both Adachi and 550 Patent/He pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Adachi’s method to power up fans because powering up or running system cooling fans at higher speeds in a computer system provides critical thermal management.
As per claim 27, 550 Patent teaches:
The method of claim 22 (see rejection on claim 22).
550 Patent does not expressly teach:
wherein responsive to determining that the temperature of the first computer chip the temperature has exceeded the threshold temperature: the target computing performance of the first computer chip is dynamically adjusted independently from the target computer performance of one or more other computer chips of the one or more computer chips.
However, Smith discloses:
wherein responsive to determining that the temperature of the first computer chip the temperature has exceeded the threshold temperature: the target computing performance of the first computer chip is dynamically adjusted independently from the target computer performance of one or more other computer chips of the one or more computer chips (Smith, [0027]).
Both Smith and 550 Patent pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Smith’s method to adjust computing performance of the first computer chip because adjusting voltage downward (known as undervolting) reduces processor and component temperatures because lower electrical input directly decreases power consumption and heat generation. Factory default settings often feed hardware more voltage than necessary to ensure stability across varied silicon quality, leaving room for optimization.
As per claim 28, 550 Patent teaches:
The method of claim 22 (see rejection on claim 22).
550 Patent does not expressly teach:
wherein responsive to determining that the temperature of the first computer chip the temperature has exceeded the threshold temperature: the target computing performance of the first computer chip is dynamically adjusted in conjunction with the target computer performance of one or more other computer chips of the one or more computer chips.
However, Smith discloses:
wherein responsive to determining that the temperature of the first computer chip the temperature has exceeded the threshold temperature:
the target computing performance of the first computer chip is dynamically adjusted in conjunction with the target computer performance of one or more other computer chips of the one or more computer chips (Smith, [0064], [0065]—under BRI, in conjunction can be together in one system).
Both Smith and 550 Patent pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Smith’s method to adjust computing performance of the first computer chip because adjusting voltage downward (known as undervolting) reduces processor and component temperatures because lower electrical input directly decreases power consumption and heat generation. Factory default settings often feed hardware more voltage than necessary to ensure stability across varied silicon quality, leaving room for optimization.
As per claim 30, 550 Patent teaches:
The method of claim 22 (see rejection on claim 22).
550 Patent does not expressly teach:
wherein decreasing the target computing performance of at least the first computer chip by the first level comprises at least one of: decreasing a supply voltage of at least the first computer chip by a first voltage value, or decreasing a clock frequency of at least the first computer chip by a first frequency value.
However, Smith discloses:
wherein decreasing the target computing performance of at least the first computer chip by the first level comprises at least one of:
decreasing a supply voltage of at least the first computer chip by a first voltage value, or decreasing a clock frequency of at least the first computer chip by a first frequency value (Smith, [0064]).
Both Smith and 550 Patent pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Smith’s method to decrease voltage or frequency because lowering voltage or frequency reduces electrical power consumption and heat output, thus lowering temperature.
As per claim 32, 550 Patent teaches:
The method of 22 (see rejection on claim 22).
550 Patent does not expressly teach:
further comprising: determining that at least one of: a supply voltage of at least the first computer chip is less than a threshold voltage, or a clock frequency of at least the first computer chip is less than a threshold frequency, and in response, causing at least the first computer chip to transition to an idle state.
However, Das discloses:
further comprising:
determining that at least one of:
a supply voltage of at least the first computer chip is less than a threshold voltage, or
a clock frequency of at least the first computer chip is less than a threshold frequency, and in response, causing at least the first computer chip to transition to an idle state (Das, Abstract—under BRI, an idle state can be a state where DVFS application stops further reduction in supply voltage by getting the warning signal with predefined timing slacks) .
Both Das and 550 Patent pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Das’s method to idle DVFS because a warning flip-flop (FF) based detection circuit uses a frequency-independent warning window to monitor delayed data before errors happen. It helps stop voltage reduction in dynamic voltage and frequency scaling (DVFS) systems by flagging early timing violations
As per claim 34, see rejection on claim 22.
As per claim 35, see rejection on claim 23.
As per claim 36, see rejections on claim 24 and 25.
As per claim 38, see rejections on claims 27 and 28.
As per claim 40, see rejection on claim 32.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 22, 27-31, 34, and 38-39 are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al (US 2022/0287876) (hereinafter Smith) in view of Applicant Admitted Prior Art (Background, Spec) (hereinafter AAPA) further in view of Mays et al (US 7646836) (hereinafter Mays).
As per claim 22, Smith teaches:
A method comprising:
accessing, by one or more processors, sensor data representing a temperature of each of one or more components (Smith, [0064]—under BRI, sensor data can be temperature data from the bottom-side temperature sensor);
determining, by the one or more processors based on the sensor data, that that the temperature of a first component of the one or more components exceeded a threshold temperature (Smith, [0064]-- the temperature of a first component of the one or more components exceeded a threshold temperature can be pad temperature close/near the high thermal pad temperature limit) ; and
responsive to determining that the temperature of the first component has exceeded the threshold temperature, dynamically adjusting, by the one or more processors, a target computing performance of at least the first computer chip Smith, [0064]), wherein dynamically adjusting the target computing performance of at least the first component comprises:
decreasing the target computing performance of at least the 1st component by a first level (Smith, [0064]),
subsequent to decreasing the target computing performance of at least the first component by the first level, determining that the temperature of at least the first component is less than the threshold temperature (Smith, [0064]), and
responsive to determining that the temperature of at least the first component is less than the threshold temperature, incrementally increasing the target computing performance of at least the first component by a second level (Smith, [0062]—under BRI, increasing the target computing performance of at least the first computer chip by a second level can be increasing . . . the DC voltage supplied to the TED 125 to move the thermal pad temperature toward the target pad temperature);
Smith does not expressly teach:
wherein the components are computer chips of a computer system configured to perform one or more cryptographic operations;
wherein the 1st component is a first computer chip;
wherein the first level is greater than the second level.
However, AAPA discloses:
wherein the components are computer chips of a computer system configured to perform one or more cryptographic operations (AAPA, [0003]);
wherein the 1st component is a first computer chip (AAPA, [0003]);
Both AAPA and Smith pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use AAPA’s method to use computer chips of a computer system configured to perform one or more cryptographic operations because implementing cryptographic operations directly on a dedicated hardware chip (such as a secure element, TPM, or crypto-coprocessor) provides major benefits, including enhanced physical security, isolated key storage, high-speed processing acceleration, and reliable protection against side-channel and invasive cyberattacks.
Smith/AAPA does not expressly teach:
wherein the first level is greater than the second level.
However, Mays discloses:
wherein the first level is greater than the second level (Mays, col 6, ll 35-40—coarse>fine).
Both Mays and Smith/AAPA pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Mays’ method to use fine and coarse level because using coarse and fine frequency steps in CPU tuning or clock generation provides a dual-speed adjustment method. Coarse steps allow fast navigation across large frequency ranges, while fine steps permit precise tuning to lock exact targets, balance performance, and minimize power or jitter.
As per claim 27, Smith/AAPA/Mays teaches:
The method of claim 22 (see rejection on claim 22), wherein responsive to determining that the temperature of the first computer chip the temperature has exceeded the threshold temperature:
the target computing performance of the first computer chip is dynamically adjusted independently from the target computer performance of one or more other computer chips of the one or more computer chips (Smith, [0064]).
As per claim 28, Smith/AAPA/Mays teaches:
The method of claim 22, wherein responsive to determining that the temperature of the first computer chip the temperature has exceeded the threshold temperature:
the target computing performance of the first computer chip is dynamically adjusted in conjunction with the target computer performance of one or more other computer chips of the one or more computer chips (Smith, [0064], [0065]—under BRI, in conjunction can be together in one system).
As per claim 29, Smith/AAPA/Mays teaches:
The method of claim 22 (see rejection on claim 22), wherein the one or more cryptographic operations comprise mining a cryptocurrency (AAPA, [0003]).
As per claim 30, Smith/AAPA/Mays teaches:
The method of claim 22 (see rejection on claim 22), wherein decreasing the target computing performance of at least the first computer chip by the first level comprises at least one of:
decreasing a supply voltage of at least the first computer chip by a first voltage value, or decreasing a clock frequency of at least the first computer chip by a first frequency value (Smith, [0064]).
As per claim 31, Smith/AAPA/Mays teaches:
The method of 30 (See rejection on claim 30), wherein increasing the target computing performance of at least the first computer chip by the second level comprises at least one of:
increasing the supply voltage of at least the first computer chip by a second voltage value, wherein the first voltage value is greater than the second voltage value, or increasing the clock frequency of at least the first computer chip by a second frequency value, wherein the first frequency value is greater than the second frequency value (Smith, [0063]).
As per claim 34, see rejection on claim 22.
As per claim 38, see rejection on claims 27 and 28.
As per claim 39, see rejection on claims 30 and 31.
Claims 23-24, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Smith/AAPA/Mays as applied above, and further in view of He et al (US 11662792 ) (hereinafter He).
As per claim 23. Smith/AAPA/Mays teaches:
The method of claim 22 (See rejection on claim 22) , wherein the sensor data further represents a temperature (Smith, [0064]), wherein the target computing performance of at least the first computer chip is dynamically adjusted based on the temperature (Smith, [0064]).
Smith/AAPA/Mays does not expressly teach:
wherein the temperature is an ambient temperature of the computer system;
However, He discloses:
wherein the temperature is an ambient temperature of the computer system (He, Abstract);
Both He and Smith/AAPA/Mays pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use He’s method to use ambient temperature because monitoring ambient temperature around computer systems prevents unexpected hardware failure, stops thermal throttling to maintain peak performance, and avoids costly data center or server downtime. It also optimizes cooling and energy costs by ensuring air conditioning systems do not over-cool spaces.
As per claim 24, Smith/AAPA/Mays/He teaches:
The method of claim 23 (see rejection on claim 23), further comprising controlling a cooling mechanism for at least the first computer chip based on the ambient temperature (He, Abstract).
As per claim 35, see rejection on claim 23.
Claims 25 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Smith/AAPA/Mays/He as applied above, and further in view of Adachi et al (US 2009/0292404) (hereinafter Adachi).
As per claim 25, Smith/AAPA/Mays/He teaches:
The method of claim 24 (see rejection on claim 24).
Smith/AAPA/Mays/He does not expressly teach:
wherein controlling the cooling mechanism comprises at least one of:
activating one or more fans of the cooling mechanism, or increasing a speed of the one or more fans of the cooling mechanism.
However, Adachi discloses:
wherein controlling the cooling mechanism comprises at least one of:
activating one or more fans of the cooling mechanism, or increasing a speed of the one or more fans of the cooling mechanism (Adachi, [0027]).
Both Adachi and Smith/AAPA/Mays/He pertain to the art of thermal management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Adachi’s method to power up fans because powering up or running system cooling fans at higher speeds in a computer system provides critical thermal management.
As per claim 36, see claims 24 and 25.
Claims 32 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Smith/AAPA/Mays as applied above, and further in view of Das et al (Das, Bishnu Prasad, and Hidetoshi Onodera. "Frequency-independent warning detection sequential for dynamic voltage and frequency scaling in ASICs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22.12 (2014): 2535-2548) (hereinafter Das).
As per claim 32, Smith/AAPA/Mays teaches:
The method 22 (see rejection on claim 22).
Smith/AAPA/Mays does not expressly teach:
further comprising:
determining that at least one of:
a supply voltage of at least the first computer chip is less than a threshold voltage, or a clock frequency of at least the first computer chip is less than a threshold frequency, and in response, causing at least the first computer chip to transition to an idle state.
However, Das discloses:
further comprising:
determining that at least one of:
a supply voltage of at least the first computer chip is less than a threshold voltage, or a clock frequency of at least the first computer chip is less than a threshold frequency, and in response, causing at least the first computer chip to transition to an idle state (Das, Abstract—under BRI, an idle state can be a state where DVFS application stops further reduction in supply voltage by getting the warning signal with predefined timing slacks) .
Both Das and Smith/AAPA/Mays pertain to the art of power management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Das’s method to idle DVFS because a warning flip-flop (FF) based detection circuit uses a frequency-independent warning window to monitor delayed data before errors happen. It helps stop voltage reduction in dynamic voltage and frequency scaling (DVFS) systems by flagging early timing violations
As per claim 40, see rejection on claim 32.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2014/0347137 teaches a method of fine and course tuning frequency.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLIE SUN/Primary Examiner, Art Unit 2198
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