DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on June 28th, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election without traverse of Group I, Species A, including Claims 1-16 in the reply filed on June 29th, 2026 is acknowledged.
The requirement is made FINAL, claims 1-16 are being examined on their merits and all non-elected claims (i.e. claims 17-20) are withdrawn from consideration at this time.
Specification
The following guidelines illustrate the preferred layout for the specification of a utility application. These guidelines are suggested for the applicant’s use.
Arrangement of the Specification
As provided in 37 CFR 1.77(b), the specification of a utility application should include the following sections in order. Each of the lettered items should appear in upper case, without underlining or bold type, as a section heading. If no text follows the section heading, the phrase “Not Applicable” should follow the section heading:
(a) TITLE OF THE INVENTION.
(b) CROSS-REFERENCE TO RELATED APPLICATIONS.
(c) STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT.
(d) THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT.
(e) INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A READ-ONLY OPTICAL DISC, AS A TEXT FILE OR AN XML FILE VIA THE PATENT ELECTRONIC SYSTEM.
(f) STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINT INVENTOR.
(g) BACKGROUND OF THE INVENTION.
(1) Field of the Invention.
(2) Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98.
(h) BRIEF SUMMARY OF THE INVENTION.
(i) BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S).
(j) DETAILED DESCRIPTION OF THE INVENTION.
(k) CLAIM OR CLAIMS (commencing on a separate sheet).
(l) ABSTRACT OF THE DISCLOSURE (commencing on a separate sheet).
(m) SEQUENCE LISTING. (See MPEP § 2422.03 and 37 CFR 1.821 - 1.825). A “Sequence Listing” is required on paper if the application discloses a nucleotide or amino acid sequence as defined in 37 CFR 1.821(a) and if the required “Sequence Listing” is not submitted as an electronic document either on read-only optical disc or as a text file via the patent electronic system.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-9, and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US20230187551A1).
Regarding claim 1;
Cheng et al. teaches a stacked field-effect transistor (FET) device (e.g. Fig. 1 ref 100, Detailed description [0040] “…FIG. 1 is schematic cross-sectional side view (X-Z plane) of a semiconductor integrated circuit device 100 comprising a stacked complementary transistor structure (e.g., stacked complementary FET structure)…”) comprising: a lower FET comprising lower channel layers and a lower gate material that is between the lower channel layers (e.g. Fig .1 ref 101,112,114,180; Detailed description [0040] “…a semiconductor integrated circuit device 100 comprising a stacked complementary transistor structure (e.g., stacked complementary FET structure) comprising a first transistor 101 (e.g., a first FET device)…”, [0041] “…the first transistor 101 comprises a nanosheet FET device comprising a plurality of active nanosheet channel layers 112 and 114…”, [0042] “the first and second transistors 101 and 102 comprise a common gate structure which comprises gate sidewall spacers 134 and 136, and a metal gate 180. In some embodiments, the metal gate 180 comprises a high-k metal gate (HKMG) structure… The metal gate 180 encapsulates the portions of the active nanosheet channel layers 112, 114, 122, and 124, which define a gate length (LG) of the first and second transistors 101 and 102…”); an upper FET that is on the lower FET, the upper FET comprising upper channel layers and an upper gate material that is between the upper channel layers (e.g. Fig .1 ref 102,122,124,180; Detailed description [0040] “…a semiconductor integrated circuit device 100 comprising a stacked complementary transistor structure (e.g., stacked complementary FET structure)…a second transistor 102 (e.g., a second FET device) disposed over the first transistor 101…”, [0041] “…The second transistor 102 comprises a nanosheet FET device comprising a plurality of active nanosheet channel layers 122 and 124…”,[0042] “the first and second transistors 101 and 102 comprise a common gate structure which comprises gate sidewall spacers 134 and 136, and a metal gate 180. In some embodiments, the metal gate 180 comprises a high-k metal gate (HKMG) structure… The metal gate 180 encapsulates the portions of the active nanosheet channel layers 112, 114, 122, and 124, which define a gate length (LG) of the first and second transistors 101 and 102…”); and an insulating layer that is between the lower gate material and the upper gate material and not in a region in which the lower channel layers are overlapped by the upper channel layers (e.g. Fig. 1 ref 175, Detailed description [0043] “The semiconductor integrated circuit device 100 further comprises…a first insulating layer 175 (or first interlayer dielectric (ILD) layer)…”).
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Regarding claim 2;
Cheng et al. further teaches in figure 1 that the insulating layer is in contact with a lower surface of the upper gate material and an upper surface of the lower gate material (e.g. see examiner markup).
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Regarding claim 3;
Cheng et al. further teaches in figure 1 that the insulating layer does not overlap the lower channel layers in a vertical direction that is perpendicular to the upper surface of the lower gate material.
Regarding claim 4;
Cheng et al. further teaches the stacked FET device of claim 1 further comprising an isolation region that separates the lower channel layers from the upper channel layers (e.g. Fig. 1 ref 150, detailed description [0042] “The first and second transistors 101 and 102 are isolated by a dielectric isolation layer 150.”, [0053] “… the sacrificial nanosheet layer 116 is subsequently replaced with a dielectric material to form the dielectric isolation layer 150 between the first and second transistors 101 and 102.”), wherein a sidewall of the insulating layer is on a sidewall of the isolation region (e.g. see examiner markup).
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Regarding claim 5;
Cheng et al. further teaches that the insulating layer comprises an etch-stop layer (e.g. Fig. 1 ref 170) that is thinner than the isolation region in a vertical direction that is parallel to the sidewall of the isolation region (e.g. see examiner markup).
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Regarding claim 8;
Cheng et al. further teaches the stacked FET device of claims 1 and 4 wherein the insulating layer is a first insulating layer (e.g. Fig. 1 ref 175, Detailed description [0043] “The semiconductor integrated circuit device 100 further comprises…a first insulating layer 175 (or first interlayer dielectric (ILD) layer)…”), and wherein the stacked FET device further comprises a second insulating layer (e.g. Fig. 1 ref 170) that is between the first insulating layer and the isolation region (e.g. see examiner markup).
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Regarding claim 9;
Cheng et al. further teaches in figure 1 that the second insulating layer comprises: a first sidewall that is in contact with the sidewall of the isolation region; and a second sidewall that is in contact with the sidewall of the first insulating layer (e.g. see examiner markup).
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Regarding claim 13;
Cheng et al. further teaches in figure 1 that the second insulating layer is thinner than the isolation region in a vertical direction that is parallel to the sidewall of the isolation region (e.g. see examiner markup).
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Regarding claim 14;
Cheng et al. further teaches in figure 1 that the first insulating layer is wider, in a lateral direction that is perpendicular to the sidewall of the isolation region, than the second insulating layer (e.g. see examiner markup).
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Regarding claim 15;
Cheng et al. teaches A stacked field-effect transistor (FET) device (e.g. Fig. 1 ref 100, Detailed description [0040] “…FIG. 1 is schematic cross-sectional side view (X-Z plane) of a semiconductor integrated circuit device 100 comprising a stacked complementary transistor structure (e.g., stacked complementary FET structure)…”) comprising: a lower FET comprising lower channel layers and a lower gate material that is between the lower channel layers (e.g. Fig .1 ref 101,112,114,180; Detailed description [0040] “…a semiconductor integrated circuit device 100 comprising a stacked complementary transistor structure (e.g., stacked complementary FET structure) comprising a first transistor 101 (e.g., a first FET device)…”, [0041] “…the first transistor 101 comprises a nanosheet FET device comprising a plurality of active nanosheet channel layers 112 and 114…”, [0042] “the first and second transistors 101 and 102 comprise a common gate structure which comprises gate sidewall spacers 134 and 136, and a metal gate 180. In some embodiments, the metal gate 180 comprises a high-k metal gate (HKMG) structure… The metal gate 180 encapsulates the portions of the active nanosheet channel layers 112, 114, 122, and 124, which define a gate length (LG) of the first and second transistors 101 and 102…”); an upper FET that is on the lower FET, the upper FET comprising upper channel layers and an upper gate material that is between the upper channel layers (e.g. Fig .1 ref 102,122,124,180; Detailed description [0040] “…a semiconductor integrated circuit device 100 comprising a stacked complementary transistor structure (e.g., stacked complementary FET structure)…a second transistor 102 (e.g., a second FET device) disposed over the first transistor 101…”, [0041] “…The second transistor 102 comprises a nanosheet FET device comprising a plurality of active nanosheet channel layers 122 and 124…”,[0042] “the first and second transistors 101 and 102 comprise a common gate structure which comprises gate sidewall spacers 134 and 136, and a metal gate 180. In some embodiments, the metal gate 180 comprises a high-k metal gate (HKMG) structure… The metal gate 180 encapsulates the portions of the active nanosheet channel layers 112, 114, 122, and 124, which define a gate length (LG) of the first and second transistors 101 and 102…”); an isolation region that separates the lower channel layers from the upper channel layers (e.g. Fig. 1 ref 150, detailed description [0042] “The first and second transistors 101 and 102 are isolated by a dielectric isolation layer 150.”, [0053] “… the sacrificial nanosheet layer 116 is subsequently replaced with a dielectric material to form the dielectric isolation layer 150 between the first and second transistors 101 and 102.”); and an insulating layer that separates the lower gate material from the upper gate material and is adjacent a sidewall of the isolation region (Fig. 1 ref 170).
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Regarding claim 16;
Cheng et al. further teaches that the insulating layer comprises silicon nitride (e.g. Fig. 1 ref 170, Detailed description [0083] “…the dielectric liner layer 170 is formed of dielectric material such as, e.g., SiOC, SiCN, SiN, SiBCN…”) and is thinner than the isolation region in a vertical direction that is parallel to the sidewall of the isolation region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6-7, and 10-12 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20230187551A1) for the following reasons:
Regarding claim 6;
Cheng et al. teaches the stacked FET device of claims 1 and 4 wherein the insulating layer and the isolation region comprise insulating materials (e.g. Detailed description [0072] “The dielectric isolation layer 150 is then formed by depositing a conformal layer of dielectric material”, [0086] “The first ILD layer 175 may comprise any suitable insulating/dielectric material…”).
Cheng et al. is silent to the insulating layer and the isolation region comprising different insulating materials from each other as claimed.
However, at the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the insulating layer and the isolation region taught in Cheng et al. from different insulating materials selected from a list of commonly utilized and suitable insulating/dielectric material, because the insulating layer taught in Cheng et al. is used to encapsulate the stacked FET device (e.g. Detailed description [0084]-[0086]) and the isolation region taught in Cheng et al. is used to electrically isolate the upper and lower FET device’s channel layers from one another (e.g. Detailed description [0042] “The first and second transistors 101 and 102 are isolated by a dielectric isolation layer 150.”). It has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding claim 7;
Cheng et al. further teaches that the insulating layer comprises silicon nitride (e.g. Detailed description [0086] “The first ILD layer 175 may comprise any suitable insulating/dielectric material that is commonly utilized in semiconductor process technologies including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, SiCOH, SiCH, SiCNH, or other types of silicon-based low-k dielectrics (e.g., k less than about 4.0), porous dielectrics, known ULK (ultra-low-k) dielectric materials (with k less than about 2.5), or any suitable combination of those materials.”).
Regarding claim 10;
Cheng et al. teaches of claims 1,4, and 8 wherein the second insulating layer comprises an insulating material (e.g. Detailed description [0083] “…the dielectric liner layer 170 is formed of dielectric material such as, e.g., SiOC, SiCN, SiN, SiBCN, which has etch selectivity to the dielectric materials of the gate capping layer 132 and the gate sidewall spacer 134.”).
Cheng et al. is silent to the second insulating layer comprising an insulating material different from that of the first insulating layer and different from that of the isolation region.as claimed.
However, at the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the second insulating layer taught in Cheng et al. from a different insulating material from the first insulating layer and the isolation region, because the second insulating layer serves a different purpose from the first insulating layer and the isolation region (e.g. Detailed description [0082] “The dielectric liner layer 170 is formed to protect the first and second source/drain elements 160-1 and 160-2 of the first transistor 101 during a subsequent epitaxial process for growing the first and second source/drain elements 162-1 and 162-2 of the second transistor 102.”). It has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding claim 11;
Cheng et al. further teaches that the insulating material of the second insulating layer comprises a dielectric material and is free of carbon and boron (e.g. Detailed description [0083] “the dielectric liner layer 170 is formed of dielectric material such as, e.g., SiOC, SiCN, SiN, SiBCN, which has etch selectivity to the dielectric materials of the gate capping layer 132 and the gate sidewall spacer 134.”), and wherein the first insulating layer comprises an insulating/dielectric material and is free of carbon, boron, and oxygen (e.g. Detailed description [0086] “The first ILD layer 175 may comprise any suitable insulating/dielectric material that is commonly utilized in semiconductor process technologies including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, SiCOH, SiCH, SiCNH, or other types of silicon-based low-k dielectrics (e.g., k less than about 4.0), porous dielectrics, known ULK (ultra-low-k) dielectric materials (with k less than about 2.5), or any suitable combination of those materials.”).
Cheng et al. is silent to the insulating material of the second insulating layer being an oxide, and the first insulating layer comprising Nitrogen as claimed.
However, at the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the insulating material of the second insulating layer taught in Cheng et al. of an oxide (e.g. SiOx. a known electrically insulative material in the art) because the second insulating layer fulfills the purpose of electrically insulating the source/drain regions of the lower FET device from the source/drain regions of the upper FET device (e.g. Detailed description [0082] “The dielectric liner layer 170 is formed to protect the first and second source/drain elements 160-1 and 160-2 of the first transistor 101 during a subsequent epitaxial process for growing the first and second source/drain elements 162-1 and 162-2 of the second transistor 102.”) and to form the first insulating layer taught in Cheng et al. from Nitrogen (e.g. SixNy, a known electrical passivation material) because the first insulating layer fulfills the purpose of encapsulating/enclosing the upper and lower FET devices (e.g. e.g. Detailed description [0084]-[0086]). It has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding claim 12;
Cheng et al. further teaches that the isolation region comprises a dielectric material (e.g. Detailed description [0072] “The dielectric isolation layer 150 is then formed by depositing a conformal layer of dielectric material, such as silicon nitride, to fill the space between the first and second nanosheet channel structures 110-1 and 120-1, followed by a etch-back process to remove the overburden dielectric material.”).
Cheng et al. is silent to dielectric material which forms the isolation region being Silicon Boron Carbonitride (hereinafter referenced as SiBCN) as claimed.
However, at the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the isolation region taught in Cheng et al. from SiBCN, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use (e.g. electrically isolating the upper and lower FET devices from one another) as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chung et al. (US20220037497A1) teaches a stacked GAA transistor device
O’Brien et al. (US20230113614A1) teaches a stacked FET device having CMOS functionality and an amorphous Boron Nitride isolation/break region
Xie et al. (US11069684B1) teaches a stacked FET device wherein the upper and lower FET devices are isolated from one another by an air gap region
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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