DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to amendment filed 1/21/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 13-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Raheja et al. (US 2021/0191737 A1, hereinafter Raheja) in view of Trika (US 2019/0004947 A1).
Regarding claim 1, Raheja discloses a device as shown in figure 1, comprising: a host processor (figure 1, 126); a memory (figure 1, 110-116); and a memory physical layer (figure 1, 118-124) configured to enter an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer ([0025]-[0029], only selected physical layer memory channel interfaces are allowed to operate in a low power state and corresponding memories are in self-refresh mode while power rails to other physical layer memory channel interfaces are shut off and corresponding memories are completely shut off, i.e., enter an enhanced low power state). Raheja differs from the claimed invention in not discloses the host processor including one or more caches and a power supply is disconnected from a portion of the memory physical layer during a phase in which memory requests are serviced from the one or more caches rather than the memory. However, Trika teaches a host device (figure 1, 102) including a cache memory circuitry (figure 1, 112 and [0015], Host device 102 includes a host processor circuitry 110, a cache memory circuitry 112, a host memory circuitry 114) and a Shutdown command configured to cause the storage device 104 to write temporary data stored in volatile memory circuitry, read as cache, to nonvolatile memory circuitry, read as memory ([0030] and [0034]) such that a power supply is disconnected from a portion of the memory physical layer, i.e., shut down the memory device during a phase in which memory requests are serviced from the one or more caches rather than the memory, i.e., during a subsequent access from the cache. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Raheja in view of Trika, in order to reduce power consumption.
Regarding claim 2, Raheja discloses that the memory physical layer is configured to enter the enhanced low power state responsive to no memory requests being serviced by the memory and no memory requests being enqueued for servicing by the memory ([0029], the physical layer interface power control logic sends the power control information through a southbridge circuit to the switches to shut off power to the memories during the sleep state responsive to no self refresh state during system sleep state).
Regarding claims 3-4, Raheja discloses that the memory physical layer is further configured to exit the enhanced low power state responsive to at least one memory request being serviced by the memory, wherein the memory physical layer is configured to exit the enhanced low power state responsive to at least one memory request being enqueued for servicing by the memory ([0044], the operating system detects a wakeup event that causes the system to wake including responsive to at least one memory request being serviced by the memory or responsive to at least one memory request being enqueued for servicing by the memory).
Regarding claim 5, Raheja discloses that the power supply is disconnected from one or more input/output (I/O) interfaces of the memory physical layer while the memory physical layer operates in the enhanced low power state, thereby causing the memory to operate in a self-refresh mode ([0029], different power rails are used for each physical layer memory channel interface or groups of interfaces as needed so that desired interfaces can be turned off while others are kept on when attached memory is in self refresh mode).
Regarding claim 13, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 14, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 15, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 17, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 18, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 19, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Claims 6, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Raheja et al. (US 2021/0191737 A1, hereinafter Raheja) in view of Trika (US 2019/0004947 A1), as applied in claims above, and further in view of Lee et al. (US 2010/00275037 A1, hereinafter Lee).
Regarding claim 6, the combination of Raheja and Trika differs from the claimed invention in not specifically teaching that the memory physical layer includes registers storing a current state of data within the memory physical layer, and the power supply is connected to the registers while the memory physical layer operates in the enhanced low power state. However, Lee teaches that the memory physical layer (figure 4, 148) includes registers (figure 4, 188) storing a current state of data within the memory physical layer ([0067], data words are stored in elastic buffer and then sent to low-power link layer as 8-bit data and one data/command bit), and the power supply is connected to the registers while the memory physical layer operates in the enhanced low power state ([0065]-[0066], sync pattern detector in low-power physical layer examines the received data and signals when a sync pattern is detected and the power down mode is active) in order to reduce power consumption for low-power devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Raheja and Trika in having that the memory physical layer includes registers storing a current state of data within the memory physical layer, and the power supply is connected to the registers while the memory physical layer operates in the enhanced low power state, as per teaching of Lee, in order to reduce power consumption for low-power devices.
Regarding claim 16, the limitations of the claim are rejected as the same reasons as set forth in claim 6.
Regarding claim 20, the limitations of the claim are rejected as the same reasons as set forth in claim 6.
Allowable Subject Matter
Claims 7-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Paul et al. (US 2025/0037750 A1) discloses a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer (abstract).
Jain et al. (US 2015/0006924 A1) discloses to adjust operating point of the memory physical layer interface based on the memory transaction bandwidth may lead to lower power consumption and/or improved CPU/GPU performance (abstract and figure 4).
Huffman et al. (US 2009/0327773 A1) discloses a host processor and a storage device include link power management based on serial advanced technology attachment (SATA), that reduces power in idle SATA conditions and limits the power consumption of the interface, thus achieving power savings function (abstract).
Branover et al. (US 2011/0264934 A1) discloses a method for powering down a physical layer of a memory interface in a memory controller, so that entry into the low power state reduces operating voltage and a clock signal provided to the memory controller and a memory is inhibited (abstract).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/ Primary Examiner, Art Unit 2133