DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 23, 2026, has been entered.
Response to Amendment
This Office action is in response to Applicant’s amendment filed on July 23, 2026, claims 1-17 and 21-23 are pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 13-15, 17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Raheja et al. (US 2021/0191737 A1, hereinafter Raheja) in view of Agarwal et al. (US 2022/0391132 A1, hereinafter Agarwal).
Regarding claim 1, Raheja discloses a device as shown in figure 1, comprising: a host processor (figure 1, 126); a memory (figure 1, 110-116); and a memory physical layer (figure 1, 118-124) configured to enter an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer ([0025]-[0029], only selected physical layer memory channel interfaces are allowed to operate in a low power state and corresponding memories are in self-refresh mode while power rails to other physical layer memory channel interfaces are shut off and corresponding memories are completely shut off, i.e., enter an enhanced low power state). Raheja differs from the claimed invention in not disclosing the host processor including one or more caches and a memory physical layer configured to enter an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer during a phase in which memory requests are serviced from one or more caches rather than the memory. However, Agarwal teaches a host device (figure 3, 300) including one or more caches (figure 3, host memory buffer 340 and [0053], some or all of the memory 340 in the host 300 is used by the data storage device 100 as an extension of its memory) and the host 300 communicates to the data storage device 100 if any region of the host memory buffer 340 will be powered off or on during a low-power state, and the host memory buffer 340 can be used efficiently by either having power islanding in the host memory buffer 340 along with efficient space utilization while keeping the amount of flushes minimal or, in absence of host-memory-buffer power islanding, providing a cached SRAM to minimize entry/exit latencies and flushes ([0055] and [0057], i.e., a power supply is disconnected from a portion of the memory physical layer and shut down the memory device during a phase in which memory requests are serviced from the one or more caches rather than the memory due to a specific area in the host memory buffer that will be powered on during a low-power state). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Raheja in having the host processor including one or more caches and a memory physical layer configured to enter an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer during a phase in which memory requests are serviced from the one or more caches rather than the memory, as per teaching of Agarwal, in order to to maximize device space utilization along with minimizing latencies.
Regarding claim 2, Raheja discloses that the memory physical layer is configured to enter the enhanced low power state responsive to no memory requests being serviced by the memory and no memory requests being enqueued for servicing by the memory ([0029], the physical layer interface power control logic sends the power control information through a southbridge circuit to the switches to shut off power to the memories during the sleep state responsive to no self-refresh state during system sleep state).
Regarding claims 3-4, Raheja discloses that the memory physical layer is further configured to exit the enhanced low power state responsive to at least one memory request being serviced by the memory, wherein the memory physical layer is configured to exit the enhanced low power state responsive to at least one memory request being enqueued for servicing by the memory ([0044], the operating system detects a wakeup event that causes the system to wake including responsive to at least one memory request being serviced by the memory or responsive to at least one memory request being enqueued for servicing by the memory).
Regarding claim 5, Raheja discloses that the power supply is disconnected from one or more input/output (I/O) interfaces of the memory physical layer while the memory physical layer operates in the enhanced low power state, thereby causing the memory to operate in a self-refresh mode ([0029], different power rails are used for each physical layer memory channel interface or groups of interfaces as needed so that desired interfaces can be turned off while others are kept on when attached memory is in self-refresh mode).
Regarding claim 13, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 14, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 15, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 17, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 21, Raheja differs from the claimed invention in not specifically teaching that the memory requests continue to be serviced from the one or more caches while the memory physical layer operates in the enhanced low power state. However, Agarwal teaches any specific area in the host memory buffer 340 that will be powered off or on during a low-power state (figure 5 and [0057], i.e., the specific area in the host memory buffer that will be powered on during a low-power state is continued to be serviced while the memory physical layer operates in the enhanced low power state) in order to minimize latencies. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Raheja in having that the memory requests continue to be serviced from the one or more caches while the memory physical layer operates in the enhanced low power state, as per teaching of Agarwal, in order to minimize latencies.
Claims 6, 16 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Raheja et al. (US 2021/0191737 A1, hereinafter Raheja) in view of Agarwal et al. (US 2022/0391132 A1, hereinafter Agarwal), as applied in claims above, and further in view of Lee et al. (US 2010/0275037 A1, hereinafter Lee).
Regarding claim 6, the combination of Raheja and Agarwal differs from the claimed invention in not specifically teaching that the memory physical layer includes registers storing a current state of data within the memory physical layer, and the power supply is connected to the registers while the memory physical layer operates in the enhanced low power state. However, Lee teaches that the memory physical layer (figure 4, 148) includes registers (figure 4, 188) storing a current state of data within the memory physical layer ([0067], data words are stored in elastic buffer and then sent to low-power link layer as 8-bit data and one data/command bit), and the power supply is connected to the registers while the memory physical layer operates in the enhanced low power state ([0065]-[0066], sync pattern detector in low-power physical layer examines the received data and signals when a sync pattern is detected and the power down mode is active) in order to reduce power consumption for low-power devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Raheja and Agarwal in having that the memory physical layer includes registers storing a current state of data within the memory physical layer, and the power supply is connected to the registers while the memory physical layer operates in the enhanced low power state, as per teaching of Lee, in order to reduce power consumption for low-power devices.
Regarding claim 16, Agarwal teaches the power supply is connected to the registers while the memory physical layer operates in the enhanced low power state, a first portion of the registers is powered up and a second portion of the registers is powered down (figure 5 and ([0057]). The combination of Raheja and Agarwal differs from the claimed invention in not specifically teaching that the memory physical layer includes registers storing a current state of data within the memory physical layer registers. However, Lee teaches that the memory physical layer (figure 4, 148) includes registers (figure 4, 188) storing a current state of data within the memory physical layer ([0067], data words are stored in elastic buffer and then sent to low-power link layer as 8-bit data and one data/command bit). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Raheja and Agarwal in having that the memory physical layer includes registers storing a current state of data within the memory physical layer, as per teaching of Lee, in order to reduce power consumption for low-power devices.
Regarding claim 23, Agarwal teaches specific area in the host memory buffer 340 that will be powered off or on during a low-power state (figure 5 and [0057]) such that a portion of memory spaces in host memory buffer are connected to a power supply and another portion of memory spaces in host memory buffer are disconnected from the power supply. The combination of Raheja and Agarwal differs from the claimed invention in not specifically teaching that the memory physical layer includes registers wherein the memory physical layer includes registers. However, Lee teaches that the memory physical layer (figure 4, 148) includes registers (figure 4, 188) storing a current state of data within the memory physical layer ([0067], data words are stored in elastic buffer and then sent to low-power link layer as 8-bit data and one data/command bit). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Raheja and Agarwal in having that the memory physical layer includes registers as per teaching of Lee, in order to reduce power consumption for low-power devices.
Allowable Subject Matter
Claims 7-12 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-17 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Paul et al. (US 2025/0037750 A1) discloses methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer (abstract and figure 4).
Niimura (US 9,813,576 B2) discloses a storage unit operating in one of a first state where a memory keeping process to keep information stored in the storage unit is executed in response to accepting an outside instruction, and a second state in which the memory keeping process is executed without accepting an outside instruction (abstract and figure 3).
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/ZHUO H LI/ Primary Examiner, Art Unit 2133
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