DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 2, 4, 5, 9, 11 and 12 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 (similarly claim 9) recite: “the virtualized guest-timer is circuitry”. The examiner is unclear how a virtualized guest-timer is circuitry(hardware). The term virtualized would be interpreted as a logical (i.e. software) representation of a physical hardware.
Claim 4 (similarly claim 11) recite: “virtual machine support”. The examiner is unclear of the metes-and-bounds of the term support.
Claims 5 and 12 are rejected based on rejection of its corresponding dependent claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-13 and 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsumoto (Pub 20170286152).
As per claim 1, Matsumoto teaches:
An apparatus comprising:
A timestamp counter control register to store an interrupt deadline;
a programmable interrupt controller to manage interrupts; ([Paragraph 64-67], In order to time-divisionally share the physical CPU 0 (10a) among the plurality of virtual CPUs 210, the timer management module 120 sets a timer event 130a for a clock tick timer configured to generate a timer interrupt at a fixed cycle period. The timer event 130a for the clock tick timer includes a start time 131a using the system time 80 as a time axis, an expiration time 132a, a cycle period 133a, and an enabled or disabled status 134a. The clock tick timer may be a system timer. The timer event 130 for the clock tick timer is set for each of the physical CPUs 10. For example, as described later with reference to FIG. 4A, the timer event 130a for the clock tick timer and timer events 130b to 130d for the clock tick timer can be provided... [Paragraph 40], The memory 50 is used as a volatile storage device configured to store a program and data. [Paragraph 50], The timer management module 120 of the virtual machine monitor 100 provides roles of, through use of the interrupt timer 40a of the physical CPU 10a, virtually realizing the interrupt timer 230a of the virtual CPU 210a, dispatching the host process 150 at a designated time, detecting a timeout of the program in operation, measuring a CPU usage amount of each piece of processing, and updating statistical information.)
a programmable interrupt controller timer to cause the programmable interrupt controller to generate an interrupt, wherein in a first mode the timestamp counter control register is to define the interrupt deadline for the programmable interrupt controller timer; ([Paragraph 4], The timer includes a remaining-time counter configured to decrement a value at a fixed frequency, and has an interval timer function of causing the remaining-time counter to start the decrementing when a value is written to the remaining-time counter and causing the interrupt controller to generate a timer interrupt in the CPU to which the interrupt controller belongs when the value becomes zero and to stop the operation until the next value is written to the remaining-time counter. [Paragraph 65], In order to activate the host process 1 (150a) at the designated time and detect a timeout of the relevant host process 1 (150a), the timer management module 120 associates a timer event 160a with the host process 1 (150a). The timer event 160a includes an expiration time 161a using the system time 80 as the time axis and an enabled or disabled status 162a.
a virtualized guest-timer to virtualize at least one timer of the apparatus; and ([Paragraph 9], However, in such related-art virtual machine systems as described in JP 2008-171293 A and disclosed in U.S. Pat. No. 7,475,002 B2, U.S. Pat. No. 8,533,709 B2, U.S. Pat. No. 7,707,578 B2, and U.S. Pat. No. 8,489,699 B2, an interrupt timer of a virtual CPU of a virtual machine is emulated through use of an interrupt timer of a physical CPU... [Paragraph 15], n conjunction with the processor scheduling mode, a timer scheduling mode to any one of: a shared timer mode in which the interrupt timer of the physical processor for which either one of the shared processor mode or the exclusive processor mode is set is shared among timer events for the plurality of virtual machines; and an exclusive timer mode in which the interrupt timer is occupied by a virtual timer of the specific virtual processor.)
execution circuitry to execute one or more instructions. ([Paragraph 51], The CPU 10 is also configured to run as a functional module for providing each function of the plurality of processes executed by the various programs. A computer and a computer system are an apparatus and a system including those functional modules, respectively.
As per claim 2, rejection of claim 1 is incorporated:
Matsumoto teaches wherein the virtualized guest-timer is circuitry. ([Paragraph 4], Those applications frequently use an interrupt timer of a CPU. The interrupt timer of a CPU herein represents a timer included in an interrupt controller built into a CPU motherboard. [Paragraph 9], However, in such related-art virtual machine systems as described in JP 2008-171293 A and disclosed in U.S. Pat. No. 7,475,002 B2, U.S. Pat. No. 8,533,709 B2, U.S. Pat. No. 7,707,578 B2, and U.S. Pat. No. 8,489,699 B2, an interrupt timer of a virtual CPU of a virtual machine is emulated through use of an interrupt timer of a physical CPU...)
As per claim 3, rejection of claim 1 is incorporated:
Matsumoto teaches wherein the virtualized guest-timer comprises microcode. ([Paragraph 9], However, in such related-art virtual machine systems as described in JP 2008-171293 A and disclosed in U.S. Pat. No. 7,475,002 B2, U.S. Pat. No. 8,533,709 B2, U.S. Pat. No. 7,707,578 B2, and U.S. Pat. No. 8,489,699 B2, an interrupt timer of a virtual CPU of a virtual machine is emulated through use of an interrupt timer of a physical CPU...)
As per claim 4, rejection of claim 1 is incorporated:
Matsumoto teaches wherein the apparatus includes virtual machine support in accordance to a virtual machine control data structure. ([Paragraph 14], Therefore, this invention has an object to control occupancy of an interrupt timer of a physical CPU by an interrupt timer of a virtual CPU in a virtual machine system in conjunction with dynamic switching of a scheduling mode for the physical CPU. [Paragraph 15], A method of controlling a virtual machine system, the virtual machine system comprising: an interrupt controller comprising an interrupt timer; a physical processor comprising the interrupt controller; a physical computer comprising the physical processor and a physical memory; and a virtualization module configured to allocate a computer resource of the physical computer to a plurality of virtual machines, the virtualization module being configured to control allocation of the physical processor, the method comprising: a first step of generating, by the virtualization module, the plurality of virtual machines by generating: a virtual processor comprising a virtual interrupt timer obtained by virtualizing the interrupt timer and a virtual interrupt controller obtained by virtualizing the interrupt controller, to which the computer resource of the physical processor is allocated; and a virtual memory to which the computer resource of the physical memory is allocated; a second step of setting, by the virtualization module, a processor scheduling mode to any one of: a shared processor mode in which one of the physical processors allocated to the plurality of virtual machines is shared among a plurality of the virtual processors; and an exclusive processor mode in which one of the physical processors allocated to the plurality of virtual machines is occupied by a specific virtual processor; and a third step of setting, by the virtualization module, in conjunction with the processor scheduling mode, a timer scheduling mode to any one of: a shared timer mode in which the interrupt timer of the physical processor for which either one of the shared processor mode or the exclusive processor mode is set is shared among timer events for the plurality of virtual machines; and an exclusive timer mode in which the interrupt timer is occupied by a virtual timer of the specific virtual processor.)
As per claim 5, rejection of claim 4 is incorporated:
Matsumoto teaches wherein the virtual machine control data structure is to include a field for a guest deadline for the virtualized guest-timer. ([Paragraph 64], In order to time-divisionally share the physical CPU 0 (10a) among the plurality of virtual CPUs 210, the timer management module 120 sets a timer event 130a for a clock tick timer configured to generate a timer interrupt at a fixed cycle period. The timer event 130a for the clock tick timer includes a start time 131a using the system time 80 as a time axis, an expiration time 132a, a cycle period 133a, and an enabled or disabled status 134a. The clock tick timer may be a system timer. The timer event 130 for the clock tick timer is set for each of the physical CPUs 10. For example, as described later with reference to FIG. 4A, the timer event 130a for the clock tick timer and timer events 130b to 130d for the clock tick timer can be provided. [Paragraph 66], The interrupt timer 230a of the virtual CPU 0 (210a) of the virtual machine 1 (200a) includes a remaining-time counter 231a and a timer frequency 232a in the same manner as the interrupt timer 40a of the physical CPU 0 (10a).)
As per claim 7, rejection of claim 1 is incorporated:
Matsumoto teaches wherein when a timer event from a virtualized guest occurs, the apparatus is to determine a time has been reached for the virtualized guest timer and trigger an interrupt. ([Paragraph 133], In Step 627, the extracted timer event is the timer event 240a for the virtual CPU 0 (210a), and hence the timer management module 120 notifies the virtual CPU 0 (210a) of the timer interrupt. When receiving the interrupt, the virtual CPU 0 (210a) executes predetermined processing corresponding to the timer event 240a. [Paragraph 143], By the above-mentioned processing, on the physical CPU 10 in the shared timer mode, the timer management module 120 can notify a computer resource corresponding to the timer event of the timer interrupt generated by the interrupt controller 30a, and can execute the processing corresponding to the timer event. When the timer event is the timer event 240a for the virtual CPU 210a, the timer management module 120 can notify the virtual CPU 210a of the timer interrupt, and can execute predetermined processing.)
As per claims 8-12 and 18, these are system claims corresponding to the apparatus claims 1-5 and 7. Therefore, rejected based on similar rationale.
As per claim 13, rejection of claim 12 is incorporated:
Matsumoto teaches wherein an exit from a virtual machine is to cause a value of the guest deadline to be stored in the virtual machine control data structure. ([Paragraph 109], The virtual machine monitor 100 traps the update request issued by the remaining-time counter 231a of the virtual CPU 210a, and transfers control to the timer management module 120 (Step 602). The virtual machine monitor 100 may activate the timer management module 120 at this point in time. [Paragraph 82], When the physical CPU 0 (10a) is taken as an example, the virtual machine monitor 100 first switches the physical CPU 0 (10a) from the exclusive CPU mode to the shared CPU mode. Then, the virtual machine monitor 100 detects that the load on the physical CPU 0 (10a) is lower than the loads on the physical CPU 2 (10c) and the physical CPU 3 (10d). [Paragraph 83], The virtual machine monitor 100 migrates the virtual CPU 0 (210a) of the virtual machine 2 (200b) and the host process 1 (150a) from the physical CPU 2 (10c) to the physical CPU 0 (10a) based on the load balancing. The patterns of migrating the virtual CPU 210 and the host process 150 in conjunction with the dynamic switching of the CPU scheduling mode 111a for the physical CPU 10a depend on occasions, and are not determined in advance. The same applies to the physical CPU 1 (10b). [Paragraph 64], The timer event 130a for the clock tick timer includes a start time 131a using the system time 80 as a time axis, an expiration time 132a, a cycle period 133a, and an enabled or disabled status 134a. The clock tick timer may be a system timer. The timer event 130 for the clock tick timer is set for each of the physical CPUs 10. For example, as described later with reference to FIG. 4A, the timer event 130a for the clock tick timer and timer events 130b to 130d for the clock tick timer can be provided.)
As per claim 19, rejection of claim 8 is incorporated:
Matsumoto teaches wherein the virtual machine is to run a guest operating system. ([Paragraph 47], A general-purpose operating system 201 operates on each of the virtual machines 200a to 200c. The general-purpose operating system 201 is specifically referred to as “guest operating system 201”.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Inakoshi (Pub 20110179417).
As per claim 6, rejection of claim 1 is incorporated:
Although Matsumoto discloses configuring of programmable interrupt controller timer.
Matsumoto does not explicitly disclose wherein the apparatus is to intercept a virtualization guest configuration attempt to configure the programmable interrupt controller timer and configure the virtualized guest-timer instead.
Inakoshi teaches wherein the apparatus is to intercept a virtualization guest configuration attempt to configure the programmable interrupt controller timer and configure the virtualized guest-timer instead. ([Paragraph 120], The setting of the timer interrupt is of the privilege instruction, and hence, in the case of the virtual system 11, an exception occurs in the physical CPU. With the exception, the control is transferred to the virtual machine monitor 1 from the guest OS 10B. The virtual machine monitor 1, to which the control is transferred from the guest OS 10B, intercepts the setting request of the timer interrupt from the guest OS 10B (arrow A2). The term "intercept" refers to receiving, in place of the hardware timer ATM, such timer setting that the guest OS 10B sets the occurrence of the timer interrupt after the elapse of a setting period in the hardware timer ATM. In the virtual machine 10 according to the first working example, the virtual machine monitor 1 intercepts the timer setting through the exception handling. As a result of the intercept, the guest OS 10B does not set the timer interrupt in the hardware timer. Note that the physical CPU executes the computer program deployed on the memory as a unit that receives the timer setting in place of the hardware timer ATM.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Matsumoto wherein an apparatus comprises interrupt deadline(s) that is/are stored in register/memory, interrupt controller manages interrupts and interrupt(s) is/are generated based on a interrupt deadline associated with a virtualized guest-timer associated with a timer of the apparatus, into teachings of Inakoshi wherein a virtualization guest configuration attempt to configure the programmable interrupt controller timer is intercepted and virtualized guest-timer is configured instead, because this would enhance the teachings of Matsumoto wherein by intercepting the configuration attempt which is a privilege instruction, virtual machine monitor can intercept the privilege instruction via exception handling and emulate the execution-requested privilege instruction (i.e. virtual timer setting). [Inakoshi paragraph 4]
As per claim 17, this is a system claim corresponding to the apparatus claim 6. Therefore, rejected based on similar rationale.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Wang et al. (Pub 20170262306) (hereafter Wang).
As per claim 14, rejection of claim 11 is incorporated:
Matsumoto does not explicitly disclose wherein the virtual machine control data structure is to include a field for a guest deadline shadow value.
Wang teaches wherein the virtual machine control data structure is to include a field for a guest deadline shadow value. ([Paragraph 139], Local APIC virtualization in the VMM may emulate the various local APIC operations and registers, such as: APIC identification/format registers, the local vector table (LVT), the interrupt command register (ICR), interrupt capture registers (TMR, IRR and ISR), task and processor priority registers (TPR, PPR), the EOI register and the APIC-timer register. Since local APICs are designed to operate with non-specific EOI, local APIC emulation also may emulate broadcast of EOI to the guest's virtual I/O APICs for level triggered virtual interrupts. [Paragraph 27], To interface the VMs 104 and 106 to resources of the processor device 102, state and control information is modified and otherwise tracked via a set of fields within a virtual machine control structure (VMCS) 122.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Matsumoto wherein an apparatus comprises interrupt deadline(s) that is/are stored in register/memory, interrupt controller manages interrupts and interrupt(s) is/are generated based on a interrupt deadline associated with a virtualized guest-timer associated with a timer of the apparatus, into teachings of Wang wherein VMCS includes guest deadline shadow value because this would enhance the teachings of Matsumoto wherein by including the guest deadline shadow value it allows local APIC virtualization in the VMM to emulate various local APIC operations and registers. [Wang paragraph 139]
As per claim 15, rejection of claim 14 is incorporated:
Wang teaches wherein a read of the timestamp counter control register that does not cause a fault is to return the guest deadline shadow value. ([Paragraph 157], Guest access to these virtual registers may be configured to cause page-fault induced VM-exits by marking these regions as always not present. The VMM may handle these VM exits by invoking appropriate virtual device emulation code.)
As per claim 16, rejection of claim 11 is incorporated:
Matsumoto does not explicitly disclose wherein the virtual machine control data structure is to include a field for a virtual timer vector to contain a vector to be used for virtual time interrupts.
Wang teaches wherein the virtual machine control data structure is to include a field for a virtual timer vector to contain a vector to be used for virtual time interrupts. ([Paragraph 139], Local APIC virtualization in the VMM may emulate the various local APIC operations and registers, such as: APIC identification/format registers, the local vector table (LVT), the interrupt command register (ICR), interrupt capture registers (TMR, IRR and ISR), task and processor priority registers (TPR, PPR), the EOI register and the APIC-timer register. Since local APICs are designed to operate with non-specific EOI, local APIC emulation also may emulate broadcast of EOI to the guest's virtual I/O APICs for level triggered virtual interrupts. [Paragraph 140], A local APIC allows interrupt masking at two levels: mask bit in the local vector table entry for local interrupts and raising processor priority through the TPR registers for masking lower priority external interrupts. The VMM may comprehend these virtual local APIC mask settings as programmed by the guest in addition to the guest virtual processor interruptibility state (when injecting APIC routed external virtual interrupts to a guest VM). [Paragraph 128], In certain implementations, a processing system operating in accordance with one or more aspects of the present disclosure uses 8-bit vectors of which 224 (20H-FFH) are available for external interrupts. Vectors are used to select the appropriate entry in the interrupt descriptor table (IDT). VMX operation allows each guest to control its own IDT. Host vectors refer to vectors delivered by the platform to the processor during the interrupt acknowledgement cycle. Guest vectors refer to vectors programmed by a guest to select an entry in its guest IDT. Depending on the I/O resource management models supported by the VMM design, the guest vector space may or may not overlap with the underlying host vector space.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Matsumoto wherein an apparatus comprises interrupt deadline(s) that is/are stored in register/memory, interrupt controller manages interrupts and interrupt(s) is/are generated based on a interrupt deadline associated with a virtualized guest-timer associated with a timer of the apparatus, into teachings of Wang wherein VMCS includes a virtual timer vector, because this would enhance the teachings of Matsumoto wherein by including various fields such as virtual timer vector, it allows vectors to be used to select appropriate entry in an interrupt descriptor table to allow guest to control its own interrupt descriptor table. [Wang paragraph 128]
As per claim 20, rejection of claim 8 is incorporated:
Matsumoto does not explicitly disclose wherein the memory is to store a virtual programmable interrupt controller page per virtual logical processor.
Wang teaches wherein the memory is to store a virtual programmable interrupt controller page per virtual logical processor. ([Paragraph 104], In an illustrative example, a TLB may be implemented as a table mapping virtual addresses to physical addresses. “TLB hit” refers to a situation when a requested virtual address is present in the TLB. “TLB miss” refers to the opposite situation: when the requested virtual address is not present in the TLB, the address translation may proceed by looking up the page table. After the physical address is determined, the virtual address to physical address mapping may be entered into the TLB. [Paragraph 106], The VMM may further create several memory pages corresponding to the above referenced views, such that each memory page would have at least an execute permission in the respective view. A first memory page 1330, which is executable from default view 1310, may comprise unprotected (i.e., guest-modifiable) guest-executable code and guest data. A second memory page 1340, which is executable from alternative view 1320, may comprise protected guest-executable code which may be employed to perform certain tasks (e.g., exit-less communication with a peer virtual machine). [Paragraph 113], When the “enable EPT” VM-execution control is 1, the identity of guest-physical addresses depends on the value of CR0.PG. If CR0.PG=0, each linear address is treated as a guest-physical address. If CR0.PG=1, guest-physical addresses are those derived from the contents of control register CR3 and the guest paging structures. (This includes the values of the PDPTEs, which logical processors store in internal, non-architectural registers.) The latter includes (in page-table entries and in other paging-structure entries for which bit 7—PS—is 1) the addresses to which linear addresses are translated by the guest paging structures. [Paragraph 122], The VPID and EPT features of the architecture for VMX operation augment this caching architecture. EPT defines the guest-physical address space and defines translations to that address space (from the linear-address space) and from that address space (to the physical-address space). Both features control the ways in which a logical processor may create and use information cached from the paging structures.)
It would have been obvious to a person with ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Matsumoto wherein an apparatus comprises interrupt deadline(s) that is/are stored in register/memory, interrupt controller manages interrupts and interrupt(s) is/are generated based on a interrupt deadline associated with a virtualized guest-timer associated with a timer of the apparatus, into teachings of Wang wherein memory stores virtual programmable interrupt controller page per virtual logical processor, because this would enhance the teachings of Matsumoto wherein by storing virtual programmable interrupt controller page per virtual logical processor, it allows each virtual logical processor with corresponding virtual machine to maintain its own paging table.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG U KIM whose telephone number is (571)270-1313. The examiner can normally be reached 9:00am - 5:00pm.
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/DONG U KIM/Primary Examiner, Art Unit 2197
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