DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/23/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal.
As to claim 17, Argarwal teaches an integrated circuit (fig 1 and 4, paragraph 59) comprising:
a current mirror (104 and 108) including a first output terminal (output terminal outputting 154) and a second output terminal (output terminal outputting 156);
a first resistor (110) including a first terminal and a second terminal, the first terminal of the first resistor coupled to the first output terminal of the current mirror;
a second resistor (122) including a first terminal including a first terminal coupled to the second terminal of the first resistor and a second terminal;
a first switch (130A) including a control terminal, a first terminal, and a second terminal, the first terminal of the first switch coupled to the second output terminal of the current mirror (paragraphs 24 and 25);
a first capacitor (408A) including a first terminal and a second terminal, the first terminal of the capacitor coupled to the second terminal of the first switch;
a third resistor (406A) including a first terminal coupled to the second terminal of the capacitor;
a fourth resistor (406A is formed as a string of resistors) including a first terminal coupled to the second terminal of the second resistor and a second terminal (paragraphs 32, 36 and 37, resistors formed in a string);
a second switch (130C) including a control terminal, a first terminal, and a second terminal, the first terminal of the second switch coupled to the first terminal of the capacitor, the second terminal of the second switch (126, paragraphs 24 and 25);
a switch (138) including a control terminal (142A and 142B), a first terminal, and a second terminal, the first terminal of the third switch coupled to the first terminal of the capacitor (paragraphs 21, 24, 25 and 41);
a fourth switch (130B) including a control terminal, a first terminal, and a second terminal, the control terminal of the fourth switch coupled to the second output terminal of the circuitry, the first terminal of the fourth switch coupled to the second output terminal of the current mirror;
a second capacitor (408B) including a first terminal and a second terminal, the first terminal of the second capacitor coupled to the second terminal of the fourth switch;
a fifth resistor (406B) including a first terminal and a second terminal, the first terminal of the firth resistor coupled to the second terminal of the second capacitor (408B);
a sixth resistor (406B is formed as a string of resistors) including a first terminal coupled to the second terminal of the third resistor and a second terminal (paragraphs 32, 36 and 37, resistors formed in a string).
a fifth switch (130D) including a control terminal coupled to the first output terminal of the circuitry, a first terminal coupled to the first terminal of the second capacitor, and a second terminal (126); and
a switch (within 138) including a control terminal coupled to the second output terminal of the circuitry, a first terminal coupled to the first terminal of the second capacitor, and a second terminal coupled to the input terminal of the comparator (paragraphs 24 and 25);
a comparator (144) including an input terminal (connected to 146A and 146B) and an output terminal (connected to 148A and 148B), the input terminal of the comparator coupled to the second terminal of the third switch (coupled to 138); and
circuitry (150) including an input terminal coupled to the output terminal of the comparator, a first output terminal (connected to 152A) coupled to the control terminal of the first switch and the control terminal of the third switch, and a second output terminal (connected to 152B) coupled to the control terminal of the second switch (paragraphs 24 and 25).
Argawal does not explicitly teach a third and sixth switch.
As would have been recognized by a person of ordinary skill in the art, using a third and sixth switch is done merely a design choice to choosing a notoriously well known in the art switching circuit to be used as switching circuit in Argawal (paragraph 25, the inputs are selectively output Vrefcomp, VA, VB, where VA and VB are selectively output based on the charging times, thus a person of ordinary skill in the art could have a switch selecting VA to an output, and another switch to have VB to an output, and disabling said switching when they are not output). As such it would have been obvious to a person of ordinary skill in the art at the time of the invention to use extra switches (third and sixth switch) in the circuit of Argawal as doing so would be a mere matter of design choice to choosing notoriously well known in the art switching to do the switching task taught in Argawal.
As to claim 18, As would have been recognized by a person of ordinary skill in the art, using transmission gate as an input-controlled switch is done merely as a design choice to choosing a notoriously well known in the art type of switch. As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to modify the switches used in Agarwal with transmission gates as doing so would be a mere matter of design choice to using notoriously well known in the art switching circuits.
As to claim 19, Agarwal teaches the first resistor is an internal resistor (paragraph 19) which maybe made of one more resistors with an adapted structure to fit internally (paragraphs 59 and 60). It would be obvious to a person of ordinary skill in the art to form the first resistor with a plurality of resistors in a structural configuration as doing so would be a mere matter of design choice to choosing a user desired configuration to appropriately fit a user desired resistance value in an internal structure.
As to claim 20, Agarwal teaches the first resistor (paragraph 19) which maybe made of different configurations (paragraphs 59 and 60). It would be obvious to a person of ordinary skill in the art to use an N-type polysilicon resistor as doing so would be a mere matter of design choice to choosing a notoriously well known resistor for the resistor taught in Agarwal.
Allowable Subject Matter
Claims 1-16 are allowed.
None of the cited prior art teach or suggest the resistor oriented at an angle with respect to one another one of the set of resistor to compensate for stress applied to the first resistor as is recited in claims 1-11; and the corresponding respective stress sensitivity ratios as is recited in claims 12-16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY M SHIN whose telephone number is (571)270-7356. The examiner can normally be reached M-F 9am-6pm PST.
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/JEFFREY M SHIN/Primary Examiner, Art Unit 2849
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