Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicants’ arguments filed on 05/19/2026 are acknowledged. Applicant elects Species I. Accordingly, claims 1-6, 7, 13, 14 and 19 remain pending and have been examined.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in parent Application No. CN202111627015.7, filed on 12/28/2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/10/2025 was compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 7, 13, 14 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Corcoran (US 2018/0330526 A1) hereinafter Corcoran.
Regarding Claim 1, Corcoran teaches an image processing circuit (fig.1B: CCU; central control unit), wherein the image processing circuit comprises: an image sensor (camera 18); a processor chip (fig.1B; CCU), wherein the processor chip is communicatively connected to the image sensor (fig.1B: CCU; central control unit and camera unit 18 are connected), and the processor chip comprises a first camera serial interface and a first bus interface (Para.0096; camera and processor with serial interface 54); and an image processing chip, wherein the image processing chip comprises a second camera serial interface and a second bus interface (Para.0096; camera and processor with serial interface 54), the second camera serial interface is connected to the first camera serial interface (Para.0096; camera and processor with serial interface 54), and the second bus interface is connected to the first bus interface, wherein the image processing chip and the processor chip transmit image data through the second camera serial interface and the first camera serial interface (Para.0096; multiple camera 18 and processor 30 with serial interface 54 transmit image data), and transmit control instructions through the second bus interface and the first bus interface (fig.1B-1E; Para.0039, 0096 and 0106; camera and processor with serial interface 54 transmit instruction using multi bus).
Regarding Claim 2, Corcoran teaches the image processing circuit according to claim 1, wherein the processor chip further comprises a first display serial interface, the image processing chip comprises a second display serial interface (Para.0078; vision system 8), and the second display serial interface is connected to the first display serial interface (fig.1B-1E; Para.0039, 0096 and 0106; Para.0078; vision system 8; camera and processor is connected to display).
Regarding Claim 3, Corcoran teaches the image processing circuit according to claim 2, wherein the processor chip further comprises an image signal processing module and a display synthesis service module, one end of the display synthesis service module is communicatively connected to the image sensor through the image signal processing module, and the other end of the display synthesis service module is connected to the first display serial interface (fig.1B-1E; Para.0039, 0096 and 0106; Para.0078; vision system 8; camera and processor is connected to display).
Regarding Claim 4, Corcoran teaches the image processing circuit according to claim 1, wherein the processor chip further comprises a first storage module, and the first camera serial interface is communicatively connected to the first storage module (fig.1B-1E; Para.0039, 0096 and 0106; camera and processor with storage 24M).
Regarding Claim 5, Corcoran teaches the electronic device, comprising the image processing circuit according to claim 1 (fig.1B-1E; Para.0039, 0096 and 0106; camera and processor).
Regarding Claim 6, Corcoran teaches same reason as Claim 1.
Regarding Claim 7, Corcoran teaches the method according to claim 6, wherein after the sending the second image data to the processor chip through the second camera serial interface, the method further comprises: receiving, through the second bus interface, a stream-off instruction sent by the processor chip; and in response to the stream-off instruction, stopping sending the second image data to the processor chip (fig.1B-1E; Para.0039, 0096 and 0106; camera and processor with serial interface 54 transmit instruction using multi bus).
Regarding Claim 13, Corcoran teaches an electronic device, comprising a processor and a memory (Para.0037; memory 24M), wherein the memory stores a program or instructions capable of running on the processor, wherein the program or the instructions, when executed by the processor, cause the electronic device to perform the steps of the data transmission method according to claim 6 (fig.1B-1E; Para.0039, 0096 and 0106; camera and processor with serial interface 54 transmit instruction using multi bus).
Regarding Claim 14, Corcoran teaches the electronic device according to claim 13, wherein after sending the second image data to the processor chip through the second camera serial interface, the program or the instructions, when executed by the processor, cause the electronic device to further perform: receiving, through the second bus interface, a stream-off instruction sent by the processor chip (Para.0039, 0096 and 0106); and in response to the stream-off instruction, stopping sending the second image data to the processor chip (fig.1B-1E; Para.0039, 0096 and 0106; camera and processor with serial interface 54 transmit instruction using multi bus).
Regarding Claim 19, Corcoran teaches a non-transitory readable storage medium, wherein the non-transitory readable storage medium stores a program or instructions, and when the program or the instructions are executed by a processor, the steps of the data transmission method according to claim 6 are implemented (fig.1B-1E; Para.0012; 0039, 0096 and 0106).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAYEZ A BHUIYAN whose telephone number is (571)270-1562. The examiner can normally be reached on 9:00 - 6:00 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAYEZ BHUIYAN/
Examiner, Art Unit 2639
/LIN YE/Supervisory Patent Examiner, Art Unit 2638
