DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendment dated 6/29/2026 has resolved the previous indefiniteness type rejections as well as the previous objections.
Applicant’s arguments with respect to the amended claim(s) and the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The new ground of rejections has introduced the secondary reference Chen (CN 1112558677) to teach the new limitations of cutting off the reverse current when the power supply voltage drops as set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 and 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nikolov (US 8,330,532) in view of Chen (CN 1112558677).
With respect to claim 1, Nikolov discloses an integrated circuit (Fig. 6 60) for generating an intermediate supply voltage which is immune to power supply voltage glitches, the integrated circuit comprising: a Band Gap Reference (BGR) circuit (Fig. 2 20,C1,21,24,CF2) configured to generate a reference voltage (Fig. 2 VREF) immune to glitch (Fig. 2 VBG filters glitches) of a power supply (Fig. 2 VDD); and a Low Dropout (LDO) circuit (Fig. 2 BPC,MBP,22) configured to receive the reference voltage from the BGR circuit, wherein the LDO circuit is configured to generate the intermediate supply voltage (Fig. 2 VLDO) based on the reference voltage and the power supply, LDO having an output terminal (Fig. 2 terminal VLDO). Nikilov does not disclose wherein the LDO circuit is configured to cut off a reverse current path from an output terminal of the LDO circuit to the power supply when a voltage of the power supply is less than the intermediate supply voltage.
Chen discloses wherein an LDO circuit (Fig. 3 10-30) is configured to cut off (Fig. 3 20 opens when VIN drops) a reverse current path from an output terminal (Fig. 3 terminal VOUT) of the LDO circuit to the power supply (Fig. 3 VIN generated by power supply) when a voltage (Fig. 3 VIN) of the power supply is less than the intermediate supply voltage (Fig. 3 VOUT). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the LDO circuit is configured to cut off a reverse current path from an output terminal of the LDO circuit to the power supply when a voltage of the power supply is less than the intermediate supply voltage, in order to prevent reverse current from VOUT to VIN if the power supply is lost or lowered too quickly.
With respect to claim 3, Nikolov in view of Chen make obvious the integrated circuit as claimed in claim 1, wherein the LDO circuit (Fig. 2 22,23,BPC,CF1,R2,MBP) comprises: a first circuitry (Fig. 2 23,RB) forming a proportional path, wherein the first circuitry includes a set of one or more resistors (Fig. 2 RB), one or more buffers (Fig. 2 IB BUF), and one or more first capacitors (Fig. 2 C4); a second circuitry (Fig. 2 22,BPC,MBP,CF1) forming a differential path, wherein the second circuitry includes a plurality of second capacitors (Fig. 2 CF1,capacitor in 22); a plurality of MOS transistors (Fig. 2 MBP, transistor in 22); and a filter (Fig. 2 CF1).
With respect to claims 6 and 8, Nikolov in view of Chen make obvious the method as set forth above. See claims 1 and 3, respectively, for additional details.
Claim(s) 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Nikolov (US 8,330,532) n view of Chen (CN 1112558677) and further in view of Cheng (CN 112181038).
With respect to claim 2, Nikolov in view of Chen make obvious the integrated circuit as claimed in claim 1, wherein the BGR circuit comprises a cascaded Resistor-Capacitor (RC) filter (Fig. 2 R3,C1,RF1,CF2). Nikolov does not disclose implementing a switched-capacitor based notch circuit, which was known before the effective filing date of the invention.
Cheng discloses a resistor capacitor filter (Fig. 3 2) filtering the output of a BGR circuit (Fig. 3 1) and at least one switched-capacitor based notch circuit (Fig. 3 3), and the RC filter (Fig. 3 2) is configured to filter one of an overshoot or an undershoot in the reference voltage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement at least one switched-capacitor based notch circuit, and the cascaded RC filter is configured to filter one of an overshoot or an undershoot in the reference voltage, in order to remove noise from the reference voltage.
With respect to claim 7, Nikolov in view of Chen and Cheng make obvious the method as set forth above. See claim 2 for additional details.
Claim(s) 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nikolov (US 8,330,532) in view of Chen (CN 1112558677) and further in view of Kadlimatti (US 2024/0361794).
With respect to claim 4, Nikolov in view of Chen make obvious the integrated circuit as set forth above, and wherein the second circuitry is configured to amplify transition (Fig. 2 DA,BPC amplify transition passed to VLDO) on the main power supply (Fig. 2 VDD), and to generate a second control signal (Fig. 2 gate signals to pass transistors) with lag (Fig. 2 loop is slower than glitch detector) to the first control signal, the second control signal controlling the plurality of MOS transistors to generate the intermediate supply voltage (Fig. 2 VLDO). Nikolov does not disclose glitch detection.
Kadlimatti discloses a glitch detector which comprises a first circuitry (Fig. 2 146) forming a proportional path, wherein the first circuitry includes a set of one or more resistors (Fig. 2 220), one or more buffers (Fig. 2 202), and one or more first capacitors (Fig. 2 22), wherein the first circuitry is configured to sense a glitch (Fig. 1 146) in a power supply (Fig. 2 VDD), and to generate a first control signal (Fig. 2 Q output). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the first circuitry is configured to sense a glitch in the power supply, and to generate a first control signal; and wherein the second circuitry is configured to amplify transition on the main power supply, and to generate a second control signal with lag to the first control signal, the second control signal controlling the plurality of MOS transistors to generate the intermediate supply voltage, in order to protect from glitches in the power supply.
With respect to claim 9, Nikolov in view of Chen and Kadlimatti make obvious the method as set forth above. See claim 4 for additional details.
Claim(s) 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nikolov (US 8,330,532) n view of Chen (CN 1112558677) and further in view of Matsumoto (US 2024/0288891).
With respect to claim 5, Nikolov in view of Chen make obvious the integrated circuit as claimed in claim 1, and further discloses a feedback resistor (Fig. 2 RFB) connected to an output terminal (Fig. 2 VLDO) of the LDO circuit. Nikolov remains silent as to whether the feedback resistor is a trim resistor and does not require wherein the LDO circuit comprises a third circuitry forming a delayed enabling path, wherein the third circuitry includes a resistor and a plurality of MOS transistors, and the third circuitry is connected to a trim resistor connected to an output terminal of the LDO circuit.
Matsumoto discloses a circuit comprises a third circuitry (Fig. 4 1a) forming a delayed enabling path, wherein the third circuitry includes a resistor (Fig. 4 R1-R12) and a plurality of MOS transistors (Fig. 4 Tr1-Tr4), and the third circuitry is connected to an output terminal of the power supply (Fig. 4 t1). While the references do not require trimming the feedback resistors, it was very well known before the effective filing date of the claimed invention to implement a trim resistor connected to an output terminal of the LDO circuit, in order to improve the accuracy of the feedback resistor in order to improve the accuracy of the output regulation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the feedback resistor of Nikolov is a trim resistor such that the LDO circuit comprises a third circuitry forming a delayed enabling path, wherein the third circuitry includes a resistor and a plurality of MOS transistors, and the third circuitry is connected to a trim resistor connected to an output terminal of the LDO circuit, in order to improve the response and accuracy of the output voltage.
With respect to claim 10, Nikolov in view of Chen and Matsumoto make obvious the method as set forth above. See claim 5 for additional details.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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