DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/28/24 and 10/16/25 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the plurality of resistors, as required in claim 5, must be shown or the feature(s) canceled from the claim(s). Examiner notes Figure 8 802 only shows a single resistor, not a plurality. Furthermore, the third circuitry in parallel with the trim resistor, as in claim 5, must be shown or the feature canceled from the claim. Examiner notes AVSS is not V0P_ALV and 802 is not in parallel with R-Trim and its series transistor. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-5 are objected to because of the following informalities: in claim 1, lines 1-2, “immune to glitch on power supply voltage” should be ‘immune to power supply voltage glitches’.
Appropriate correction is required.
In claim 4, “main power supply” does not match the previously recited “power supply” in independent claim 1. Likewise, in claim 9, “input power supply” does not match the previously recited “power supply” in independent claim 6.
Appropriate clarification is requested.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where Applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “parallel” in claims 5 and 10 are used by the claims to mean “adjacent,” while the accepted meaning is “parallel.” The term is indefinite because the specification does not clearly redefine the term. Figure 8 802 shows the disclosed third circuitry and the trim resistor R-trim, but as can be seen in Figure 8, 802 is not in parallel to R-trim since 802 is connected between VOUT and V0P7_ALV while R-Trim is connected between VOUT and AVSS, and AVSS is not the same as V0P7_ALV. For the purpose of examination the claim limitation shall be interpreted as being drafted as a misinterpretation of Figure 8 and require the elements connected to the output node. Examiner also notes Figure 8 802 does not show a plurality of resistors, further confusing the claim when interpreted in light of the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6 and 8 are rejected under 35 U.S.C. 102a1 as being anticipated by Nikolov (US 8,330,532).
With respect to claim 1, Nikolov discloses an integrated circuit (Fig. 6 60) for generating an intermediate supply voltage which is immune to glitch on power supply voltage, the integrated circuit comprising: a Band Gap Reference (BGR) circuit (Fig. 2 20,C1,21,24,CF2) configured to generate a reference voltage (Fig. 2 VREF) immune to glitch (Fig. 2 VBG filters glitches) of a power supply (Fig. 2 VDD); and a Low Dropout (LDO) circuit (Fig. 2 BPC,MBP,22) configured to receive the reference voltage from the BGR circuit, wherein the LDO circuit is configured to generate a glitch-immune (Fig. 2 MBP removes glitches) intermediate supply voltage (Fig. 2 VLDO) based on the reference voltage and the power supply.
With respect to claim 3, Nikolov discloses the integrated circuit as claimed in claim 1, wherein the LDO circuit (Fig. 2 22,23,BPC,CF1,R2,MBP) comprises: a first circuitry (Fig. 2 23,RB) forming a proportional path, wherein the first circuitry includes a set of one or more resistors (Fig. 2 RB), one or more buffers (Fig. 2 IB BUF), and one or more first capacitors (Fig. 2 C4); a second circuitry (Fig. 2 22,BPC,MBP,CF1) forming a differential path, wherein the second circuitry includes a plurality of second capacitors (Fig. 2 CF1,capacitor in 22); a plurality of MOS transistors (Fig. 2 MBP, transistor in 22); and a filter (Fig. 2 CF1).
With respect to claims 6 and 8, Nikolov discloses the method as set forth above. See claims 1 and 3, respectively, for additional details.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Nikolov (US 8,330,532) in view of Cheng (CN 112181038).
With respect to claim 2, Nikolov discloses the integrated circuit as claimed in claim 1, wherein the BGR circuit comprises a cascaded Resistor-Capacitor (RC) filter (Fig. 2 R3,C1,RF1,CF2). Nikolov does not disclose implementing a switched-capacitor based notch circuit, which was known before the effective filing date of the invention.
Cheng discloses a resistor capacitor filter (Fig. 3 2) filtering the output of a BGR circuit (Fig. 3 1) and at least one switched-capacitor based notch circuit (Fig. 3 3), and the RC filter (Fig. 3 2) is configured to filter one of an overshoot or an undershoot in the reference voltage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement at least one switched-capacitor based notch circuit, and the cascaded RC filter is configured to filter one of an overshoot or an undershoot in the reference voltage, in order to remove noise from the reference voltage.
With respect to claim 7, Nikolov in view of Cheng make obvious the method as set forth above. See claim 2 for additional details.
Claim(s) 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nikolov (US 8,330,532) in view of Kadlimatti (US 2024/0361794).
With respect to claim 4, Nikolov discloses the integrated circuit as set forth above, and wherein the second circuitry is configured to amplify transition (Fig. 2 DA,BPC amplify transition passed to VLDO) on the main power supply (Fig. 2 VDD), and to generate a second control signal (Fig. 2 gate signals to pass transistors) with lag (Fig. 2 loop is slower than glitch detector) to the first control signal, the second control signal controlling the plurality of MOS transistors to generate the intermediate supply voltage (Fig. 2 VLDO). Nikolov does not disclose glitch detection.
Kadlimatti discloses a glitch detector which comprises a first circuitry (Fig. 2 146) forming a proportional path, wherein the first circuitry includes a set of one or more resistors (Fig. 2 220), one or more buffers (Fig. 2 202), and one or more first capacitors (Fig. 2 22), wherein the first circuitry is configured to sense a glitch (Fig. 1 146) in a main power supply (Fig. 2 VDD), and to generate a first control signal (Fig. 2 Q output). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the first circuitry is configured to sense a glitch in a main power supply, and to generate a first control signal; and wherein the second circuitry is configured to amplify transition on the main power supply, and to generate a second control signal with lag to the first control signal, the second control signal controlling the plurality of MOS transistors to generate the intermediate supply voltage, in order to protect from glitches in the power supply.
With respect to claim 9, Nikolov in view of Kadlimatti make obvious the method as set forth above. See claim 4 for additional details.
Claim(s) 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nikolov (US 8,330,532) in view of Matsumoto (US 2024/0288891).
With respect to claim 5, Nikolov discloses the integrated circuit as claimed in claim 1, and further discloses a feedback resistor (Fig. 2 RFB) connected to an output terminal (Fig. 2 VLDO), and does not require wherein the LDO circuit comprises a third circuitry forming a delayed enabling path, wherein the third circuitry includes a plurality of resistors and a plurality of MOS transistors, and the third circuitry is connected in parallel to resistor connected to an output terminal of the LDO circuit.
Matsumoto discloses a circuit comprises a third circuitry (Fig. 4 1a) forming a delayed enabling path, wherein the third circuitry includes a plurality of resistors (Fig. 4 R1-R12) and a plurality of MOS transistors (Fig. 4 Tr1-Tr4), and the third circuitry is connected in parallel to an output terminal of the power supply (Fig. 4 t1). While the references do not require trimming the feedback resistors, it was very well known before the effective filing date of the claimed invention to implement a trim resistor connected to an output terminal of the LDO circuit, in order to improve the accuracy of the feedback resistor in order to improve the accuracy of the output regulation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the LDO circuit comprises a third circuitry forming a delayed enabling path, wherein the third circuitry includes a plurality of resistors and a plurality of MOS transistors, and the third circuitry is connected in parallel to a trim resistor connected to an output terminal of the LDO circuit, in order to improve the response and accuracy of the output voltage.
With respect to claim 10, Nikolov in view of Matsumoto make obvious the method as set forth above. See claim 10 for additional details.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Strik (US 8,289,009) discloses filtering a bandgap reference voltage to an LDO with a cascaded RC filter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838