DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 17 contains the trademark/trade name IEEE 1500. Where a trademark or trade name is used in a claim as a limitation to identify or describe a particular material or product, the claim does not comply with the requirements of 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. See Ex parte Simpson, 218 USPQ 1020 (Bd. App. 1982). The claim scope is uncertain since the trademark or trade name cannot be used properly to identify any particular material or product. A trademark or trade name is used to identify a source of goods, and not the goods themselves. Thus, a trademark or trade name does not identify or describe the goods associated with the trademark or trade name. In the present case, the trademark/trade name is used to identify/describe a connector and, accordingly, the identification/description is indefinite.
Regarding claim 12, the claim is indefinite because the claim is drawn to an apparatus but the boot processor in lines 2-3, 6-8 are drawn to method steps. (MPEP 2173.05(p)(II) A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011).)
There is a difference between a boot processor capable of monitoring and a boot processor configured to monitor. There is a difference between a boot processor capable of initiating than a boot processor configured to initiate.
Regarding claim 13, the claim is indefinite because the claim is drawn to an apparatus but the boot processor in lines 1-3 are drawn to method steps. (MPEP 2173.05(p)(II) A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011).)
There is a difference between a boot processor capable of storing and a boot processor configured to store.
Regarding claim 14, the claim is indefinite because the claim is drawn to an apparatus but the boot processor in lines 1-2 are drawn to method steps. (MPEP 2173.05(p)(II) A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011).)
There is a difference between a boot processor capable of initiating and a boot processor configured to initiate. There is a difference between a boot processor capable of initiating than a boot processor configured to initiate.
Regarding claim 15, the claim is indefinite because the claim is drawn to an apparatus but the boot processor in lines 1-3 are drawn to method steps and the memory controller in lines 3 and 4 are drawn to method steps/ (MPEP 2173.05(p)(II) A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011).)
There is a difference between a boot processor initializes and a boot processor configured to initialize. There is a difference between a memory controller capable of communicating than a boot processor configured to communicate.
Regarding claim 16, the claim is indefinite because the claim is drawn to an apparatus but the boot processor in lines 2-3 are drawn to method steps (MPEP 2173.05(p)(II) A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011).)
There is a difference between a boot processor invoking and a boot processor configured to invoke.
Regarding claim 18, the claim is indefinite because the claim is drawn to an apparatus but the boot processor in lines 2-3 are drawn to method steps. (MPEP 2173.05(p)(II) A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011).)
There is a difference between a boot processor initiates and a boot processor configured to initiate.
Claims 17, 19 and 20 are rejected for containing the 112 rejections above and for depending on rejected claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et al. (US 20220102224) .
Regarding claim 1, An et al. teach A method of operation for an integrated circuit device, (Note the elements of Fig. 4 is interpreted as an integrated circuit device) the method comprising:
initiating a boot process of the integrated circuit device, wherein the boot process is implemented by a boot processor (Note Test host with CPU, Fig. 4, par. 0077) of the integrated circuit device;
as part of the boot process, initiating a die crack test of a memory device of the integrated circuit device, wherein the memory device (Note 31 and 32, Fig. 4) is coupled to the boot processor; (Note Test host with CPU, Fig. 4, par.0077 )
receiving, by the boot processor, a result of the die crack test of the memory device during the boot process; (Note [0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14. The test host 402 may apply the main power voltage VCC to the C11 channel terminal, apply the power voltage VCCQ to the channel terminal C12, and apply the ground voltage VSS to the remaining channel terminals C13 and C14. The ground voltage VSS applied to the channel terminal C13 may provide the hardware reset signal RST_n of the storage device 10 at a low level. Accordingly, when the storage device 10 transitions to the idle power state S330 and the first and second NVMs 30 and 31 enter the low power mode, the test host 402 may measure current flowing through the first channel terminals C11 to C14. The test host 402 may detect crack defects of the NVMs 30 and 31 based on the current measured in the first channel terminals C11 to C14. The test host 402 may determine crack defects of the NVMs 30 and 31 when the current measured in the first channel terminals C11 to C14 is greater than or equal to a test reference value.)
and
storing the result of the die crack test in a register of the integrated circuit device.(Examiner takes the position that cpu 404 inherently has memory for storing which would implicitly teach a register .)
Regarding claim 2, An et al. teach wherein the boot process is implemented by the boot processor (cpu 404, Fig. 4) executing a bootloader for the integrated circuit device, wherein the bootloader includes instructions that, upon execution, initiate the die crack test. [0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14.
Regarding claim 3, An et al. teach wherein the initiating the boot process is performed in response to a reset of the integrated circuit device. Examiner’s position is that when the test ends (Fig. 5)(interpreted as reset) and when another test begins is interpreted as initiating a boot process.
Regarding claim 4, An et al. wherein the die crack test is initiated by the boot processor (CPU 404, Fig. 4) invoking a die crack monitor (DCM) circuit (testboard 420, Fig. 4) of the memory device through a dedicated test port of the memory device. (Note conductor leading from NVM 31 to B10 to U10 to L10 to connectors of 400. Fig. 4)
Regarding claim 10, An et al. teach wherein the memory device is a memory chiplet. (Note combination of 30 and 31, Fig. 4)
Regarding claim 5, An et al. teach prior to initiating the die crack test of the memory device, initializing, by the boot processor (CPU 404), a memory controller (20, par. 0074) capable of communicating with the memory device over the dedicated test port.
Regarding claim 7, An et al. teach wherein the memory device is one of a plurality of memory devices (Note 30 and 31, Fig. 4) of the integrated circuit device, and wherein the method comprises: initiating the die crack test in each of the plurality of memory devices of the integrated circuit device. (Note [0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14. The test host 402 may apply the main power voltage VCC to the C11 channel terminal, apply the power voltage VCCQ to the channel terminal C12, and apply the ground voltage VSS to the remaining channel terminals C13 and C14. The ground voltage VSS applied to the channel terminal C13 may provide the hardware reset signal RST_n of the storage device 10 at a low level. Accordingly, when the storage device 10 transitions to the idle power state S330 and the first and second NVMs 30 and 31 enter the low power mode, the test host 402 may measure current flowing through the first channel terminals C11 to C14. The test host 402 may detect crack defects of the NVMs 30 and 31 based on the current measured in the first channel terminals C11 to C14. The test host 402 may determine crack defects of the NVMs 30 and 31 when the current measured in the first channel terminals C11 to C14 is greater than or equal to a test reference value.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615).
Regarding claim 12, An et al. teach an integrated circuit device (Note the elements of Fig. 4 is interpreted as an integrated circuit device), comprising: a boot processor capable of implementing a boot process by executing a bootloader; (Note Test host with CPU, Fig. 4) and a high-bandwidth memory (HBM) stack including a dedicated test port (Note conductor coming from NVM 31, Fig. 4), wherein the boot processor (Note CPU 404, Fig. 4, when testing) is coupled to the dedicated test port of the HBM stack; wherein the boot processor, in response to executing one or more instructions of the bootloader, as part of the boot process, is capable of initiating a die crack test of the HBM stack. (Note [0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14. The test host 402 may apply the main power voltage VCC to the C11 channel terminal, apply the power voltage VCCQ to the channel terminal C12, and apply the ground voltage VSS to the remaining channel terminals C13 and C14. The ground voltage VSS applied to the channel terminal C13 may provide the hardware reset signal RST_n of the storage device 10 at a low level. Accordingly, when the storage device 10 transitions to the idle power state S330 and the first and second NVMs 30 and 31 enter the low power mode, the test host 402 may measure current flowing through the first channel terminals C11 to C14. The test host 402 may detect crack defects of the NVMs 30 and 31 based on the current measured in the first channel terminals C11 to C14. The test host 402 may determine crack defects of the NVMs 30 and 31 when the current measured in the first channel terminals C11 to C14 is greater than or equal to a test reference value.)
An et al. does not teach where the memory is HBM stack.
Kwon et al. teach where the memory is HBM stack. (Note abstract)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of the memory is HBM stack to test high performance memory in addition to standard performance memory thereby providing the ability of testing different memory devices.
Regarding claim 13, An et al. teach wherein the boot processor is capable of, in response to receiving a result of the die crack test, storing a result of the die crack test in a register. (Note, Fig. 4, test host 402 which comprises a CPU 404 which inherently has memory for storing)
Regarding claim 14, An et al. teach wherein the boot processor (CPU 404) is capable of initiating the boot process in response to a reset of the integrated circuit device. Examiner’s position is that when the test ends (Fig. 5)(interpreted as reset) and when another test begins is interpreted as initiating a boot process.(Noe par. 0077)
Regarding claim 16, An et al. teach wherein the die crack test is initiated by the boot processor (CPU 404, Fig. 4) invoking a die crack monitor (DCM) circuit (testboard 420, Fig. 4) of the HBM stack through the dedicated test port.(Note conductor leading from NVM 31 to B10 to U10 to L10 to connectors of 400. Fig. 4)
Regarding claim 15, wherein the boot processor (CPU 404), prior to initiating the die crack test of the HBM stack, initializes a memory controller (20, par. 0074) capable of communicating with the HBM stack over the dedicated test port. (Note par. 0004)
Regarding claim 11, An et al. does not teach wherein the memory device is a High-Bandwidth Memory stack.
Kwon et al. teach where the memory is HBM stack. (Note abstract)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of the memory is HBM stack to test high performance memory in addition to standard performance memory thereby providing the ability of testing different memory devices.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615) in view of Kim et al. (US 20250264529).
An et al. teach the instant invention except the following claim limitations.
Regarding claim 18, An et al. teach initiating die crack test in memory devices 30 and 31, Fig. 4 Note par. 0077 and where in each memory device 30 and 31 are tested. ([0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14.) and boot processor initiates the die crack test in the stack. (Note par. 0077)
An et al. does not teach wherein the HBM stack is one of a plurality of HBM stacks, and wherein the boot processor initiates the die crack test in each HBM stack of the plurality of HBM stacks.
Kim et al. teach wherein the HBM stack is one of a plurality of HBM stacks,(Note Fig. 15, HBM1 and HBM2) and wherein the boot processor initiates the die crack test in each HBM stack of the plurality of HBM stacks.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of wherein the HBM stack is one of a plurality of HBM stacks, and wherein the boot processor initiates the die crack test in each HBM stack of the plurality of HBM stacks to provide the testing of more complex memory devices.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615) in view of Kim et al. (US 20250264529) further in view of Lee et al. (US 20230070785).
An et al. as modified teach the instant invention except the following claim limitations.
Regarding claim 19, An et al. does not disclose wherein the die crack test of the plurality of HBM stacks is initiated in parallel.
Kim et al. teach wherein the die crack test of the plurality of HBM stacks is initiated in parallel. (Note par. 0111)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of wherein the die crack test of the plurality of HBM stacks is initiated in parallel to allow multiple test to run simultaneous. (Note par. 0111)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615) in view of Sarangi et al. (US 20190195947)
An et al. teach the instant invention except the following claim limitations.
Regarding claim 17, An et al. does not teach wherein the dedicated test port is an IEEE 1500 port.
Sarangi et al. teach wherein the dedicated test port is an IEEE 1500 port. (Note par. 0026)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of dedicated test port is an IEEE 1500 port to provide the ability to reuse test patterns and testbenches across different SoC designs, reducing the overall design and test development time.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615) in view of Wang et al. (US 20130099809).
An et teach the instant invention except the following claim limitations.
Regarding claim 20, An et al. does not teach rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack.
Wang et al. teach rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack. [0117] At a continuity check step 1041, a continuity check between the conductive pads to be tested of the wafer under test and the respective probe pins of the wafer probing system is performed. If the continuity check is not passed, the wafer under test is rejected as indicated at 1081.) (Note memory device par. 0027) Examiner’s position is that the continuity check is interpreted as the die crack test.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack to minimize the risk of providing defective devices to the customer.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Sarangi et al. (US 20190195947)
An et al. teach the instant invention except the following claim limitations.
Regarding claim 6, An et al. does not teach wherein the dedicated test port is an IEEE 1500 port.
Sarangi et al. teach wherein the dedicated test port is an IEEE 1500 port. (Note par. 0026)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of dedicated test port is an IEEE 1500 port to provide the ability to reuse test patterns and testbenches across different SoC designs, reducing the overall design and test development time.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Lee et al. (US 20230070785).
An et al. as modified teach the instant invention except the following claim limitations.
Regarding claim 8, An et al. does not disclose wherein the die crack test of the plurality of memory devices is initiated in parallel.
Kim et al. teach wherein the die crack test of the plurality of memory devices is initiated in parallel. (Note par. 0111)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of wherein the die crack test of the plurality of memory devices is initiated in parallel to allow multiple test to run simultaneous. (Note par. 0111)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Wang et al. (US 20130099809).
An et teach the instant invention except the following claim limitations.
Regarding claim 9, An et al. does not teach rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack.
Wang et al. teach rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack. [0117] At a continuity check step 1041, a continuity check between the conductive pads to be tested of the wafer under test and the respective probe pins of the wafer probing system is performed. If the continuity check is not passed, the wafer under test is rejected as indicated at 1081.) (Note memory device par. 0027) Examiner’s position is that the continuity check is interpreted as the die crack test.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack to minimize the risk of providing defective devices to the customer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEMETRIUS R PRETLOW whose telephone number is (571)272-3441. The examiner can normally be reached M-F, 5:30-1:30.
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/DEMETRIUS R PRETLOW/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858