DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been considered but are moot due to new grounds of rejections cited below.
Applicant's arguments filed 5/11/2026 regarding claims 12-10 have been fully considered but they are not persuasive. Applicant does not appear to present arguments as to how the claims distinguish from the cited art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 20240402248) in view of An et al. (US 20220102224).
Regarding claim 1, Chun et al. teach A method of operation for an integrated circuit device, the method comprising:
initiating a boot process of the integrated circuit device (Examiner interprets the test device 10 as initiating a boot process par. 0059), wherein the boot process is implemented by a boot processor (test logic 100 is interpreted as the boot processor, par. 0060) within the integrated circuit device (20, Fig. 3);
as part of the boot process, initiating, by the boot processor, a die crack test of a memory device within the integrated circuit device, (0060] In some example embodiments, when receiving the test enable signal ES, the test logic 100 may generate a test pulse signal PS by combining the test enable signal ES and the crack detection signal CDS. ) wherein the memory device (1210, Fig. is coupled to the boot processor (test logic 100, Fig. 2);
receiving, by the boot processor, a result of the die crack test of the memory device during the boot process; (Note par. 0047, In addition, the memory device 1200 may include test logic 100 and a crack detection structure 200 to detect cracks in a plurality of pads included in the memory device 1200.) and
Chun et al. does not explicitly teach storing the result of the die crack test in a register of the integrated circuit device.
An et al. teach storing the result of the die crack test in a register of the integrated circuit device. (Examiner takes the position that cpu 404 inherently has memory for storing which would implicitly teach a register)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of storing the result of the die crack test in a register of the integrated circuit device so that the data can be used by the cpu to determine a pass of failure of the test operation. (Note An et al. par. 0078)
Regarding claim 2, Che et al. does not explicitly teach wherein the boot process is implemented by the boot processor executing a bootloader for the integrated circuit device, wherein the bootloader includes instructions that, upon execution, initiate the die crack test.
An et al. teach wherein the boot process is implemented by the boot processor (cpu 404, Fig. 4)executing a bootloader for the integrated circuit device, wherein the bootloader includes instructions that, upon execution, initiate the die crack test.
[0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of wherein the boot process is implemented by the boot processor executing a bootloader for the integrated circuit device, wherein the bootloader includes instructions that, upon execution, initiate the die crack test so that the memory devices can be tested.
Regarding claim 3, Chun et al. does not teach wherein the initiating the boot process is performed in response to a reset of the integrated circuit device.
An et al. teach wherein the initiating the boot process is performed in response to a reset of the integrated circuit device. Examiner’s position is that when the test ends (Fig. 5) (interpreted as reset) and when another test begins is interpreted as initiating a boot process.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of initiating the boot process is performed in response to a reset of the integrated circuit device to start a new testing process.
Regarding claim 4, Chun et al. does not teach wherein the die crack test is initiated by the boot processor (test logic 100)
Chun et al. does not teach invoking a die crack monitor (DCM) circuit of the memory device through a dedicated test port of the memory device.
An et al. wherein the die crack test is initiated by the boot processor (CPU 404, Fig. 4) invoking a die crack monitor (DCM) circuit (testboard 420, Fig. 4) of the memory device through a dedicated test port of the memory device. (Note conductor leading from NVM 31 to B10 to U10 to L10 to connectors of 400. Fig. 4)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of invoking a die crack monitor (DCM) circuit of the memory device through a dedicated test port of the memory device to provide communication between the circuits.
Regarding claim 5, Chun et al. does not teach prior to initiating the die crack test of the memory device, initializing, by the boot processor, a memory controller configured to communicate with the memory device over the dedicated test port.
An et al. teach prior to initiating the die crack test of the memory device, initializing, by the boot processor (CPU 404), a memory controller (20, par. 0074) configured to communicate with the memory device over the dedicated test port.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of teach prior to initiating the die crack test of the memory device, initializing, by the boot processor, a memory controller configured to communicate with the memory device over the dedicated test port so that the test can be directed to the correct device.
Regarding claim 6, Chun et al. does not teach wherein the dedicated test port is configured as a design for testability. (Note package balls B10 and B20, Fig. 4)
Regarding claim 7, Chun et al. does not teach wherein the memory device is one of a plurality of memory devices of the integrated circuit device, and wherein the method comprises: initiating the die crack test in each of the plurality of memory devices of the integrated circuit device.
An et al. teach wherein the memory device is one of a plurality of memory devices (Note 30 and 31, Fig. 4) of the integrated circuit device, and wherein the method comprises: initiating the die crack test in each of the plurality of memory devices of the integrated circuit device. (Note [0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14. The test host 402 may apply the main power voltage VCC to the C11 channel terminal, apply the power voltage VCCQ to the channel terminal C12, and apply the ground voltage VSS to the remaining channel terminals C13 and C14. The ground voltage VSS applied to the channel terminal C13 may provide the hardware reset signal RST_n of the storage device 10 at a low level. Accordingly, when the storage device 10 transitions to the idle power state S330 and the first and second NVMs 30 and 31 enter the low power mode, the test host 402 may measure current flowing through the first channel terminals C11 to C14. The test host 402 may detect crack defects of the NVMs 30 and 31 based on the current measured in the first channel terminals C11 to C14. The test host 402 may determine crack defects of the NVMs 30 and 31 when the current measured in the first channel terminals C11 to C14 is greater than or equal to a test reference value.)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of wherein the memory device is one of a plurality of memory devices of the integrated circuit device, and wherein the method comprises: initiating the die crack test in each of the plurality of memory devices of the integrated circuit device to determine if each memory device is damaged or not.
Regarding claim 10, Chun et al. teach wherein the memory device is a memory chiplet. (Note 1210 Fig. 2 is interpreted as memory chiplet)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 20240402248) in view of An et al. (US 20220102224) further in view of Lee et al. (US 20230070785).
Chun et al. as modified teach the instant invention except the following claim limitations.
Regarding claim 8, Chun et al. does not disclose wherein the die crack test of the plurality of memory devices is initiated in parallel.
Lee et al. teach wherein the die crack test of the plurality of memory devices is initiated in parallel. (Note par. 0111)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of wherein the die crack test of the plurality of memory devices is initiated in parallel to allow multiple test to run simultaneous. (Note par. 0111)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 20240402248) in view of An et al. (US 20220102224) further in view of Wang et al. (US 20130099809).
Chun et teach the instant invention except the following claim limitations.
Regarding claim 9, Chun et al. does not teach rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack.
Wang et al. teach rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack. [0117] At a continuity check step 1041, a continuity check between the conductive pads to be tested of the wafer under test and the respective probe pins of the wafer probing system is performed. If the continuity check is not passed, the wafer under test is rejected as indicated at 1081.) (Note memory device par. 0027) Examiner’s position is that the continuity check is interpreted as the die crack test.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack to minimize the risk of providing defective devices to the customer.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 20240402248) in view of An et al. (US 20220102224) further in view of Kwon et al. (US 20210193615).
Regarding claim 11, Chun et al. does not teach wherein the memory device is a High-Bandwidth Memory stack.
Kwon et al. teach where the memory is HBM stack. (Note abstract)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Chun et al. to include the teaching of the memory is HBM stack to test high performance memory in addition to standard performance memory thereby providing the ability of testing different memory devices.
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615).
Regarding claim 12, An et al. teach an integrated circuit device (Note the elements of Fig. 4 is interpreted as an integrated circuit device), comprising: a boot processor configured to implement a boot process by executing a bootloader; (Note Test host with CPU, Fig. 4) and a high-bandwidth memory (HBM) stack including a dedicated test port (Note conductor coming from NVM 31, Fig. 4), wherein the boot processor (Note CPU 404, Fig. 4, when testing) is coupled to the dedicated test port of the HBM stack; wherein the boot processor, in response to executing one or more instructions of the bootloader, as part of the boot process, is configured to initiate die crack test of the HBM stack. (Note [0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14. The test host 402 may apply the main power voltage VCC to the C11 channel terminal, apply the power voltage VCCQ to the channel terminal C12, and apply the ground voltage VSS to the remaining channel terminals C13 and C14. The ground voltage VSS applied to the channel terminal C13 may provide the hardware reset signal RST_n of the storage device 10 at a low level. Accordingly, when the storage device 10 transitions to the idle power state S330 and the first and second NVMs 30 and 31 enter the low power mode, the test host 402 may measure current flowing through the first channel terminals C11 to C14. The test host 402 may detect crack defects of the NVMs 30 and 31 based on the current measured in the first channel terminals C11 to C14. The test host 402 may determine crack defects of the NVMs 30 and 31 when the current measured in the first channel terminals C11 to C14 is greater than or equal to a test reference value.)
An et al. does not teach where the memory is HBM stack.
Kwon et al. teach where the memory is HBM stack. (Note abstract)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of the memory is HBM stack to test high performance memory in addition to standard performance memory thereby providing the ability of testing different memory devices.
Regarding claim 13, An et al. teach wherein the boot processor is in response to receiving a result of the die crack test, storing a result of the die crack test in a register. (Note, Fig. 4, test host 402 which comprises a CPU 404 which inherently has memory for storing)
Regarding claim 14, An et al. teach wherein the boot processor (CPU 404) is configured to initiate the boot process in response to a reset of the integrated circuit device. Examiner’s position is that when the test ends (Fig. 5)(interpreted as reset) and when another test begins is interpreted as initiating a boot process.(Noe par. 0077)
Regarding claim 16, An et al. teach wherein the die crack test is initiated by the boot processor (CPU 404, Fig. 4) invoking a die crack monitor (DCM) circuit (testboard 420, Fig. 4) of the HBM stack through the dedicated test port.(Note conductor leading from NVM 31 to B10 to U10 to L10 to connectors of 400. Fig. 4)
Regarding claim 15, wherein the boot processor (CPU 404), prior to initiating the die crack test of the HBM stack, initializes a memory controller (20, par. 0074) configured to communicate with the HBM stack over the dedicated test port. (Note par. 0004)
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615) in view of Kim et al. (US 20250264529).
An et al. teach the instant invention except the following claim limitations.
Regarding claim 18, An et al. teach initiating die crack test in memory devices 30 and 31, Fig. 4 Note par. 0077 and where in each memory device 30 and 31 are tested. ([0077] The test host 402 may test whether the crack 32 of the NVMs 30 and 31 of the MCP 10 is defective using the first channel terminals C11 to C14.) and boot processor initiates the die crack test in the stack. (Note par. 0077)
An et al. does not teach wherein the HBM stack is one of a plurality of HBM stacks, and wherein the boot processor initiates the die crack test in each HBM stack of the plurality of HBM stacks.
Kim et al. teach wherein the HBM stack is one of a plurality of HBM stacks,(Note Fig. 15, HBM1 and HBM2) and wherein the boot processor initiates the die crack test in each HBM stack of the plurality of HBM stacks.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of wherein the HBM stack is one of a plurality of HBM stacks, and wherein the boot processor initiates the die crack test in each HBM stack of the plurality of HBM stacks to provide the testing of more complex memory devices.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615) in view of Kim et al. (US 20250264529) further in view of Lee et al. (US 20230070785).
An et al. as modified teach the instant invention except the following claim limitations.
Regarding claim 19, An et al. does not disclose wherein the die crack test of the plurality of HBM stacks is initiated in parallel.
Kim et al. teach wherein the die crack test of the plurality of HBM stacks is initiated in parallel. (Note par. 0111)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of wherein the die crack test of the plurality of HBM stacks is initiated in parallel to allow multiple test to run simultaneous. (Note par. 0111)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615) in view of Sarangi et al. (US 20190195947)
An et al. teach the instant invention except the following claim limitations.
Regarding claim 17, An et al. does not teach wherein the dedicated test port is an IEEE 1500 port.
Sarangi et al. teach wherein the dedicated test port is an IEEE 1500 port. (Note par. 0026)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of dedicated test port is an IEEE 1500 port to provide the ability to reuse test patterns and testbenches across different SoC designs, reducing the overall design and test development time.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20220102224) in view of Kwon et al. (US 20210193615) in view of Wang et al. (US 20130099809).
An et teach the instant invention except the following claim limitations.
Regarding claim 20, An et al. does not teach rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack.
Wang et al. teach rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack. [0117] At a continuity check step 1041, a continuity check between the conductive pads to be tested of the wafer under test and the respective probe pins of the wafer probing system is performed. If the continuity check is not passed, the wafer under test is rejected as indicated at 1081.) (Note memory device par. 0027) Examiner’s position is that the continuity check is interpreted as the die crack test.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify An et al. to include the teaching of rejecting the integrated circuit device in response to the result of the die crack test of the memory device indicating a die crack to minimize the risk of providing defective devices to the customer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DEMETRIUS R PRETLOW/ Examiner, Art Unit 2858
/LEE E RODAK/ Supervisory Patent Examiner, Art Unit 2858
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