DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Information disclosure statements filed 28 June 2024, 9 July 2024, and 19 August 2024 have been fully considered.
Specification
The abstract of the disclosure is objected to because it appears to describe the specific patentably distinct invention of parent app. no. 16/941170 rather than either a generic disclosed invention or the specific claimed invention of the instant application. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 1 and 9 are objected to because of the following informalities:
Claim 1 recites the limitation, “the gate structure comprising at least one gate electrode layer and at least one interlayer insulation layers.” This appears to contain a typographical error and may be corrected as, “the gate structure comprising at least one gate electrode layer and at least one interlayer insulation layer[[s]].”
Claim 9 recites the limitation, “The nonvolatile memory device of claim 5, the nonvolatile memory device further comprises.” This appears to contain a typographical error with the redundant recitation of the term “nonvolatile memory device” and may be corrected as, “The nonvolatile memory device of claim 5, ing.”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5, and 13 of U.S. Patent No. 11,114,504. Although the claims at issue are not identical, they are not patentably distinct from each other.
With respect to claim 1, U.S. Patent No. 11,114,504 claims a nonvolatile memory device as claimed, comprising:
a substrate (claim 1, clause 1);
a gate structure disposed on the substrate, the gate structure comprising at least one gate electrode layer and at least one interlayer insulation layers that are alternately stacked (claim 1, clause 2);
a hole pattern penetrating the gate structure on the substrate (claim 1, clause 3);
a resistance change layer covering a sidewall surface of the gate structure in the hole pattern and comprising a variable resistance material (claim 1, clause 4); and
a channel layer disposed to cover the resistance change layer in the hole pattern (claim 1, clause 4).
With respect to claim 2, U.S. Patent No. 11,114,504 claims further comprising: a channel lower contact layer, contacting an end of the channel layer and electrically connected to a source electrode; and a channel upper contact layer, contacting the other end of the channel layer in a direction perpendicular to the substrate and electrically connected to a drain electrode (claim 5).
With respect to claim 3, U.S. Patent No. 11,114,504 claims further comprising a gate insulation layer disposed between the sidewall surface of the gate structure in the hole pattern and the resistance change layer (claim 13).
With respect to claim 4, U.S. Patent No. 11,114,504 claims wherein the resistance change layer comprises movable oxygen vacancies or movable metal ions (claims 1 and 2).
Claims 1, 3, and 4 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, and 7 of U.S. Patent No. 11,362,143. Although the claims at issue are not identical, they are not patentably distinct from each other.
With respect to claim 1, U.S. Patent No. 11,362,143 claims a nonvolatile memory device as claimed, comprising:
a substrate (claim 1, clause 1);
a gate structure disposed on the substrate, the gate structure comprising at least one gate electrode layer and at least one interlayer insulation layers that are alternately stacked (claim 1, clause 2);
a hole pattern penetrating the gate structure on the substrate (claim 1, clause 2);
a resistance change layer covering a sidewall surface of the gate structure in the hole pattern and comprising a variable resistance material (claim 1, clause 4; claim 6); and
a channel layer disposed to cover the resistance change layer in the hole pattern (claim 1, clause 5).
With respect to claim 3, U.S. Patent No. 11,362,143 claims further comprising a gate insulation layer disposed between the sidewall surface of the gate structure in the hole pattern and the resistance change layer (claim 1, clause 3; claim 6).
With respect to claim 4, U.S. Patent No. 11,362,143 claims wherein the resistance change layer comprises movable oxygen vacancies or movable metal ions (claim 7).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 3, and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation, “the other end of the channel layer.” There is insufficient antecedent basis for this limitation in the claim. It is unclear which other end of the channel layer the claim refers.
Claim 3 recites the limitation, “the sidewall surface of the gate structure.” There is insufficient antecedent basis for this limitation in the claim. It is unclear which sidewall surface the claim refers.
Claim 6 recites the limitation, “wherein the first resistive material layer is a higher resistive body than the second resistive material layer.” It is unclear as to what the term “higher” in the claim refers (e.g. spatially higher, higher in concentration, higher in resistivity, etc.). For the purposes of applying art, the term “higher” will mean higher resistivity.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh et al. (US Patent Application Publication 2017/0162578, hereinafter Noh ‘578).
With respect to claim 1, Noh ‘578 teaches (FIG. 13) a nonvolatile memory device as claimed, comprising:
a substrate (100) ([0041]);
a gate structure (110 and 150U) disposed on the substrate (100), the gate structure comprising at least one gate electrode layer (150U) and at least one interlayer insulation layers (110) that are alternately stacked ([0042, 0087]);
a hole pattern (H) penetrating the gate structure (110 and 150U) on the substrate (100) ([0047]);
a resistance change layer (120) covering a sidewall surface of the gate structure (110 and 150U) in the hole pattern (H) and comprising a variable resistance material ([0110]); and
a channel layer (130) disposed to cover the resistance change layer (120) in the hole pattern (H) ([0070]).
With respect to claim 3, Noh ‘578 teaches further comprising a gate insulation layer (144) disposed between the sidewall surface of the gate structure (110 and 150U) in the hole pattern (H) and the resistance change layer (120) ([0087]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Noh ‘578 as applied to claim 1 above, and further in view of Lee (US Patent Application Publication 2017/0263620, hereinafter Lee ‘620).
With respect to claim 2, Noh ‘578 teaches the device as described in claim 1 above with the exception of the additional limitation further comprising: a channel lower contact layer, contacting an end of the channel layer and electrically connected to a source electrode; and a channel upper contact layer, contacting the other end of the channel layer in a direction perpendicular to the substrate and electrically connected to a drain electrode.
However, Lee ‘620 teaches (FIG. 3) a nonvolatile memory device comprising a channel lower contact layer (SSL), contacting an end of a channel layer (CH) and electrically connected to a source electrode; and a channel upper contact layer (DSL), contacting the other end of the channel layer in a direction perpendicular to a substrate (400) and electrically connected to a drain electrode to provide to the channel a flow of charge carriers to operate the memory ([0041-0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the nonvolatile memory device of Noh ‘578 further comprising: a channel lower contact layer, contacting an end of the channel layer and electrically connected to a source electrode; and a channel upper contact layer, contacting the other end of the channel layer in a direction perpendicular to the substrate and electrically connected to a drain electrode as taught by Lee ‘620 to provide to the channel a flow of charge carriers to operate the memory.
Claims 4-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Noh ‘578 as applied to claim 1 above, and further in view of Takahashi (US Patent Application Publication 2011/0001110, hereinafter Takahashi ‘110) of record.
With respect to claims 4-7, Noh ‘578 teaches the device as described in claim 1 above with the exception of the additional limitation wherein the resistance change layer comprises movable oxygen vacancies or movable metal ions; wherein the resistance change layer comprises: a first resistive material layer contacting the channel layer; and a second resistive material layer disposed on the first resistive material layer, wherein the first resistive material layer has a lower concentration of oxygen vacancies or a lower concentration of movable metal ions than the second resistive material layer; wherein the first resistive material layer is a higher resistive body than the second resistive material layer; and wherein the resistance change layer has a concentration of oxygen vacancies or a concentration of metal ions which increases from a region adjacent to an interface with the channel layer to a region adjacent to an interface with the gate structure.
However, Takahashi ‘110 teaches (FIGs. 7A and 7B) a nonvolatile resistance change memory comprising a resistance change layer (11) having a pair of resistive materials (8 and 9) stacked on a substrate (3), wherein a concentration of movable oxygen vacancies or movable metal ions, and thus the corresponding resistivity, may be selected to have an increasing concentration from a first interface between the resistance change layer and the substrate to a second interface between the resistance change layer and an electrode layer (1) ([0080-0081]) to effectively control or select the ON/OFF resistances of the memory device ([0075-0079]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the resistance change layer of Noh ‘578 comprising movable oxygen vacancies or movable metal ions; wherein the resistance change layer comprises: a first resistive material layer contacting the channel layer; and a second resistive material layer disposed on the first resistive material layer, wherein the first resistive material layer has a lower concentration of oxygen vacancies or a lower concentration of movable metal ions than the second resistive material layer; wherein the first resistive material layer is a higher resistive body than the second resistive material layer; and wherein the resistance change layer has a concentration of oxygen vacancies or a concentration of metal ions which increases from a region adjacent to an interface with the channel layer to a region adjacent to an interface with the gate structure as taught by Takahashi ‘110 to effectively control or select the ON/OFF resistances of the memory device.
With respect to claim 9, Noh ‘578 and Takahashi ‘110 teach the device as described in claim 5 above, but primary reference Noh ‘578 does not explicitly teach the additional limitation the nonvolatile memory device further comprises: first and second trigger filaments formed in the first resistive material layer; and a connecting filament formed in the second resistive material layer, the connecting filament connecting the first and second trigger filaments, wherein diameters of the first and second trigger filaments are greater than a diameter of the connecting filament.
However, the combination of Noh ‘578 in view of Takahashi ‘110 would result in the nonvolatile memory device further comprising: first and second trigger filaments formed in the first resistive material layer; and a connecting filament formed in the second resistive material layer, the connecting filament connecting the first and second trigger filaments, wherein diameters of the first and second trigger filaments are greater than a diameter of the connecting filament as claimed. This is because the formation of trigger filaments formed in the first resistive material layer and a connecting filament formed in the second resistive material layer, and their accompanying characteristics, occurs as a byproduct of application of voltage to the memory device. See paragraphs [0041-0042, 0045-0046] of Applicant’s specification. Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Further, while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the nonvolatile memory device of Noh ‘578 and Takahashi ‘110 further comprising: first and second trigger filaments formed in the first resistive material layer; and a connecting filament formed in the second resistive material layer, the connecting filament connecting the first and second trigger filaments, wherein diameters of the first and second trigger filaments are greater than a diameter of the connecting filament as a byproduct of application of voltage to said memory device.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the nonvolatile memory device of claim 8 in the combination of limitations as claimed, noting particularly the limitation, “wherein a thickness of the first resistive material layer is less than a thickness of the second resistive material layer,” in combination with at least, “wherein the first resistive material layer has a lower concentration of oxygen vacancies or a lower concentration of movable metal ions than the second resistive material layer,” of claim 5 off which the claim depends.
Noh ‘578 and Takahashi ‘110 represent the closest prior art of record. See the 35 U.S.C. 103 rejection of claim 5 above. However, Noh ‘578 is silent to wherein the resistance change layer has a first resistive material land and a second resistive material layer. Takahashi ‘110 teaches (FIGs. 7A and 7B) a nonvolatile resistance change memory comprising a resistance change layer (11) having a pair of resistive materials (8 and 9) stacked on a substrate (3), wherein a concentration of movable oxygen vacancies or movable metal ions, and thus the corresponding resistivity, may be selected to have an increasing concentration from a first interface between the resistance change layer and the substrate to a second interface between the resistance change layer and an electrode layer (1) ([0080-0081]) to effectively control or select the ON/OFF resistances of the memory device ([0075-0079]). However, FIG. 7A and 7B of Takahashi ‘110 show the first resistive material layer (one of 8 or 9) having a same thickness as the second resistive material layer (the other of 8 or 9), not a lesser thickness as claimed. One of ordinary skill in the art could look to FIG. 8 of Takahashi ‘110 as teaching a thickness of the first resistive material layer (8) is less than a thickness of the second resistive material layer (9 and 10). However, because the first resistive material layer (8) has a lower oxygen concentration than the second resistive material layer (9 and 10), it can be presumed that said first resistive material layer (8) has a greater concentration of oxygen vacancies or a greater concentration of movable metal ions compared with the second resistive material layer (9 or 10), not a lower concentration of oxygen vacancies or a lower concentration of movable metal ions as claimed.
Sung (US Patent Application Publication 2010/0258778) of record teaches (FIG. 2) a thickness of a first resistive material layer (25) is less than a thickness of a second resistive material layer (26) ([0041]). However, the first resistive material layer (25) has a greater concentration of vacancies than the second resistive material layer (26), not a lower concentration of vacancies (39) as claimed.
Han et al. (US Patent Application Publication 2021/0202835) of record teaches (FIG. 13) a nonvolatile memory device comprising a first resistive material (320a) and a second resistive material (320b) ([0073]). However, this reference is not prior art under 35 U.S.C. 102(a)(1) because it was not published prior to the effective filing date of the claimed invention, and is not prior art under 35 U.S.C. 102(a)(2) because it does not name another inventor.
Conclusion
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/C.M.R./Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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