DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendments, filed on 05/11/2026, have been received and made of record. In response to the most recent Office Action, dated 02/11/2026, claims 1, 6-7, 10 and 14-15 have been amended.
Claims 1-15 are currently pending.
Response to Arguments
Applicant’s amendments, filed on 05/11/2026, have been entered and fully considered. In light of the amendments, the rejection(s) have been withdrawn. However, upon further consideration, a new ground(s) of rejection(s) have been made, and applicant's arguments are rendered moot.
Claim Rejections - 35 USC § 112(a)
Claims 1-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, claim 1 recites, inter alia, “wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage” which is a limitation that does not have support from the application as originally filed. Specifically, the specification does not recite the language of “positive polarity” nor does it use the terms of “positive” or “polarity” separately either. The specification describes sampling and holding a peak value of a sense signal indicative of current flowing through the power stage, however, it does not disclose that the sense signal or the peak value associated with the sense signal has a positive polarity, or that positive polarity represents current flowing from the input voltage to the output voltage. The term “positive polarity” without proper support from the disclosure could mean many things to one or ordinary skill in the art such as (1) the physical direction of the current, (2) the algebraic sign of the sense signal, (3) the voltage stored by the sample and hold circuit is a positive voltage or (4) the polarity of the converter’s switching interval. The Applicant is trying to use this terminology to mean that it is obvious to mean only definition (1) in some manner, however, this term can mean many things to a person of ordinary skill in the art and thus needs to have proper support from the specification. Accordingly, the new limitations add new matter which does not have support from the originally presented disclosure and is therefore rejected under 35 U.S.C. 112(a) for failing to comply with the written description requirement.
However, for purposes of examination the Examiner has taken the interpretation that the limitation “wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage” means that wherein the sense signal and thus the peak value of the sense signal is a positive current value that flows between the input voltage and the output voltage.
Claims 2-6 depend upon claim 1 and therefore inherit the deficiencies of claim 1 and thus are also rejected under 35 U.S.C. 112(a).
Regarding claim 7, claim 7 recites, inter alia, “wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage” which is a limitation that does not have support from the application as originally filed. Specifically, the specification does not recite the language of “positive polarity” nor does it use the terms of “positive” or “polarity” separately either. The specification describes sampling and holding a peak value of a sense signal indicative of current flowing through the power stage, however, it does not disclose that the sense signal or the peak value associated with the sense signal has a positive polarity, or that positive polarity represents current flowing from the input voltage to the output voltage. The term “positive polarity” without proper support from the disclosure could mean many things to one or ordinary skill in the art such as (1) the physical direction of the current, (2) the algebraic sign of the sense signal, (3) the voltage stored by the sample and hold circuit is a positive voltage or (4) the polarity of the converter’s switching interval. The Applicant is trying to use this terminology to mean that it is obvious to mean only definition (1) in some manner, however, this term can mean many things to a person of ordinary skill in the art and thus needs to have proper support from the specification. Accordingly, the new limitations add new matter which does not have support from the originally presented disclosure and is therefore rejected under 35 U.S.C. 112(a) for failing to comply with the written description requirement.
However, for purposes of examination the Examiner has taken the interpretation that the limitation “wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage” means that wherein the sense signal and thus the peak value of the sense signal is a positive current value that flows between the input voltage and the output voltage.
Claims 8 and 9 depend upon claim 7 and therefore inherit the deficiencies of claim 7 and thus are also rejected under 35 U.S.C. 112(a).
Regarding claim 10, claim 10 recites, inter alia, “wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage” which is a limitation that does not have support from the application as originally filed. Specifically, the specification does not recite the language of “positive polarity” nor does it use the terms of “positive” or “polarity” separately either. The specification describes sampling and holding a peak value of a sense signal indicative of current flowing through the power stage, however, it does not disclose that the sense signal or the peak value associated with the sense signal has a positive polarity, or that positive polarity represents current flowing from the input voltage to the output voltage. The term “positive polarity” without proper support from the disclosure could mean many things to one or ordinary skill in the art such as (1) the physical direction of the current, (2) the algebraic sign of the sense signal, (3) the voltage stored by the sample and hold circuit is a positive voltage or (4) the polarity of the converter’s switching interval. The Applicant is trying to use this terminology to mean that it is obvious to mean only definition (1) in some manner, however, this term can mean many things to a person of ordinary skill in the art and thus needs to have proper support from the specification. Accordingly, the new limitations add new matter which does not have support from the originally presented disclosure and is therefore rejected under 35 U.S.C. 112(a) for failing to comply with the written description requirement.
However, for purposes of examination the Examiner has taken the interpretation that the limitation “wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage” means that wherein the sense signal and thus the peak value of the sense signal is a positive current value that flows between the input voltage and the output voltage.
Claims 11-15 depend upon claim 10 and therefore inherit the deficiencies of claim 10 and thus are also rejected under 35 U.S.C. 112(a).
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yukawa (CN 116131606 A – Translation Attached) in view of Kim (KR 102195245 B1 – Translation Attached) and in further view of Nguyen (US 2017/0338739 A1) .
Regarding claim 1, Yukawa teaches a switching mode power supply (Figure 2; Figure 2 has been annotated below as Figure 2A for purposes of clarity), comprising: a power stage (Figure 2A Component PS), including a high side power switch (Figure 2A Component HS) and a low side power switch (Figure 2A Component LS), configured to be periodically turned on and off (Translation Paragraph 41 highlights that control signals control the turning on and off of Components HS and LS; This is a basic operation of a buck converter high side switch on for one period and the low side switch on for a second period within a switching cycle), to convert an input voltage (Figure 2A Component Vin) to an output voltage (Figure 2A Component Vout); a sample and hold circuit (Figure 2A Component SH; Figure 5 is a detailed figure of the configuration of Component SH; Translation Paragraph 57 “FIG. 5 is a schematic circuit diagram of a sample and hold circuit”), configured to receive a sense signal indicative of a current flowing through the power stage (Figure 2A Component VCS; Translation Paragraph 45 “The sample and hold circuit is used to receive the low-side control signal CTRL2 and the current sampling signal VCS, and generate a specific value S/H of the current sampling signal VCS according to the low-side control signal CTRL2 and the current sampling signal VCS”), and to sample and hold a peak value of the sense signal (Translation Paragraph 57 “the specific value of the current sampling signal includes the peak value of the current sampling signal”), to generate a sample and hold signal (Figure 2A Component S/H); an amplifying circuit (Figure 2A Component AC), configured to amplify a difference between the sample and hold signal and a reference current (Figure 2A Component Iref; Component EA amplifies the difference between Components S/H and Iref), to generate an adjust reference signal (Figure 2A Component New_valleyref); a comparing circuit (Figure 2A Component COMP; Translation Paragraph 44 “a first comparator”), configured to compare the adjust reference signal with the sense signal (Figure 2A Component COMP compares Component New_valleyref with Component VCS), to generate a comparison signal (Figure 2A Component Valley); and a logical circuit (Figure 2A Component 11; Component 11 is seen in further detail in Figure 3; Figure 3 Component & can be seen as a logical circuit), configured to generate a control signal in response to the comparison signal (Figure 3 Component TOFF).
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Yukawa does not teach wherein the amplifying circuit is configured to find a difference between the sample and hold signal and a reference voltage; and wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage.
Kim teaches a switching mode power supply (Figure 2) including a power stage (Figure 2 Components M+W1+W2+D1+C1) converting an input voltage (Figure 2 Component Vin) to an output voltage (Figure 2 Component Vout); a sample and hold circuit (Figure 2 Component 121; Translation Paragraph 0053 “when the time point of the falling edge of the second detection voltage VS is detected, the sampling/holder 121 outputs the held voltage as the predicted voltage signal EV”) configured to receives a sensed signal (Figure 2 Component VS) and to generate a sample and hold signal (Figure 2 Component EV); an amplifying circuit (Figure 2 Component 139), configured to amplify a difference between the sample and hold signal and a reference voltage (Figure 2 Component VR2; Component 139 amplifies the difference between Components EV and VR2), to generate an adjust reference signal (Figure 2 Component EVAE).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate using a reference voltage instead as taught by Kim. The advantage of this design is that the standard norm in feedback circuits utilizing error amplifiers and comparators is to use voltage references and voltage domain implementations thus reducing the circuit complexity and improving implementation robustness.
Nguyen teaches a DC/DC buck converter (Figure 4), comprising: a power stage (Figure 4 Components N1+N2), including a high side power switch (Figure 4 Component N1) and a low side power switch (Figure 4 Component N2), configured to be periodically turned on and off, to convert an input voltage to an output voltage (Paragraph 0018 “The high side driver 101 turns ON the high side switch N1 and the low side driver 102 turns OFF the low side switch N2 to connect the switch node SW to the input voltage. The high side driver 101 turns OFF the high side switch N1 and the low side driver 102 turns ON the low side switch N2 to connect the switch node SW to ground”); a sample and hold circuit (Figure 4 Component 301), configured to receive a sense signal indicative of a current flowing through the power stage, and to sample and hold a peak value of the sense signal (Paragraph 0028 “When the transistors MP3 and MP4 are ON and the transistor MP5 is OFF, the positive inductor current is mirrored by the transistor MP1 to charge the capacitor C2, allowing the peak (i.e., highest point or value) of the positive inductor current to be stored as charge in the capacitor C2 when the transistor MP4 is turned OFF”), wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage (See 112(a) Rejection For Interpretation; Paragraph 0017 “The inductor current (IL), i.e., the current through the output inductor L1, is positive (+IL) when the inductor current flows from the switch node SW to the output node 104”; Paragraph 0028 “When the transistors MP3 and MP4 are ON and the transistor MP5 is OFF, the positive inductor current is mirrored by the transistor MP1 to charge the capacitor C2, allowing the peak (i.e., highest point or value) of the positive inductor current to be stored as charge in the capacitor C2 when the transistor MP4 is turned OFF”; Claim 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate a current sampling circuit to sample and hold a positive polarity peak signal representing the forward inductor current flowing from the input to the output as taught by Nguyen. The advantage of this modification that it would improve the reliability of Yukawa’s current-limit control and help prevent excessive forward peak current from overloading the power components within the circuit therefore improving overcurrent protection.
Regarding claim 2, Yukawa, Kim and Nguyen teach all the limitations of claim 1. Yukawa further teaches wherein the sample and hold circuit (Figure 2A Component SH is seen in further detail in Figure 5) comprises: a sample switch (Figure 5 Component 53) and a sample capacitor (Figure 5 Component 52), wherein the sample switch is configured to be turned on when the current flowing through the power stage is going to decrease from its peak value, so that the peak value of the sense signal is delivered to the sample capacitor (Translation Paragraph 57 highlights that the sample switch 53 turns on based on the single pulse generator 51 which is triggered when a switching transition happens and a switching transition means the current flowing is going to decrease as the switch is no longer providing current to that point).
Regarding claim 3, Yukawa, Kim and Nguyen teach all the limitations of claim 1. Yukawa does not teach wherein: the logical circuit is configured to generate the control signal in response to the comparison signal and a clock signal, wherein the logical circuit is configured to generate the control signal to control the current flowing through the power stage to increase in response to the clock signal, and is configured to generate the control signal to control the current flowing through the power stage to decrease in response to the comparison signal.
Kim teaches a switching mode power supply (Figure 2) including a power stage (Figure 2 Components M+W1+W2+D1+C1) converting an input voltage (Figure 2 Component Vin) to an output voltage (Figure 2 Component Vout); a sample and hold circuit (Figure 2 Component 121; Translation Paragraph 0053 “when the time point of the falling edge of the second detection voltage VS is detected, the sampling/holder 121 outputs the held voltage as the predicted voltage signal EV”) configured to receives a sensed signal (Figure 2 Component VS) and to generate a sample and hold signal (Figure 2 Component EV); an amplifying circuit (Figure 2 Component 139), configured to amplify a difference between the sample and hold signal and a reference voltage (Figure 2 Component VR2; Component 139 amplifies the difference between Components EV and VR2), to generate an adjust reference signal (Figure 2 Component EVAE); a comparing circuit (Figure 2 Component 107), configured to compare the adjust reference signal with a current sense signal (Figure 2 Component 107 compares Components EVAE and CS), to generate a comparison signal (Figure 2 Component CP2); and a logical circuit (Figure 2 Component 103), configured to generate a control signal in response to the comparison signal (Figure 2 Component QS is generated in response to Component CP2); wherein: the logical circuit is configured to generate the control signal in response to the comparison signal and a clock signal (Figure 2 Component QS is generated in response to Components CLK, a clock signal, and CP2 through Component 105), wherein the logical circuit is configured to generate the control signal to control the current flowing through the power stage to increase in response to the clock signal (Figure 2 Component QS is set based on the clock signal thus increases based on the clock signal therefore it turns on Component M increasing the current; Translation Paragraph 0061 “the SR latch 103 outputs a high-level switch signal QS at the time of the rising edge of the clock signal CLK. Then, the gate signal GC becomes a high level, and the gate driver 100 generates a high level gate voltage VG”), and is configured to generate the control signal to control the current flowing through the power stage to decrease in response to the comparison signal (Figure 2 Component QS is reset based on Component CP2 which in turn turns off Component M thus decreasing the current flowing through; Translation Paragraph 0060 “The SR latch 103 outputs a low-level switch signal QS in synchronization with the rising edge of the comparison signal CP. Then, the gate signal GC becomes a low level and the gate driver 100 generates a low level gate voltage VG. Therefore, the power switch M is turned off”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate using comparator, latch, clock control structure as taught by Kim. The advantage of this design is the comparator, latch, clock control structure ensures proper switching transitions and prevent false switching events caused by comparator noise or ripple in sensed signals and thus would improve switching stability and control reliability.
Regarding claim 4, Yukawa, Kim and Nguyen teach all the limitations of claim 1. Yukawa further teaches a driver (Figure 2A Component 11 is seen in detail in Figure 3; Translation Paragraph 54 “FIG. 3 shows a schematic diagram of a circuit principle of the logic unit 11”; Translation Paragraph 55 “one embodiment, the output terminal of the RS flip-flop will be coupled to the gate of the MOS transistor through the driving circuit”; This passage shows that although not shown a driving circuit is present), configured to generate a high side drive signal and a low side drive signal in response to the control signal (Figure 2A Components CTRL1 and CTRL2 are based off Component TOFF), to respectively control the high side power switch and the low side power switch (Figure 2A Components HS and LS are controlled by Components CTRL1 and CTRL2, respectively).
Regarding claim 5, Yukawa, Kim and Nguyen teach all the limitations of claim 4. Yukawa further teaches a short pulse generator (Figure 2A Component SH is seen in further detail in Figure 5; Figure 5 Component 51; Translation Paragraph 57 “sample and hold circuit includes a single pulse signal generator 51”), configured to generate a short pulse signal in response to the low side drive signal or the high side drive signal (Translation Paragraph 57 “The single-pulse signal generator 51 is used for receiving the low-side control signal CTRL2, and generating a single-pulse signal when the low-side control signal CTRL2 changes from the first logic state to the second logic state”), to control the sample and hold circuit to sample and hold the peak value of the sense signal (Figure 5 Component 51 controls switch 52 which holds the peak value of Component VCS).
Regarding claim 6, Yukawa, Kim and Nguyen teach all the limitations of claim 5. Yukawa further teaches wherein: the short pulse generator is configured to generate the short pulse signal in response to an edge jump of the low side drive signal or an edge jump the high side drive signal (Translation Paragraph 57 “When the low-side control signal CTRL2 is received from the first logic state to the second logic state, for example, when the high level for controlling the turn-on of the low-side switch LS is switched to the low level for controlling the turnoff of the low-side switch LS, the single The pulse signal generator generates a single pulse signal and sends it to the control terminal of the sampling switch 52”; This passage shows that the switch transition, i.e. the edge jump from high to low or low to high, triggers the single pulse).
Regarding claim 7, Yukawa teaches a controller (Figure 2 has been annotated as Figure 2A above; Figure 2A All Components Except Component PS can be seen collectively as a controller) of a switching mode power supply (Figure 2A) with a power stage (Figure 2A Component PS), comprising: a sample and hold circuit (Figure 2A Component SH; Figure 5 is a detailed figure of the configuration of Component SH; Translation Paragraph 57 “FIG. 5 is a schematic circuit diagram of a sample and hold circuit”), configured to receive a sense signal indicative of a current flowing through the power stage (Figure 2A Component VCS; Translation Paragraph 45 “The sample and hold circuit is used to receive the low-side control signal CTRL2 and the current sampling signal VCS, and generate a specific value S/H of the current sampling signal VCS according to the low-side control signal CTRL2 and the current sampling signal VCS”), and to sample and hold a peak value of the sense signal (Translation Paragraph 57 “the specific value of the current sampling signal includes the peak value of the current sampling signal”), to generate a sample and hold signal (Figure 2A Component S/H); an amplifying circuit (Figure 2A Component AC), configured to generate an adjust reference signal (Figure 2A Component New_valleyref) in response to a reference current and the sample and hold signal (Figure 2A Component Iref; Component EA amplifies the difference between Components S/H and Iref); a comparing circuit (Figure 2A Component COMP; Translation Paragraph 44 “a first comparator”), configured to compare the adjust reference signal with the sense signal (Figure 2A Component COMP compares Component New_valleyref with Component VCS), to generate a comparison signal (Figure 2A Component Valley); and a logical circuit (Figure 2A Component 11; Component 11 is seen in further detail in Figure 3; Figure 3 Component & can be seen as a logical circuit), configured to generate a control signal in response to the comparison signal (Figure 3 Component TOFF).
Yukawa does not teach wherein the amplifying circuit is configured to generate an adjust reference signal based on the sample and hold signal and a reference voltage; and wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage.
Kim teaches a switching mode power supply (Figure 2) including a power stage (Figure 2 Components M+W1+W2+D1+C1) converting an input voltage (Figure 2 Component Vin) to an output voltage (Figure 2 Component Vout); a sample and hold circuit (Figure 2 Component 121; Translation Paragraph 0053 “when the time point of the falling edge of the second detection voltage VS is detected, the sampling/holder 121 outputs the held voltage as the predicted voltage signal EV”) configured to receives a sensed signal (Figure 2 Component VS) and to generate a sample and hold signal (Figure 2 Component EV); an amplifying circuit (Figure 2 Component 139), configured to amplify a difference between the sample and hold signal and a reference voltage (Figure 2 Component VR2; Component 139 amplifies the difference between Components EV and VR2), to generate an adjust reference signal (Figure 2 Component EVAE).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate using a reference voltage instead as taught by Kim. The advantage of this design is that the standard norm in feedback circuits utilizing error amplifiers and comparators is to use voltage references and voltage domain implementations thus reducing the circuit complexity and improving implementation robustness.
Nguyen teaches a DC/DC buck converter (Figure 4), comprising: a power stage (Figure 4 Components N1+N2), including a high side power switch (Figure 4 Component N1) and a low side power switch (Figure 4 Component N2), configured to be periodically turned on and off, to convert an input voltage to an output voltage (Paragraph 0018 “The high side driver 101 turns ON the high side switch N1 and the low side driver 102 turns OFF the low side switch N2 to connect the switch node SW to the input voltage. The high side driver 101 turns OFF the high side switch N1 and the low side driver 102 turns ON the low side switch N2 to connect the switch node SW to ground”); a sample and hold circuit (Figure 4 Component 301), configured to receive a sense signal indicative of a current flowing through the power stage, and to sample and hold a peak value of the sense signal (Paragraph 0028 “When the transistors MP3 and MP4 are ON and the transistor MP5 is OFF, the positive inductor current is mirrored by the transistor MP1 to charge the capacitor C2, allowing the peak (i.e., highest point or value) of the positive inductor current to be stored as charge in the capacitor C2 when the transistor MP4 is turned OFF”), wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage (See 112(a) Rejection For Interpretation; Paragraph 0017 “The inductor current (IL), i.e., the current through the output inductor L1, is positive (+IL) when the inductor current flows from the switch node SW to the output node 104”; Paragraph 0028 “When the transistors MP3 and MP4 are ON and the transistor MP5 is OFF, the positive inductor current is mirrored by the transistor MP1 to charge the capacitor C2, allowing the peak (i.e., highest point or value) of the positive inductor current to be stored as charge in the capacitor C2 when the transistor MP4 is turned OFF”; Claim 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate a current sampling circuit to sample and hold a positive polarity peak signal representing the forward inductor current flowing from the input to the output as taught by Nguyen. The advantage of this modification that it would improve the reliability of Yukawa’s current-limit control and help prevent excessive forward peak current from overloading the power components within the circuit therefore improving overcurrent protection.
Regarding claim 8, Yukawa, Kim and Nguyen teach all the limitations of claim 7. Yukawa further teaches wherein the sample and hold circuit (Figure 2A Component SH is seen in further detail in Figure 5) comprises: a sample switch (Figure 5 Component 53) and a sample capacitor (Figure 5 Component 52), wherein the sample switch is configured to be turned on when the current flowing through the power stage is going to decrease from its peak value, so that the peak value of the sense signal is delivered to the sample capacitor (Translation Paragraph 57 highlights that the sample switch 53 turns on based on the single pulse generator 51 which is triggered when a switching transition happens and a switching transition means the current flowing is going to decrease as the switch is no longer providing current to that point).
Regarding claim 9, Yukawa, Kim and Nguyen teach all the limitations of claim 7. Yukawa does not teach wherein: the logical circuit is configured to generate the control signal in response to the comparison signal and a clock signal, wherein the logical circuit is configured to generate the control signal to control the current flowing through the power stage to increase in response to the clock signal, and is configured to generate the control signal to control the current flowing through the power stage to decrease in response to the comparison signal.
Kim teaches a switching mode power supply (Figure 2) including a power stage (Figure 2 Components M+W1+W2+D1+C1) converting an input voltage (Figure 2 Component Vin) to an output voltage (Figure 2 Component Vout); a sample and hold circuit (Figure 2 Component 121; Translation Paragraph 0053 “when the time point of the falling edge of the second detection voltage VS is detected, the sampling/holder 121 outputs the held voltage as the predicted voltage signal EV”) configured to receives a sensed signal (Figure 2 Component VS) and to generate a sample and hold signal (Figure 2 Component EV); an amplifying circuit (Figure 2 Component 139), configured to amplify a difference between the sample and hold signal and a reference voltage (Figure 2 Component VR2; Component 139 amplifies the difference between Components EV and VR2), to generate an adjust reference signal (Figure 2 Component EVAE); a comparing circuit (Figure 2 Component 107), configured to compare the adjust reference signal with a current sense signal (Figure 2 Component 107 compares Components EVAE and CS), to generate a comparison signal (Figure 2 Component CP2); and a logical circuit (Figure 2 Component 103), configured to generate a control signal in response to the comparison signal (Figure 2 Component QS is generated in response to Component CP2); wherein: the logical circuit is configured to generate the control signal in response to the comparison signal and a clock signal (Figure 2 Component QS is generated in response to Components CLK, a clock signal, and CP2 through Component 105), wherein the logical circuit is configured to generate the control signal to control the current flowing through the power stage to increase in response to the clock signal (Figure 2 Component QS is set based on the clock signal thus increases based on the clock signal therefore it turns on Component M increasing the current; Translation Paragraph 0061 “the SR latch 103 outputs a high-level switch signal QS at the time of the rising edge of the clock signal CLK. Then, the gate signal GC becomes a high level, and the gate driver 100 generates a high level gate voltage VG”), and is configured to generate the control signal to control the current flowing through the power stage to decrease in response to the comparison signal (Figure 2 Component QS is reset based on Component CP2 which in turn turns off Component M thus decreasing the current flowing through; Translation Paragraph 0060 “The SR latch 103 outputs a low-level switch signal QS in synchronization with the rising edge of the comparison signal CP. Then, the gate signal GC becomes a low level and the gate driver 100 generates a low level gate voltage VG. Therefore, the power switch M is turned off”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate using comparator, latch, clock control structure as taught by Kim. The advantage of this design is the comparator, latch, clock control structure ensures proper switching transitions and prevent false switching events caused by comparator noise or ripple in sensed signals and thus would improve switching stability and control reliability.
Regarding claim 10, Yukawa teaches a switching mode power supply (Figure 2; Figure 2 has been annotated above as Figure 2A), comprising: a power stage (Figure 2A Component PS), including at least one power switch (Figure 2A Components HS and LS), configured to be periodically turned on and off (Translation Paragraph 41 highlights that control signals control the turning on and off of Components HS and LS; This is a basic operation of a buck converter high side switch on for one period and the low side switch on for a second period within a switching cycle), to convert an input voltage (Figure 2A Component Vin) to an output voltage (Figure 2A Component Vout); a sample and hold circuit (Figure 2A Component SH; Figure 5 is a detailed figure of the configuration of Component SH; Translation Paragraph 57 “FIG. 5 is a schematic circuit diagram of a sample and hold circuit”), configured to receive a sense signal indicative of a current flowing through the power stage (Figure 2A Component VCS; Translation Paragraph 45 “The sample and hold circuit is used to receive the low-side control signal CTRL2 and the current sampling signal VCS, and generate a specific value S/H of the current sampling signal VCS according to the low-side control signal CTRL2 and the current sampling signal VCS”), and to sample and hold a peak value of the sense signal (Translation Paragraph 57 “the specific value of the current sampling signal includes the peak value of the current sampling signal”), to generate a sample and hold signal (Figure 2A Component S/H); an amplifying circuit (Figure 2A Component AC), configured to amplify a difference between the sample and hold signal and a reference current (Figure 2A Component Iref; Component EA amplifies the difference between Components S/H and Iref), to generate an adjust reference signal (Figure 2A Component New_valleyref); a comparing circuit (Figure 2A Component COMP; Translation Paragraph 44 “a first comparator”), configured to compare the adjust reference signal with the sense signal (Figure 2A Component COMP compares Component New_valleyref with Component VCS), to generate a comparison signal (Figure 2A Component Valley); and a logical circuit (Figure 2A Component 11; Component 11 is seen in further detail in Figure 3; Figure 3 Component & can be seen as a logical circuit), configured to generate a control signal in response to the comparison signal (Figure 3 Component TOFF).
Yukawa does not teach wherein the amplifying circuit is configured to find a difference between the sample and hold signal and reference voltage; and wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage.
Kim teaches a switching mode power supply (Figure 2) including a power stage (Figure 2 Components M+W1+W2+D1+C1) converting an input voltage (Figure 2 Component Vin) to an output voltage (Figure 2 Component Vout); a sample and hold circuit (Figure 2 Component 121; Translation Paragraph 0053 “when the time point of the falling edge of the second detection voltage VS is detected, the sampling/holder 121 outputs the held voltage as the predicted voltage signal EV”) configured to receives a sensed signal (Figure 2 Component VS) and to generate a sample and hold signal (Figure 2 Component EV); an amplifying circuit (Figure 2 Component 139), configured to amplify a difference between the sample and hold signal and a reference voltage (Figure 2 Component VR2; Component 139 amplifies the difference between Components EV and VR2), to generate an adjust reference signal (Figure 2 Component EVAE).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate using a reference voltage instead as taught by Kim. The advantage of this design is that the standard norm in feedback circuits utilizing error amplifiers and comparators is to use voltage references and voltage domain implementations thus reducing the circuit complexity and improving implementation robustness.
Nguyen teaches a DC/DC buck converter (Figure 4), comprising: a power stage (Figure 4 Components N1+N2), including a high side power switch (Figure 4 Component N1) and a low side power switch (Figure 4 Component N2), configured to be periodically turned on and off, to convert an input voltage to an output voltage (Paragraph 0018 “The high side driver 101 turns ON the high side switch N1 and the low side driver 102 turns OFF the low side switch N2 to connect the switch node SW to the input voltage. The high side driver 101 turns OFF the high side switch N1 and the low side driver 102 turns ON the low side switch N2 to connect the switch node SW to ground”); a sample and hold circuit (Figure 4 Component 301), configured to receive a sense signal indicative of a current flowing through the power stage, and to sample and hold a peak value of the sense signal (Paragraph 0028 “When the transistors MP3 and MP4 are ON and the transistor MP5 is OFF, the positive inductor current is mirrored by the transistor MP1 to charge the capacitor C2, allowing the peak (i.e., highest point or value) of the positive inductor current to be stored as charge in the capacitor C2 when the transistor MP4 is turned OFF”), wherein the peak value of the sense signal having a positive polarity representing the current flowing from the input voltage to the output voltage (See 112(a) Rejection For Interpretation; Paragraph 0017 “The inductor current (IL), i.e., the current through the output inductor L1, is positive (+IL) when the inductor current flows from the switch node SW to the output node 104”; Paragraph 0028 “When the transistors MP3 and MP4 are ON and the transistor MP5 is OFF, the positive inductor current is mirrored by the transistor MP1 to charge the capacitor C2, allowing the peak (i.e., highest point or value) of the positive inductor current to be stored as charge in the capacitor C2 when the transistor MP4 is turned OFF”; Claim 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate a current sampling circuit to sample and hold a positive polarity peak signal representing the forward inductor current flowing from the input to the output as taught by Nguyen. The advantage of this modification that it would improve the reliability of Yukawa’s current-limit control and help prevent excessive forward peak current from overloading the power components within the circuit therefore improving overcurrent protection.
Regarding claim 11, Yukawa, Kim and Nguyen teach all the limitations of claim 10. Yukawa further teaches wherein the sample and hold circuit (Figure 2A Component SH is seen in further detail in Figure 5) comprises: a sample switch (Figure 5 Component 53) and a sample capacitor (Figure 5 Component 52), wherein the sample switch is configured to be turned on when the current flowing through the power stage is going to decrease from its peak value, so that the peak value of the sense signal is delivered to the sample capacitor (Translation Paragraph 57 highlights that the sample switch 53 turns on based on the single pulse generator 51 which is triggered when a switching transition happens and a switching transition means the current flowing is going to decrease as the switch is no longer providing current to that point).
Regarding claim 12, Yukawa, Kim and Nguyen teach all the limitations of claim 10. Yukawa does not teach wherein: the logical circuit is configured to generate the control signal in response to the comparison signal and a clock signal, wherein the logical circuit is configured to generate the control signal to control the current flowing through the power stage to increase in response to the clock signal, and is configured to generate the control signal to control the current flowing through the power stage to decrease in response to the comparison signal.
Kim teaches a switching mode power supply (Figure 2) including a power stage (Figure 2 Components M+W1+W2+D1+C1) converting an input voltage (Figure 2 Component Vin) to an output voltage (Figure 2 Component Vout); a sample and hold circuit (Figure 2 Component 121; Translation Paragraph 0053 “when the time point of the falling edge of the second detection voltage VS is detected, the sampling/holder 121 outputs the held voltage as the predicted voltage signal EV”) configured to receives a sensed signal (Figure 2 Component VS) and to generate a sample and hold signal (Figure 2 Component EV); an amplifying circuit (Figure 2 Component 139), configured to amplify a difference between the sample and hold signal and a reference voltage (Figure 2 Component VR2; Component 139 amplifies the difference between Components EV and VR2), to generate an adjust reference signal (Figure 2 Component EVAE); a comparing circuit (Figure 2 Component 107), configured to compare the adjust reference signal with a current sense signal (Figure 2 Component 107 compares Components EVAE and CS), to generate a comparison signal (Figure 2 Component CP2); and a logical circuit (Figure 2 Component 103), configured to generate a control signal in response to the comparison signal (Figure 2 Component QS is generated in response to Component CP2); wherein: the logical circuit is configured to generate the control signal in response to the comparison signal and a clock signal (Figure 2 Component QS is generated in response to Components CLK, a clock signal, and CP2 through Component 105), wherein the logical circuit is configured to generate the control signal to control the current flowing through the power stage to increase in response to the clock signal (Figure 2 Component QS is set based on the clock signal thus increases based on the clock signal therefore it turns on Component M increasing the current; Translation Paragraph 0061 “the SR latch 103 outputs a high-level switch signal QS at the time of the rising edge of the clock signal CLK. Then, the gate signal GC becomes a high level, and the gate driver 100 generates a high level gate voltage VG”), and is configured to generate the control signal to control the current flowing through the power stage to decrease in response to the comparison signal (Figure 2 Component QS is reset based on Component CP2 which in turn turns off Component M thus decreasing the current flowing through; Translation Paragraph 0060 “The SR latch 103 outputs a low-level switch signal QS in synchronization with the rising edge of the comparison signal CP. Then, the gate signal GC becomes a low level and the gate driver 100 generates a low level gate voltage VG. Therefore, the power switch M is turned off”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Yukawa to incorporate using comparator, latch, clock control structure as taught by Kim. The advantage of this design is the comparator, latch, clock control structure ensures proper switching transitions and prevent false switching events caused by comparator noise or ripple in sensed signals and thus would improve switching stability and control reliability.
Regarding claim 13, Yukawa, Kim and Nguyen teach all the limitations of claim 10. Yukawa further teaches wherein the power switch comprises a first power switch (Figure 2A Component HS) and a second power switch (Figure 2A Component LS), and wherein the switching mode power supply further comprising: a drive circuit (Figure 2A Component 11 is seen in detail in Figure 3; Translation Paragraph 54 “FIG. 3 shows a schematic diagram of a circuit principle of the logic unit 11”; Translation Paragraph 55 “one embodiment, the output terminal of the RS flip-flop will be coupled to the gate of the MOS transistor through the driving circuit”; This passage shows that although not shown a driving circuit is present), configured to generate a first drive signal and a second drive signal in response to the control signal (Figure 2A Components CTRL1 and CTRL2 are based off Component TOFF), to respectively control the first power switch and the second power switch (Figure 2A Components HS and LS are controlled by Components CTRL1 and CTRL2, respectively).
Regarding claim 14, Yukawa, Kim and Nguyen teach all the limitations of claim 13. Yukawa further teaches a short pulse generator (Figure 2A Component SH is seen in further detail in Figure 5; Figure 5 Component 51; Translation Paragraph 57 “sample and hold circuit includes a single pulse signal generator 51”), configured to generate a short pulse signal in response to the first drive signal or the second drive signal (Translation Paragraph 57 “The single-pulse signal generator 51 is used for receiving the low-side control signal CTRL2, and generating a single-pulse signal when the low-side control signal CTRL2 changes from the first logic state to the second logic state”), to control the sample and hold circuit to sample and hold the peak value of the sense signal (Figure 5 Component 51 controls switch 52 which holds the peak value of Component VCS).
Regarding claim 15, Yukawa, Kim and Nguyen teach all the limitations of claim 14. Yukawa further teaches wherein: the short pulse generator is configured to generate the short pulse signal in response to an edge jump of the first drive signal or an edge jump the second drive signal (Translation Paragraph 57 “When the low-side control signal CTRL2 is received from the first logic state to the second logic state, for example, when the high level for controlling the turn-on of the low-side switch LS is switched to the low level for controlling the turnoff of the low-side switch LS, the single The pulse signal generator generates a single pulse signal and sends it to the control terminal of the sampling switch 52”; This passage shows that the switch transition, i.e. the edge jump from high to low or low to high, triggers the single pulse).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
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