DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 11 , the disclosure does not provide adequate disclosure to perform the claimed functions of a pulse feedback detector configured to detect a response pulse from the generated pulse reflected from the aircraft electrical load, wherein the pulse feedback detector is operably coupled to a power output of the SSPC.
The specification only recites [0017] The pulse feedback detectors 104a-104n can detect a response pulse from each of the aircraft electrical loads 116 through respective power outputs 114a-114n. The response pulse is a reflection of the pulse by one or more of the aircraft electrical loads 116. The microcontroller 108 can analyze the response pulses detected by the pulse feedback detectors 104a-104n to calibrate the response pulse for each pulse feedback detectors 104a-104n. Each of the pulse feedback detectors 104a-104n can have a different calibrated response pulse corresponding to the differences in the circuitry downstream from each power output 114a-114n. Examples of differences in the circuitry can include different wiring impedances, routing, production breaks, loads, etc. If an SSPC 106a is replaced, the same calibration can be performed on the new SSPC 106a.
Examiner acknowledges the use of the term pulse feedback detectors in the specification however the specification is silent as to the structure of applicant’s pulse feedback detector. Figure 1 shows the pulse feedback detectors as a box with text. The use of this term does not provide adequate because there are any number of possible configurations for a pulse feedback detector. As such, the specification does not provide adequate description of applicant’s pulse feedback detector such that one of ordinary skill in the art would understand what is applicant’s pulse feedback detector .
Regarding claims 7 and 17 , the disclosure does not provide adequate disclosure to perform the claimed functions of a pulse feedback detector wherein the pulse feedback detector is further configured to generate the trigger based on identifying an abnormal voltage or abnormal current.
The specification only recites [0022] In certain embodiments, the pulse generator 102 can be triggered based on detecting changes in power characteristics of the voltage or currents. The pulse feedback detectors 104a-104n can read voltage and current of the circuitry and when the power characteristics are considered abnormal in regard to the system operation, the pulse generator 102 can send a pulse for the pulse feedback detectors 104a-104n to evaluate corresponding response pulses.
Examiner acknowledges the use of the term pulse feedback detectors in the specification however the specification is silent as to the structure of applicant’s pulse feedback detector and the manner in which the pulse feedback detector is implemented to generate a trigger. Figure 1 shows the pulse feedback detectors as a box with text. The use of this term does not provide adequate because there are any number of possible configurations for a pulse feedback detector. As such, the specification does not provide adequate description of applicant’s pulse feedback detector such that one of ordinary skill in the art would understand what is applicant’s pulse feedback detector .
Regarding claims 9 and 19, the disclosure does not provide adequate disclosure to perform the claimed functions of deactivate the pulse generator after a specified number of pulses have been identified by the pulse feedback detector; and determine a calibrated response signal based on response pulses received by the feedback detector for the specified number of pulses.
The specification only recites [0017] The pulse feedback detectors 104a-104n can detect a response pulse from each of the aircraft electrical loads 116 through respective power outputs 114a-114n. The response pulse is a reflection of the pulse by one or more of the aircraft electrical loads 116. The microcontroller 108 can analyze the response pulses detected by the pulse feedback detectors 104a-104n to calibrate the response pulse for each pulse feedback detectors 104a-104n. Each of the pulse feedback detectors 104a-104n can have a different calibrated response pulse corresponding to the differences in the circuitry downstream from each power output 114a-114n. Examples of differences in the circuitry can include different wiring impedances, routing, production breaks, loads, etc. If an SSPC 106a is replaced, the same calibration can be performed on the new SSPC 106a.
Examiner acknowledges the use of the term pulse feedback detectors in the specification however the specification is silent as to the structure of applicant’s pulse feedback detector. Figure 1 shows the pulse feedback detectors as a box with text. The use of the term does not provide adequate because there are any number of possible configurations for a pulse feedback detector. As such, the specification does not provide adequate description of applicant’s pulse feedback detector such that one of ordinary skill in the art would understand what is applicant’s pulse feedback detector .
Claims 2-6,8,10,12-16, 18 and 20 are rejected for containing the 112 rejections above and for depending on rejected claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 11, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Medina Garcia et al. (US 20200103445, hereafter Medina) in view of Kasztenny et al. (WO 2016130949 A1)
Regarding claims 1 and 11, Medina teach An apparatus (Note Fig. 2) comprising:
a solid-state power controller (SSPC) (Note 72, Fig. 2 and para. 0029) configured to output power from a power source to an aircraft electrical load; (Note 52, Fig. 2)
a pulse generator configured to generate a pulse through the SSPC; ([0032] The reflectometry module 92 can include a pattern generator, such as a pseudo-noise code (PN code) generator 94. The PN code generator 94 can be configured or adapted to generate a predetermined identifying pattern to be sent along the power output (e.g. via line 102) to the set of SSPCs 72, 74, 76, and ultimately to at least one electrical load 52, 56 via a respective conductor 86. )
a pulse feedback detector configured to detect a response pulse from the generated pulse reflected from the aircraft electrical load, wherein the pulse feedback detector is operably coupled to a power output of the SSPC; (The reflectometry module 92 can also include a reflection line 100 configured or adapted to receive, sense, measure, or the like, a reflected incident signal. ) and
Medina teach a microcontroller (Note arc fault detection hardware, Fig. 3, par. 0019).
Medina does not teach a microcontroller to trip the SSPC when the response pulse detected by the pulse feedback detector operably coupled to the SSPC is determined to be abnormal.
Kasztenny et al. teach a microcontroller ([0029] Several aspects of the embodiments described will be illustrated as software modules or components. As used herein, a software module or component may include any type of computer instruction or computer executable code located within a memory device and/or transmitted as electronic signals over a system bus or wired or wireless network. ) configured to trip the SSPC when the response pulse detected by the pulse feedback detector operably coupled to the SSPC is determined to be abnormal. ([0025] The distance calculated using Eq. 1 may be used to determine if the distance is less than a line length with margin, and if so, the system may trip the breaker based on the arrival time difference between the first current wave and the first SOP wave.) Examiner interprets the time difference as being abnormal as the reason as why the breaker is tripped.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Medina to include the teaching of a microcontroller to trip the SSPC when the response pulse detected by the pulse feedback detector operably coupled to the SSPC is determined to be abnormal to provide a safety mechanism to protect the circuit.
Regarding claims 5 and 15, Medina teach the pulse generator is configured to continuously generate the pulse at a predetermined interval. (Note par. 0037)
Regarding claims 6 and 16, Medina teach the pulse generator is configured to generate the pulse based on a trigger. (Note par. 0037) Examiner’s position is that the moment the reflectometer module generates the pulse it does so in response to some type of initiation or trigger.
Claims 2-4,12,13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Medina Garcia et al. (US 20200103445, hereafter Medina) in view of Kasztenny et al. (WO 2016130949 A1) further in view of Park (KR 20110082806 A).
Medina teach the instant invention except the following claim limitations.
Regarding claims 2 and 12, Medina does not teach wherein the microcontroller is further configured to compare the response pulse to a calibrated response pulse for the SSPC when determining whether the response pulse is abnormal.
Park et al. teach wherein the microcontroller (control unit 130, par. 0019) is further configured to compare the response pulse to a calibrated response pulse for the SSPC when determining whether the response pulse is abnormal. (The time difference and amplitude information of the reference signal (interpreted as calibrated response signal) and the response signal are compared with a predetermined reference value to diagnose the wiring state, calculate an abnormal position of the wiring (S750), and output the result (S760).)[Note par. 0097]
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Medina to include the teaching of wherein the microcontroller is further configured to compare the response pulse to a calibrated response pulse for the SSPC when determining whether the response pulse is abnormal to detect a wiring state for fault. (Note Park et al. abstract)
Regarding claims 3 and 13, Medina does not teach the microcontroller is configured to compare key signal characteristics of the response pulse to key signal characteristics of the calibrated response pulse.
Park et al. teach the microcontroller is configured to compare key signal characteristics of the response pulse to key signal characteristics of the calibrated response pulse. (The time difference and amplitude information of the reference signal (interpreted as calibrated response signal) and the response signal are compared with a predetermined reference value to diagnose the wiring state, calculate an abnormal position of the wiring (S750), and output the result (S760).)[Note par. 0097]
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Medina to include the teaching of the microcontroller is configured to compare key signal characteristics of the response pulse to key signal characteristics of the calibrated response pulse to detect a wiring state for fault. (Note Park et al. abstract)
Regarding claims 4 and 14, Medina does not teach wherein the key signal characteristics of the calibrated response pulse include at least one of a shape, an amplitude, a curve, a time, frequency domain harmonics, and a quantity of the pulse.
Park et al. teach wherein the key signal characteristics of the calibrated response pulse include at least one of a shape, an amplitude, a curve, a time, frequency domain harmonics, and a quantity of the pulse. (The time difference and amplitude information of the reference signal (interpreted as calibrated response signal) and the response signal are compared with a predetermined reference value to diagnose the wiring state, calculate an abnormal position of the wiring (S750), and output the result (S760).)[Note par. 0097]
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Medina to include the teaching of teach wherein the key signal characteristics of the calibrated response pulse include at least one of a shape, an amplitude, a curve, a time, frequency domain harmonics, and a quantity of the pulse to detect a wiring state for fault. (Note Park et al. abstract)
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Medina Garcia et al. (US 20200103445, hereafter Medina) in view of Kasztenny et al. (WO 2016130949 A1) further in view of Cai et al. (CN 111355472 A).
Medina teach the instant invention except the following claim limitations.
Regarding claims 8 and 18, Medina does not teach receive an input for entering a calibration mode to identify calibrated response signals; and activate the pulse generator.
Cai et al. teach receive an input for entering a calibration mode to identify calibrated response signals; and activate the pulse generator.(Note par. 0077 The above calibration process only requires the pulse generation module 202 and counter 203 in the calibration circuit 200 to run once or multiple times at startup, and then save the count value N for the calibration module 204 to call.) Examiner’s position is that the startup is interpreted as the input for entering calibration.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Medina to include the teaching of receive an input for entering a calibration mode to identify calibrated response signals; and activate the pulse generator to initiate calibration at startup, preparing the device for operation.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Medina Garcia et al. (US 20200103445, hereafter Medina) in view of Kasztenny et al. (WO 2016130949 A1) further in view of Cai et al. (CN 111355472 A) further in view of Park (KR 20110082806 A).
Medina teach the instant invention except the following claim limitations.
Regarding claims 10 and 20, Medina does not teach the microcontroller is further configured to store key signal characteristics of the calibrated response signals.
Park teach the microcontroller is further configured to store key signal characteristics of the calibrated response signals. (The time difference and amplitude information of the reference signal (interpreted as calibrated response signal) and the response signal are compared with a predetermined reference value to diagnose the wiring state, calculate an abnormal position of the wiring (S750), and output the result (S760).)[Note par. 0097] Examiner’s position is that the control unit 130 stores the key level for comparision.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Medina to include the teaching of the microcontroller is further configured to store key signal characteristics of the calibrated response signals to detect a wiring state for fault. (Note Park et al. abstract)
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Medina Garcia et al. (US 20200103445, hereafter Medina) in view of Kasztenny et al. (WO 2016130949 A1) further in view of Mapham et al. (US 3590323)
Regarding claims 7 and 17, Medina does not teach wherein the pulse feedback detector is further configured to generate the trigger based on identifying an abnormal voltage or abnormal current.
Mapham et al. teach wherein the pulse feedback detector is further configured to generate the trigger based on identifying an abnormal voltage or abnormal current. (Note claim 13)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Medina to include the teaching of the pulse feedback detector is further configured to generate the trigger based on identifying an abnormal voltage or abnormal current to cause the circuit breaker to interrupt the circuit and protect the circuit when a fault occurs.
Examiner’s Note:
Claims 9 and 19 stand rejected under 35 USC 112(a) as outlined above. No prior art rejection has been applied to these claims because the prior art of record taken alone or in combination fails to teach the following features recited in these claims:
Regarding claim 9, wherein the microcontroller is further configured to: deactivate the pulse generator after a specified number of pulses have been identified by the pulse feedback detector; and determine a calibrated response signal based on response pulses received by the feedback detector for the specified number of pulses.
Regarding claim 19, deactivating the pulse generator after a specified number of pulses have been identified by each of the pulse feedback detector; and determining a calibrated response signal based on response pulses received by the pulse feedback detector for the specified number of pulses.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEMETRIUS R PRETLOW whose telephone number is (571)272-3441. The examiner can normally be reached M-F, 5:30-1:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DEMETRIUS R PRETLOW/ Examiner, Art Unit 2858
/LEE E RODAK/ Supervisory Patent Examiner, Art Unit 2858