DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Page 11, Line 11, “VFB_VCMP” should be changed to “VFB_CMP”.
Page 12, Line 20, “potion” should be changed to “portion”.
Page 15, Line 2, “comparator 320” should be changed to “comparator 352”.
Appropriate correction is required.
Claim Objections
Claims 1-7 and 9 are objected to because of the following informalities:
Claim 1, line 11 “a reference voltage” should be changed to “the reference voltage”.
Claim 3, lines 4-5, recites “the voltage regulator” which does not have proper antecedent basis as neither claim 3 nor claim 1, which claim 3 depends upon, does not recite any element called “a voltage regulator” so should be changed to “a voltage regulator of the voltage regulation portion”.
Claims 2 and 4-6, recite “the control circuitry” while claim 1 recites “a control portion” therefore the language in claim 1 should be changed to “a control circuitry”.
Claim 7, line 5, “a reference voltage” should be changed to “the reference voltage”.
Claim 9, line 3, “the received output voltage” should be changed to “the output voltage”.
Appropriate correction is required.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 8, 10-11 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sharma (US 2024/0094753 A1).
Regarding claim 1, Sharma teaches a voltage regulation circuitry (Figure 2 Component 205) comprising: a voltage regulation portion (Figure 7 is the voltage regulation portion in further detail; Operational Characteristics and details of Figure 7 are explained in Figures 5A and 5B which also show Component 205 from Figure 2 in further detail; Paragraph 0039) having a regulation mode (Figure 5A; Paragraph 0029 “FIG. 5A is a circuit diagram illustrating multi-mode LDO regulator circuit 205 operating in regulation/LDO mode 305”; Figure 3A) and a bypass mode (Figure 5B; Paragraph 0033 “FIG. 5B is a circuit diagram illustrating multi-mode LDO regulator circuit 205 operating in bypass/switch mode 310”; Figure 3B), and being configured: when the voltage regulation portion is in the bypass mode (Figure 5B), to output an unregulated voltage received from a power supply (Figure 3A shows that in the bypass mode 310 the pass transistor operates as a switch and the output voltage Vout is substantially the same as the supply voltage VIN showing an unregulated voltage output; Figure 6B shows this in the bypass mode); and when the voltage regulation portion is in the regulation mode (Figure 5A) and the received unregulated voltage is greater than a received reference voltage (Figure 3B shows that in the regulation mode Vout is compared with Vref at operational amplifier 302 and the control is based on the comparison between the voltages; Figure 6B shows that in the regulation mode the voltage is regulated; Paragraphs 0025 and 0028), to regulate the unregulated voltage to output a predetermined regulated voltage (Figure 6B shows that the voltage is regulated to a certain amount in the regulation mode); and the voltage regulation circuitry further comprising a control portion (Figure 7 Components 702+302+Rf1+Rf2) configured to: compare a feedback voltage based on the output from the voltage regulation portion to a reference voltage (Figure 7 Component 302); and when the voltage regulation portion is in the regulation mode, in response to determining that the feedback voltage does not exceed the reference voltage, switch the voltage regulation portion into the bypass mode (Paragraph 0040 “Dropout detector circuit 702 may detect a dropout in the output voltage, V.sub.OUT, and asserts a dropout flag 704 (e.g., dropout flag 704 becomes “1”) in response to detection of the dropout in the output voltage, V.sub.OUT. If an allow_switchmode flag 706 is set to “1”, then the switch mode enable signal, EN_SW 504, may be asserted (e.g., changes its value to the defined high voltage or to the bit value of “1”). In response to the assertion of the switch mode enable signal, EN_SW 504, LDO regulator circuit 205 may transition from regulation/LDO mode 305 to bypass/switch mode 310”; Figure 8).
Regarding claim 2, Sharma teaches all the limitations of claim 1. Sharma further teaches wherein the control circuitry is configured, when the voltage regulation portion is in bypass mode, in response to determining that the feedback voltage exceeds the reference voltage, to switch the voltage regulation portion into the regulation mode (Paragraph 0041 “When dropout detector circuit 702 detects an increase in the output voltage, V.sub.OUT, dropout flag 704 de-asserts (e.g., dropout flag 704 becomes “0”), the switch mode enable signal, EN_SW 504, also de-asserts (e.g., changes its value to the defined low voltage or to the bit value of “0”). In response to the de-assertion of the switch mode enable signal, EN_SW 504, LDO regulator circuit 205 may transition from bypass/switch mode 310 back to regulation/LDO mode 305”; Figure 8).
Regarding claim 8, Sharma teaches all the limitations of claim 1. Sharma further teaches wherein the voltage regulation circuitry comprises a feedback divider portion (Figure 7 Components Rf1+Rf2), and wherein the feedback divider portion is configured to: receive the output voltage of the voltage regulation portion (Figure 7 Components Rf1+Rf2 receive Vout); output a feedback voltage to the control portion derived from the output voltage (Figure 7 Components Rf1+Rf2 output Vfb); and output a feedback voltage to the voltage regulation portion derived from the output voltage (Figure 7 Component Vfb is derived from the output voltage).
Regarding claim 10, Sharma teaches all the limitations of claim 1. Sharma further teaches wherein the voltage regulation circuitry is provided as part of an integrated circuit on a system-on-chip (Figure 2 shows that the LDO is part of an integrated circuit within a device).
Regarding claim 11, Sharma teaches all the limitations of claim 10. Sharma further teaches wherein the voltage regulation circuitry is configured to start in the bypass mode when the system-on-chip undergoes an analog reset (Paragraph 0002 highlights the powering on of analog device such as the one shown in Figure 2 that has an LDO therefore when powered on that can be seen as the analog reset; Figures 6A-6B show the initial mode of operation is the bypass mode).
Regarding claim 14, Sharma teaches a method of voltage regulation (Figure 2 Component 205) comprising: using a voltage regulation portion of circuitry (Figure 7 is the voltage regulation portion in further detail; Operational Characteristics and details of Figure 7 are explained in Figures 5A and 5B which also show Component 205 from Figure 2 in further detail; Paragraph 0039) to output an unregulated voltage (Figure 7 Component Vout) received from a power supply (Figure 7 Component Vin) when the voltage regulation portion is in a bypass mode (Figure 5B; Paragraph 0033 “FIG. 5B is a circuit diagram illustrating multi-mode LDO regulator circuit 205 operating in bypass/switch mode 310”; Figure 3B; Figure 3A shows that in the bypass mode 310 the pass transistor operates as a switch and the output voltage Vout is substantially the same as the supply voltage VIN showing an unregulated voltage output; Figure 6B shows this in the bypass mode); when the voltage regulation portion is in a regulation mode (Figure 5A; Paragraph 0029 “FIG. 5A is a circuit diagram illustrating multi-mode LDO regulator circuit 205 operating in regulation/LDO mode 305”; Figure 3A) and the received unregulated voltage is greater than a received reference voltage (Figure 3B shows that in the regulation mode Vout is compared with Vref at operational amplifier 302 and the control is based on the comparison between the voltages; Figure 6B shows that in the regulation mode the voltage is regulated; Paragraphs 0025 and 0028), using the voltage regulation portion to regulate the unregulated voltage to output a predetermined regulated voltage (Figure 6B shows that the voltage is regulated to a certain amount in the regulation mode); and using a control portion of circuitry (Figure 7 Components 702+302+Rf1+Rf2) to: compare a feedback voltage based on the output from the voltage regulation portion to a reference voltage (Figure 7 Component 302; Component Vref); and when the voltage regulation portion is in the regulation mode, in response to determining that the feedback voltage does not exceed the reference voltage, switch the voltage regulator into a bypass mode (Paragraph 0040 “Dropout detector circuit 702 may detect a dropout in the output voltage, V.sub.OUT, and asserts a dropout flag 704 (e.g., dropout flag 704 becomes “1”) in response to detection of the dropout in the output voltage, V.sub.OUT. If an allow_switchmode flag 706 is set to “1”, then the switch mode enable signal, EN_SW 504, may be asserted (e.g., changes its value to the defined high voltage or to the bit value of “1”). In response to the assertion of the switch mode enable signal, EN_SW 504, LDO regulator circuit 205 may transition from regulation/LDO mode 305 to bypass/switch mode 310”; Figure 8).
Allowable Subject Matter
Claims 3-7, 9 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the voltage regulation portion has an idle mode, and the voltage regulation portion is configured, when the voltage regulation portion is in the idle mode, such that no power is provided to the voltage regulator, and the unregulated voltage received from the power supply is not passed through to the output of the voltage regulation portion. Claims 4-6 depend upon claim 3.
Regarding claim 7, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the voltage regulation circuitry comprises a reference voltage generator portion, and wherein the reference voltage generator portion is configured: when the voltage regulation circuitry is operating in a high-power mode, to output a reference voltage using a high-power current source; and when the voltage regulation circuitry is operating in a low-power mode, to output a reference voltage using a low-power current source.
Regarding claim 9, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein when the feedback divider is switched on, the feedback divider is configured to output a feedback voltage to the control portion which is higher than the received output voltage of the voltage regulation portion.
Regarding claim 12, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the control circuitry is configured, when the voltage regulation circuitry is in the bypass mode following the analog reset of the system-on-chip, to switch the voltage regulation portion to the regulation mode after a predetermined time period has elapsed since the reset
Regarding claim 13, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the voltage regulation circuitry is configured to operate in a high-power mode when the high-frequency digital clock of the system-on-chip is running, and otherwise run in a low-power mode.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lourens (US 8080983 B2) teaches a power element bypass and voltage regulation circuit shutdown is used in a low drop out (LDO) bypass voltage regulator to minimize current drawn by the voltage regulator circuit when the supply input voltage approaches the regulated output voltage of the voltage regulation circuit. Two modes of operation are used in the low drop out (LDO) bypass voltage regulator. A regulate mode is used when the supply input voltage is greater than the reference voltage input, and a track mode is used when the supply input voltage is less than or equal to approximately the regulated output voltage of the voltage regulation circuit. Hysteresis may be introduced when switching between the regulate and track modes of operation.
Bhattad (US 2015/0077076 A1) teaches a dual mode low dropout voltage regulator has a low dropout regulation mode and a bypass mode and provides a smooth transition between mode transitions taking place under load. When an accessory requires a larger voltage level, a bypass signal commands the dual mode low dropout voltage regulator to go into bypass mode and transfer voltage level of the unregulated input voltage source to the output of the dual mode low dropout voltage regulator. The dual mode low dropout voltage regulator provides a smooth transition to the bypass to prevent the output of the dual mode low dropout voltage regulator from decreasing or having a "brown out" until a pass transistor is forced to turn on fully to provide the voltage level of the unregulated input voltage source to fully bypass the low dropout regulating mode of operation.
Cheng (US 10444780 B1) teaches a regulator with regulation and bypass automation wherein the LDO includes a resistor, a pass transistor having a source, a gate, and a drain to output a voltage Vout, the source coupled to a supply voltage, the gate coupled to an output of an operational transconductance amplifier (OTA), and the drain coupled to a first terminal of the resistor; a feedback switch having a drain, a gate, and a source, the drain coupled to a second terminal of the resistor, the source coupled to a negative input of the OTA; and an pull-down transistor having a drain, a gate, and a source, the source coupled to ground, and the drain coupled to the negative input of the OTA, wherein the gate of the pull-down transistor and the gate of the feedback switch are configured to receive a bypass signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
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