DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/8/2025 has been entered.
Terminal Disclaimer
The terminal disclaimer filed has been accepted and the double patenting rejection withdrawn.
Response to Amendment
The amendments filed 12/8/2025 have been accepted. Claims 2-6 and 8-21 are still pending. Claims 2 and 11-21 are amended. Applicant’s amendments to the claims have overcome each and every 103 rejection previously set forth in the Non-Final Office Action mailed 10/8/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US PGPub 2021/0294503) in view of Schuetz (US PGPub 2011/0276775) in view of Arndt et al. (US PGPub 2019/0121760, hereafter referred to as Arndt).
Regarding claim 2, Lee teaches an apparatus, comprising: processing circuitry coupled with a plurality of memory dies (Fig. 3 and Paragraphs [0069]-[0070], and [0082], shows the memory device that has a control logic (and thus a controller that uses the logic) and a status register that can contain the status of the multiple planes of the device. Paragraph [0167], states that a die package can be used), the processing circuitry configured to cause the apparatus to: poll a plurality of statuses comprising a respective status corresponding to each memory die of the plurality of memory dies (Paragraph [0082] and [0113], shows that the control logic can set the status register for each plane based on whether or not it is currently conducting an operation or has finished. Fig. 9 and Paragraphs [0105], shows that the state of the device can be checked meaning that the status information would have to be polled). Lee does not explicitly teach the processing circuitry connected via a bus and external to the memory dies, transmit, via the bus that is coupled with each memory die of the plurality of memory dies, a single polling request for a plurality of flags comprising a respective flag corresponding to each memory die of the plurality of memory dies; receive, via the bus and in response to the single polling request, respective indications of a respective state of each of the plurality of flags; transmit, to a first memory die of the plurality of memory dies based at least in part on the respective indications of the respective state of each of the plurality of flags, and receive, from the first memory die based at least in part on a command to output data, the data corresponding to the access operation at the first memory die.
Schuetz teaches the processing circuitry connected via a bus and external to the memory dies (Fig. 1A and Paragraph [0041], shows the memory controller is external to the memory devices and is connected to them via a channel which includes a set of buses), transmit, via the bus that is coupled with each memory die of the plurality of memory dies, a plurality of flags comprising a respective flag corresponding to each memory die of the plurality of memory dies (Paragraph [0062], states that the bridge device can set its status register to ready when data is ready to be read out (indicating the read operation at the memory device is completed. Paragraph [0073], states that there are status register bits meaning the flag in the status register comprises at least a single bit. Paragraph [0072] and [0099]-[0101], states that the memory controller can check (poll) the register to see if the pending reads are completed and then what state the particular devices/planes are in (ready or deferred). While there is no explicit recitation of a polling request for the flag, the steps presented are equivalent as Schuetz does show polling as a method of obtaining the indication of the flag (done by the bridge for the flag) as well as done by the controller for an indication of completion meaning the controller is capable of polling for information. One of ordinary skill would recognize that one could substitute the method of identifying the flag and entity doing it to obtain the predictable result of the claimed limitations. Fig. 2A, 3A, and 4, and Paragraph [0041] and [0062], show the data channels which comprises busses that connect the memory controller to the bridge and to the memory devices which allows for the sending of commands and requests which include the one that would poll the status of the devices (die flags) and states that the devices can be operated concurrently), transmit, to a first memory die of the plurality of memory dies, based at least in part on the respective indications of the respective state of each of the plurality of flags, a command to output data, wherein the command to output data is based at least in part on a first flag corresponding to the first memory die of the plurality of memory dies indicating a completion of at least one access operation at the first memory die and receive, from the first memory die based at least in part on the command to output the data, the data corresponding to the at least one access operation at the first memory die (Paragraph [0072] and [0101], states the memory controller can send a read command once the data is ready as a method to then retrieve the data. Paragraph [0072] and [0099]-[0101], as stated previously, a check (polling) can be done to see the state of the memory device and a command can be sent based on the check). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee to use the bridge device of Schuetz to have an improved bridge device having a minimally sized data buffer which can control access by the discrete memory devices (Schuetz, Paragraph [0009]). Lee and Schuetz do not teach transmit, via the bus that is coupled with each memory die of the plurality of memory dies, a single polling request for a plurality of flags comprising a respective flag corresponding to each memory die of the plurality of memory dies; receive, via the bus and in response to the single polling request, respective indications of a respective state of each of the plurality of flags.
Arndt teaches transmit, via the bus, a single polling request for a plurality of statuses comprising a respective status corresponding to each entity; receive, via the bus and in response to the single polling request, respective indications of a respective state of each of the plurality of states (Paragraph [0053], states a single polling request can be sent to multiple processing units for the status of threads managed by snoopers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee and Schuetz to utilize the single polling request as taught in Arndt so to efficiently manage the sequence of one or more single bus commands and responses supported by interrupt bus protocol within interrupt logic (Arndt, Paragraph [0052]).
Regarding claim 3, Lee, Schuetz, and Arndt teach all the limitations to claim 2. Schuetz further teaches wherein the processing circuitry is further configured to cause the apparatus to: identify, based at least in part on polling the plurality of flags, that a second flag associated with a second memory die indicates that no access operation has been completed at the second memory die, and refrain from polling a register associated with the second memory die based at least in part on the second flag associated with the second memory die indicating that no access operation has been completed at the second memory die (Paragraph [0072], if the query shows that a device/plane is not ready, then there is no need to proceed further with checking the data. This is also true if no read command has been sent to a second device when the flags are polled as there is no access operation to check on). The combination of and reason for combining are the same as those given in claim 2.
Regarding claim 4, Lee, Schuetz, and Arndt teach all the limitations to claim 2. Lee further teaches wherein the processing circuitry is further configured to cause the apparatus to: poll, a register associated with the first memory die, and identify, based at least in part on polling the register, the completion of the at least one access operation at a first plane of a plurality of planes associated with the first memory die, (Paragraph [0082] and [0113], shows that the control logic can set the status register for each plane based on whether or not it is currently conducting an operation or has finished. Fig. 9 and Paragraphs [0105], shows that the state of the device can be checked meaning that the status information would have to be polled). Schuetz further teaches poll, based at least in part on the first flag indicating the completion of at least one access operation (Paragraph [0072] and [0099]-[0101], as stated in the rejection to claim 2), wherein the command to output the data requests the data associated with the at least one access operation at the first plane (Paragraphs [0072] and [0101], as stated in the rejection to claim 2, the command can be a read command directed to the data retrieved by the operation). The combination of and reason for combining are the same as those given in claim 2.
Regarding claim 5, Lee, Schuetz, and Arndt teach all the limitations to claim 2. Schuetz further teaches wherein, to poll the register associated with the first memory die, the processing circuitry is further configured to cause the apparatus to: poll a first status bit of a plurality of status bits stored in the register, the first status bit corresponding to the first plane and indicating the completion of the at least one access operation at the first plane (Paragraph [0062], states that the bridge device can set its status register to ready when data is ready to be read out (indicating the read operation at the memory device is completed. Paragraph [0073], states that there are status register bits meaning the flag in the status register comprises at least a single bit). The combination of and reason for combining are the same as those given in claim 2.
Regarding claim 6, Lee, Schuetz, and Arndt teach all the limitations to claim 5. Schuetz further teaches wherein a second status bit of the plurality of status bits stored in the register indicates a completion status of at least a second operation at a second plane of the plurality of planes associated with the first memory die (Fig. 4-6 and Paragraphs [0056]-[0058], shows multiple devices can be connected to a channel and those devices can each have multiple planes. Paragraphs [0062] and [0072], as stated in the rejection to claim 1 describe the process of reading data from the devices. Paragraph [0102] also states that multiple-device, multiple-plane read situations are also a possibility. The limitations are essentially describing performing the exact same procedure with another die in the apparatus). The combination of and reason for combining are the same as those given in claim 2.
Regarding claim 8, Lee, Schuetz, and Arndt teach all the limitations to claim 2. Schuetz further teaches wherein the processing circuitry is further configured to cause the apparatus to: receive, via the bus based at least in part on polling the plurality of flags, a plurality of signal lines, each of the plurality of signal lines indicating a value of a respective flag of the plurality of flags (Fig. 2A, 3A, and 4, and Paragraph [0041],as stated in the rejection to claim 1, the bus also can carry the ready/busy signals for the devices/planes concurrently as well). The combination of and reason for combining are the same as those given in claim 2.
Regarding claim 9, Lee, Schuetz, and Arndt teach all the limitations to claim 2. Schuetz further teaches wherein the processing circuitry is further configured to cause the apparatus to: transmit, via the bus, a first command to the first memory die to initiate the at least one access operation, and transmit, via the bus, a second command to a second memory die to initiate a second access operation, wherein performance of the at least one access operation by the first memory die is concurrent with performance of the second access operation by the second memory die (Paragraph [0062], as stated in the rejection to claim 7, the devices can be read concurrently. It should also be noted that this is standard interleaving that has been a standard property of all flash devices for decades). The combination of and reason for combining are the same as those given in claim 2.
Regarding claim 10, Lee, Schuetz, and Arndt teach all the limitations to claim 2. Schuetz further teaches wherein the bus is an open not-and (NAND) flash interface (ONFI) bus (Paragraph [0050], states that the format used can be ONFi standard meaning the busses would be also be ONFi busses). The combination of and reason for combining are the same as those given in claim 2.
Claims 11-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Schuetz in view of Shekhar (US PGPub 2019/0042491).
Regarding claim 11, Lee teaches a memory system, comprising: one or more memory dies each comprising a plurality of planes, one or more registers associated with the one or more memory dies, each register of the one or more registers configured to store a plurality of status bits each corresponding to a respective one of the plurality of planes, and processing circuitry coupled with the one or more memory dies (Fig. 3 and Paragraphs [0069]-[0070], and [0082], shows the memory device that has a control logic (and thus a controller that uses the logic) and a status register that can contain the status of the multiple planes of the device. Paragraph [0167], states that a die package can be used), and configured to cause the memory system to: set a first status bit of a register of the one or more registers corresponding to a first plane of the plurality of planes included in a first memory die of the one or more memory dies based at least in part on a completion of an access operation at the first plane (Paragraph [0082] and [0113], shows that the control logic can set the status register for each plane based on whether or not it is currently conducting an operation or has finished). Lee does not explicitly teach setting a first flag stored at the first memory die to indicate a completion of the at least one access operation at the first memory die based at least in part on the completion of the access operation at the first plane, receive, after setting the first flag to indicate the completion of at least one access operation at the first memory die, a single polling request for the first flag and for at least a second flag stored at a second memory die, output, in response to the single polling request for the first flag and for at least the second flag, a first indication that the first flag is set and at least a second indication of whether the second flag is set, receive, based at least in part on the first flag to indicate the completion of at the least one access operation at the first memory die being set, a command to output data associated with the first plane, and output, based at least in part on the command, data corresponding to the access operation at the first plane.
Schuetz teaches setting a first flag associated with the first memory die to indicate a completion of at least one access operation at the first memory die based at least in part on the completion of the access operation at the first plane (Paragraph [0062], states that the bridge device can set its status register to ready when data is ready to be read out (indicating the read operation at the memory device is completed), receive, after setting the flag to indicate the completion of at least one access operation at the first memory die, a polling request for the first flag, output, in response to the polling request for the first flag, an indication that the first flag is set (Paragraph [0072] and [0099]-[0101], states that the memory controller can check (poll) the register to see if the pending reads are completed and then what state the particular devices/planes are in (ready or deferred) meaning a response would be received in response to the polling), receive, based at least in part on the first flag to indicate the completion of at least one access operation being set, a command to output data associated with the first plane, and output, based at least in part on the command, data corresponding to the access operation at the first plane (Paragraph [0062] and [0072], states that the bridge device can signal the memory controller when the data is ready and then the memory controller can then send a command to reinitiate the read command and transfer the data. Paragraph [0054], states that read data is provided to the memory controller via the GLBCMD_OUT). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee to use the bridge device of Schuetz to have an improved bridge device having a minimally sized data buffer which can control access by the discrete memory devices (Schuetz, Paragraph [0009]). Lee and Schuetz do not teach setting a flag associated with stored at the memory die to indicate a completion of at least one access operation at the memory die, and polling the flag in the memory die.
Shekhar teaches setting a first flag associated with stored at the first memory die to indicate a completion of at least one access operation at the memory die, and polling the first flag in the first memory die (Paragraph [0038], states that a flag can be set in the shared memory and can be polled by the processor). Since both Lee/Schuetz and Shekhar teach indicating completion of an operation and polling the status of the operation it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the method of indicating and polling of Lee and Schuetz with that of Shekhar to obtain the predictable result of setting a flag associated with stored at the memory die to indicate a completion of at least one access operation at the memory die, and polling the flag in the memory die. Lee, Schuetz, and Shekhar do not teach a single polling request for the first flag and for at least a second flag stored at a second memory die, output, in response to the single polling request for the first flag and for at least the second flag, a first indication that the first flag is set and at least a second indication of whether the second flag is set.
Arndt teaches a single polling request for the first status and for at least a second status, output, in response to the single polling request for the first status and for at least the second stats, a first indication of the first status and at least a second indication of the second status (Paragraph [0053], states a single polling request can be sent to multiple processing units for the status of threads managed by snoopers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee, Schuetz, and Shekhar to utilize the single polling request as taught in Arndt so to efficiently manage the sequence of one or more single bus commands and responses supported by interrupt bus protocol within interrupt logic (Arndt, Paragraph [0052]).
Regarding claim 12, Lee, Schuetz, Shekhar, and Arndt teach all the limitations to claim 11. Schuetz further teaches the second memory die of the one or more memory dies comprising a second plurality of planes, wherein both the first memory die and the second memory die are coupled with the processing circuitry via a shared bus (Fig. 4-6 and Paragraphs [0056]-[0058], shows multiple devices can be connected to a channel (shared bus) and those devices can each have multiple planes). The combination of and reason for combining are the same as those given in claim 11.
Regarding claim 13, Lee, Schuetz, Shekhar, and Arndt teach all the limitations to claim 12. Schuetz further teaches wherein, to output the first indication that the first flag is set, the processing circuitry is further configured to cause the memory system to: output, from the first memory die to the processing circuitry via the shared bus, the first indication that the first flag is set (Fig. 2A, 3A, and 4 and Paragraphs [0041], the bus also can carry the ready/busy signals for the devices/planes which is an indication of whether the flag is set). The combination of and reason for combining are the same as those given in claim 11.
Regarding claim 14, Lee, Schuetz, Shekhar, and Arndt teach all the limitations to claim 12. Schuetz further teaches wherein the processing circuitry is further configured to cause the memory system to: output, from the second memory die to the processing circuitry via the shared bus, the second indication of whether the second flag associated with the second memory die is set, the second flag indicating a completion status of at least one access operation at the second memory die (Fig. 4-6 and Paragraphs [0056]-[0058], shows multiple devices can be connected to a channel and those devices can each have multiple planes. Paragraphs [0062] and [0072], as stated in the rejection to claim 11 describe the process of reading data from the devices. Paragraph [0102] also states that multiple-device, multiple-plane read situations are also a possibility. The limitations are essentially describing performing the exact same procedure with another die in the apparatus). The combination of and reason for combining are the same as those given in claim 11.
Regarding claim 15, Lee, Schuetz, Shekhar, and Arndt teach all the limitations to claim 12. Schuetz further teaches wherein the processing circuitry is further configured to cause the memory system to: output, from the second memory die to the processing circuitry via the shared bus, the second indication of whether the second flag associated with the second memory die is set, wherein the second indication at least partially overlaps in time with the first indication that the first flag is set output from the first memory die (Fig. 2A, 3A, and 4 and Paragraphs [0041], show the data channels which comprises busses that connect the memory controller to the bridge and to the memory devices which allows for the sending of commands and requests which include the one that would poll the status of the devices (die flags). Paragraph [0062], states operations can be done concurrently). The combination of and reason for combining are the same as those given in claim 11.
Regarding claim 16, Lee, Schuetz, Shekhar, and Arndt teach all the limitations to claim 12. Schuetz further teaches wherein the processing circuitry is further configured to cause the memory system to: output, from the second memory die to the processing circuitry via the shared bus, the second indication of whether the second flag associated with the second memory die is set, wherein the second indication is output from the second memory die via a first input/output (I/O) line of the shared bus, and wherein the first indication that the first flag is set is output from the first memory die via a second I/O line of the shared bus (Fig. 4 and Paragraphs [0053]-[0054], show the various lines that are used to transfer information which include separate ready/busy lines that are used for each memory device). The combination of and reason for combining are the same as those given in claim 11.
Regarding claims 17-21, claims 17-21 are the computer readable medium claims associated with claims 11-16. Since Lee, Schuetz, Shekhar, and Arndt teach all the limitations to claims 11-16, they also teach all the limitations to claims 17-21; therefore the rejections to claims 11-16 also apply to claims 17-21.
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot because the applicant amended the claims with the limitation a single polling request for a plurality of flags…” to overcome the prior rejections set forth in the Final Rejection mailed 10/8/2025. To address this, new reference Arndt has been incorporated into the rejections to teach the amended limitations.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132