Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to communications filed on 7/27/26.
Claims 1-12, 25-32 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-12 and 25-32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 and 25 recite the limitations “the selected one of the plurality of delay taps being fixed for the logic block and not varying based on a selection, during operation of the digital semiconductor device, between a plurality of different processing functions performable by the logic block on the data”, which is not fully supported by the specification.
Applicant’s response cites [0038]-[0039] for the support. The limitations are not fully supported by the specification Fig 5, [0038]-[0039] because the embodiment is not limited to temperature and process as argued in the page 11 – page 12 of the submitted reply (“parameters monitored can include but are not limited to temperature and process” in [0038] of specification). The negative limitations must be fully supported by the specification. The mere absence of a feature in the specification does not automatically support a negative limitation. Specification does not mention the selected one of the plurality of delay taps being fixed for the logic block and not varying based on a selection, during operation of the digital semiconductor device, between a plurality of different processing functions performable by the logic block on the data.
The dependent claims inherit the subject matters and are rejected with the same rationale.
Response to Arguments
Applicant's arguments with respect to support for the newly added limitations have been fully considered but they are not persuasive.
Applicant argues that specification [0038]-[0039] provides the support for the newly added limitations.
Applicant mentions support for this amendment can be found, at least, at paragraphs [0038]-[0039] of the Specification, which describe the clock delay chain as providing "an adjustable delay that enables either static configuration of clock delays or dynamic adjustment," with dynamic adjustment "based on control signals... driven by on chip monitoring circuitry" monitoring "temperature and process." Further applicant mentions:
The Specification never describes this dynamic adjustment as based on the processing function being performed on the data. The only basis for dynamic adjustment disclosed anywhere in the Specification is temperature and process monitoring, consistent with the amended claim language excluding variation based on processing function. No new matter is introduced. (see pages 11 and 12 of response)
Examiner disagrees. The mere absence of a feature in the specification does not automatically support a negative limitation Specification Section [0038][0039] does not mention the selected one of the plurality of delay taps being fixed for the logic block and not varying based on a selection, during operation of the digital semiconductor device, between a plurality of different processing functions performable by the logic block on the data. Mere stating dynamic adjustment "based on control signals... driven by on chip monitoring circuitry" monitoring "temperature and process" is not sufficient for the newly cited limitations (i.e., not varying based on a selection, during operation of the digital semiconductor device, between a plurality of different processing functions) particularly when [0038] is open ended (i.e., “but are not limited to ..”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAHMIDA RAHMAN whose telephone number is (571)272-8159. The examiner can normally be reached Monday - Friday 10 AM - 7 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175
