Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to communications filed on 4/6/26.
Claims 1-12, 25-32 are pending.
The IDS filed on 4/20/26, 2/10/25 have been considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-8, 10, 12, 25- 26, 28-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US Patent 9740487) in view of Olivarez et al (US Patent Application Publication 2014/0281735)
For claim 1, Huang et al teach the following limitations: A digital semiconductor device (Fig 1; Fig 4 – Fig 9) comprising: a first set of logic blocks (Fig 8 shows the array of logic blocks; lines 1-13 of col 8) having a processing structure (processor 310 330 provide pipelined processing; line 50, col 4 through line 5, col 5; lines 1-13 of col 8) to process data along a first processing path (Fig 8; pipeline 800 lines 1-10 of col 8), from a first logic block in the first processing path to the last logic block element in the first processing path (Fig 4 Fig 8, lines 1-32 of col 8; pipeline 800 has successive stages; each intermediate stage processes input data from previous stage; pipeline 800 may include five stages); a second set of logic blocks (lines 10-15 of col 8; line 63, col 4 through line 4, col 5 mention that any number of separate pipelines in CPUs can be included) having a processing structure to process data along one or more processing paths, from a first logic block for each of the one or more processing paths to and last logic block in the one or more processing paths (Fig 4 Fig 8, lines 1-32 of col 8; pipeline has successive stages; each intermediate stage processes input data from previous stage; thus the separate second pipeline has plurality of stages including blocks to process data along the path from the first stage to the last stage); a clocking structure (Fig 4 – Fig 8 depict the clocking structure; Fig 5 – Fig 7 – 422 is the clock out) where the clock for each logic block in the first processing path follows the data along the first processing path (Fig 4 and Fig 8; lines 15-30 of col 5; lines 10-13 of col 7; lines 1-32 of col 8 – clock path is shown as 408, 420, 422 through stages in Fig 4 and data path is shown through 402, 410, 406, 404 through stages; the stages of pipeline are hierarchical; Fig 8 shows a pipeline structure with plurality of stages where data flows through the stages and clock follows data via 420) and is configured to asynchronously forward the clock to adjacent logic blocks in the first processing path (Fig 4 and Fig 8; lines 10-12 of col 4; lines 14-20 of col 5; asynchronous processor and the clock is not synchronous with any system clock lines 63-65 of col 1), the first processing path being asynchronous with the one or more processing paths (the processor is asynchronous to the extent that there is no global or system clock; lines 14-26 of col 5, lines 10-12 of col 4; lines 25-30 of col 4; the pipelines are asynchronous respect to each other).
Huang et al does not explicitly mention the following limitations:
a synchronizer connected to the last logic block in the first processing path and to each of the last logic blocks of the one or more processing paths configured to output synchronized data.
Olivarez teaches the following limitations: A digital semiconductor device (Fig 1) comprising synchronizer (synchronizer 146 in Fig 1) connected to last logic block in the first processing path and to each of the last logic blocks of the one or more processing paths (101, 102, 103, 104, each core has plurality of logic blocks including Debug 125, 126, 127, 128 ; the last logic blocks debug column 125 – 128 in Fig 1 are connected to synchronizer 146) configured to output synchronized data ([0027] – synchronizer 146 provide output data)
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide a synchronizer to the system of Huang et al, since the synchronizer can synchronize the heterogeneous/asynchronous cores to a common timing domain. The system of Huang is asynchronous (line 54 of col 4). With the teachings from Olivarez, the synchronizer can be deployed in Huang to synchronize various signals to one common timing domain ([0025]-[0027], Olivarez). With proper synchronization, a coherent representation of operation of multiple cores are obtained ([0013], Olivarez).
For claim 2, cited art teaches wherein the first set of logic blocks and second set are arranged in an array of rows (Fig 8 in Huang teaches logic blocks in row direction) and columns (Olivarez teaches logic blocks in column direction Fig 1), the first processing path is a row within the array, and the one or more processing paths form additional rows within the array (Fig 1 of Olivarez and Fig 8 of Huang; logic blocks each pipeline is on the row and the pipelines are on the column).
For claim 3, Olivarez teaches wherein the synchronizer includes a plurality of asynchronous FIFOs ([0027] – asynchronous FIFO buffer, buffer includes plural memory elements).
For claim 5, Huang teaches wherein the forwarded clock is in the same direction as the data flow (Fig 8; both data and clock flows through the successive stages; lines 10-55 of col 5).
For claim 6, Huang teaches wherein the clocks are forwarded mesochronously (Fig 5 shows the clock generator 420 which only delays a single clock and selects a clock where only the delay value is different; thus, the clock is mesochronous).
For claim 7, Huang et al teach the following limitations: A digital semiconductor device (Fig 1; Fig 4 – Fig 9) comprising: an array of logic blocks (Fig 8 shows the array of logic blocks; lines 1-13 of col 8) having a processing structure (processor 310 330 provide pipelined processing; line 50, col 4 through line 5, col 5; lines 1-13 of col 8) to process data having a data flow across multiple hierarchical logic blocks in an array (Fig 4 Fig 8, lines 1-32 of col 8; pipeline 800 has successive stages; each intermediate stage processes input data from previous stage); a clocking structure (Fig 4 – Fig 8 depict the clocking structure; Fig 5 – Fig 7 – 422 is the clock out) where the clock for each logic block in the array follows the data path through the multiple hierarchical logic blocks (Fig 4 and Fig 8; lines 15-30 of col 5; lines 10-13 of col 7; lines 1-32 of col 8 – clock path is shown as 408, 420, 422 through stages in Fig 4 and data path is shown through 402, 410, 406, 404 through stages; the stages of pipeline are hierarchical; Fig 8 shows a pipeline structure with plurality of stages where data flows through the stages and clock follows data via 420) and is configured to asynchronously forward the clock through the multiple hierarchical logic blocks (Fig 4 and Fig 8; lines 10-12 of col 4; lines 14-20 of col 5; asynchronous processor and the clock is not synchronous with any system clock lines 63-65 of col 1).
For the limitations, “end column of logic blocks”, Huang teaches a plurality of separate pipelines 800 with separate CPUs (lines 1-5 of col 5; lines 10-13 of col 8) and therefore, each pipeline has the end stage. These end stages of the pipelines constitute the end column of logic blocks. For further clarification, Examiner cites Olivarez below. Huang does not explicitly mention the following limitations:
a synchronizer connected to a plurality of end logic blocks and outputting synchronized data
Olivarez teaches the following limitations: A digital semiconductor device (Fig 1) comprising an array of logic blocks (101, 102, 103, 104, each core has plurality of logic blocks including Debug 125, 126, 127, 128) having an end column of logic blocks (the debug column 125 – 128 in Fig 1) and a synchronizer connected to a plurality of end logic blocks (synchronizer 146 in Fig 1) and outputting synchronized data ([0027] – synchronizer 146 provide output data).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide a synchronizer to the system of Huang et al, since the synchronizer can synchronize the heterogeneous/asynchronous cores to a common timing domain. The system of Huang is asynchronous (line 54 of col 4). With the teachings from Olivarez, the synchronizer can be deployed in Huang to synchronize various signals to one common timing domain ([0025]-[0027], Olivarez). With proper synchronization, a coherent representation of operation of multiple cores are obtained ([0013], Olivarez).
For claim 8, Olivarez teaches wherein the synchronizer includes a plurality of asynchronous FIFOs ([0027] – asynchronous FIFO buffer, buffer includes plural memory elements).
For claim 10, Huang teaches wherein the forwarded clock is in the same direction as the data flow (Fig 8; both data and clock flows through the successive stages; lines 10-55 of col 5).
For claim 12, Huang teaches wherein the clocks are forwarded mesochronously (Fig 5 shows the clock generator 420 which only delays a single clock and selects a clock where only the delay value is different; thus, the clock is mesochronous).
For claim 25, Huang et al teach the following limitations: A method for processing data by a digital semiconductor device (Fig 1; Fig 4 – Fig 9), the method comprising: receiving the data by a first set of logic blocks (Fig, Fig 8; lines 23-31 of col 8 mention each logic block performs processing on input data), the first set of logic blocks (Fig 8 shows the array of logic blocks; lines 1-13 of col 8) having a processing structure (processor 310 330 provide pipelined processing; line 50, col 4 through line 5, col 5; lines 1-13 of col 8) to process the data along a first processing path (Fig 8; pipeline 800 lines 1-10 of col 8; data is processed along the pipeline), from a first logic block in the first processing path to the last logic block element in the first processing path (Fig 4 Fig 8, lines 1-32 of col 8; pipeline 800 has successive stages; each intermediate stage processes input data from previous stage; pipeline 800 may include five stages); processing the data by the first processing path (lines 1-32 of col 8 mentions how data is processed over the pipeline stages); receiving the data by a second set of logic blocks (lines 10-15 of col 8; line 63, col 4 through line 4, col 5 mention that any number of separate pipelines in CPUs can be included; thus the second pipeline receives data by a second set of logic blocks), the second set of logic blocks having a processing structure to process data along one or more processing paths (the second pipeline has the stages similar to Fig 8; lines 10-15 of col 8; line 63, col 4 through line 4, col 5), from a first logic block for each of the one or more processing paths to and last logic block in the one or more processing paths (Fig 4 Fig 8, lines 1-32 of col 8; pipeline has successive stages; each intermediate stage processes input data from previous stage; thus the separate second pipeline has plurality of stages including blocks to process data along the path from the first stage to the last stage); processing the data by the one or more processing paths (lines 10-15 of col 8; line 63, col 4 through line 4, col 5); generating a clock for each logic block by a clocking structure (Fig 4 – Fig 8 depict the clocking structure; Fig 5 – Fig 7 – 422 is the clock out; Fig 8 shows each stage has corresponding clock that is generated from 420), where the clock for each of the logic blocks in the first processing path follows the data along the first processing path (Fig 4 and Fig 8; lines 15-30 of col 5; lines 10-13 of col 7; lines 1-32 of col 8 – clock path is shown as 408, 420, 422 through stages in Fig 4 and data path is shown through 402, 410, 406, 404 through stages; the stages of pipeline are hierarchical; Fig 8 shows a pipeline structure with plurality of stages where data flows through the stages and clock follows data via 420); asynchronously forwarding the clock from the each of the logic blocks to adjacent logic blocks in the first processing path (Fig 4 and Fig 8; lines 10-12 of col 4; lines 14-55 of col 5; asynchronous processor and the clock is not synchronous with any system clock lines 63-65 of col 1; data is forwarded through 410 404, clock is forwarded through 420; lines 1-31 of col 8), the first processing path being asynchronous with the one or more processing paths (the processor is asynchronous to the extent that there is no global or system clock; lines 14-26 of col 5, lines 10-12 of col 4; lines 25-30 of col 4; the pipelines are asynchronous respect to each other).
Huang et al do not explicitly mention the following limitations:
outputting synchronized data by a synchronizer connected to the last logic block in the first processing path and to each of the last logic blocks of the one or more processing paths.
Olivarez teaches the following limitations: outputting synchronized data by a synchronizer (synchronizer 146 in Fig 1; [0027] – synchronizer 146 provide output data) connected to the last logic block in the first processing path and to each of the last logic blocks of the one or more processing paths (101, 102, 103, 104, each core has plurality of logic blocks including Debug 125, 126, 127, 128; the last logic blocks debug column 125 – 128 in Fig 1 are connected to synchronizer 146).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide a synchronizer to the system of Huang et al, since the synchronizer can synchronize the heterogeneous/asynchronous cores to a common timing domain. The system of Huang is asynchronous (line 54 of col 4). With the teachings from Olivarez, the synchronizer can be deployed in Huang to synchronize various signals to one common timing domain ([0025]-[0027], Olivarez). With proper synchronization, a coherent representation of operation of multiple cores are obtained ([0013], Olivarez).
For claim 26, cited art teaches the processing of the data by the first processing path comprising processing the data by the first set of logic blocks arranged in an array of rows (Fig 8 in Huang teaches logic blocks in row direction) and columns (Olivarez teaches logic blocks in column direction Fig 1), the first processing path is a row within the array, and the one or more processing paths form additional rows within the array (Fig 1 of Olivarez and Fig 8 of Huang; logic blocks each pipeline is on the row and the pipelines are on the column).
For claim 28, Huang teaches the method further comprising forwarding the clock in the same direction as the data flow (Fig 8; both data and clock flows through the successive stages; lines 10-55 of col 5).
For claim 29, Huang teaches method further comprising forwarding the clocks mesochronously (Fig 5 shows the clock generator 420 which only delays a single clock and selects a clock where only the delay value is different; thus, the clock is mesochronous).
For claim 30, Olivarez teaches the outputting further comprising receiving the data by a plurality of First In, First Outs (FIFOs) ([0027] synchronizer includes FIFO buffer – FIFO buffers include plural FIFO elements).
For claim 31, Olivarez teaches method further comprising clocking the First In, First Outs asynchronously from each other ([0027]).
For claim 32, Olivarez teaches method further comprising buffering the data by the First In, First Outs (FIFOs) to synchronize a data output (synchronizer includes FIFO to synchronize data output; [0027]).
Claim(s) 4, 9 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US Patent 9740487) in view of Olivarez et al (US Patent Application Publication 2014/0281735), further in view of Kulmala et al (US Patent Application Publication 20140052951).
For claims 4, 9 and 27, Olivarez et al teach that the synchronizer receives plural data inputs with one input clock and one output clock ([0027]). Huang in view of Olivarez do not mention using read clock and plural write clocks in the synchronizer. Synchronizers with read clock and plural write clocks are known in the art (Fig 1, read clock CLK2 and write clocks CLK1 and WCLK; Kulmala).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide read clock and write clocks since the reading domain is often different from the writing domain. Olivarez uses different types of synchronizing elements with different types of signals ([0027]) and therefore, the write clocks and read clock can be received by the synchronizer for synchronization.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US Patent 9740487) in view of Olivarez et al (US Patent Application Publication 2014/0281735), further in view of Volpe et al (US Patent Application Publication 2022/0350775).
For claim 11, Huang in view of Olivarez mention multiple hierarchical logical blocks (Fig 1 Olivarez; Fig 8 Huang), but does not mention having data and clock path in multiple direction. Volpe et al teach data from multiple directions (Fig 1 A, Fig 2A). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide the data from multiple directions in the system of Huang in view of Olivarez, since the processing of the data can be made faster with plural multi-directional data inputs as shown in Volpe.
Conclusion
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/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175
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