DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6, 8, 10, 14-17 and 19 are rejected under 35 U.S.C. 102a1 as being anticipated by Khlat (US 2012/0313701).
With respect to claim 6, Khlat discloses an apparatus, comprising: a power converter (Fig. 34A 802,16) having a first voltage terminal (Fig. 34A 24) and a second voltage terminal (Fig. 34A 28); and an amplifier (Fig. 34A 35) having a first input (Fig. 12A 206B), a second input (Fig. 12A 206B), and an output (Fig. 12A 206C), the first input and the output coupled to the second voltage terminal (Fig. 12A 28).
With respect to claim 8, Khlat discloses the apparatus of claim 6, further comprising a capacitor (Fig. 12A 18A) coupled between the output of the amplifier (Fig. 12A 206C) and the second voltage terminal (Fig. 12A 28).
With respect to claim 10, Khlat discloses the apparatus of claim 6, further comprising a buffer (Fig. 12A 210) coupled between the output of the amplifier (Fig. 12A 206C) and the second voltage terminal (Fig. 12A 28).
With respect to claim 14, Khlat discloses an apparatus, comprising: a power converter (Fig. 34A 802,16) having a first voltage terminal (Fig. 34A 24) and a second voltage terminal (Fig. 34A 28); and a voltage support circuit (Fig. 34A 35,18) having an input (Fig. 34A 212) and an output (Fig. 34A 28), the input and the output coupled to the second voltage terminal, the voltage support circuit configured to respond to a reduction in an output voltage (Fig. 12A VCC) at the second voltage terminal by increasing the output voltage based on (Fig. 12A 206,208) a reference voltage (Fig. 12A VRAMP) and the output voltage (Fig. 12A VCC).
With respect to claim 15, Khlat discloses the apparatus of claim 14, wherein the voltage support circuit includes an amplifier (Fig. 12A 206) having an input (Fig. 12A 206B) coupled to the input of the voltage support circuit and having an output (Fig. 12A 206C).
With respect to claim 16, Khlat discloses the apparatus of claim 15, further comprising a capacitor (Fig.12A CA) coupled between the output of the amplifier and the second voltage terminal (Fig. 12A 28).
With respect to claim 17, Khlat discloses the apparatus of claim 16, further comprising a buffer (Fig. 12A 210) coupled between the output of the amplifier and the capacitor.
With respect to claim 19, Khlat discloses the apparatus of claim 14, wherein the power converter is a boost converter (Fig 7A 56).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 12-13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (US 2012/0313701) in view of Mottola (US 2007/0216479).
With respect to claim 1, Khlat discloses an apparatus, comprising: a power converter (Fig. 34A 802,16) having a first voltage terminal (Fig. 34A 24) and a second voltage terminal (Fig. 34A 28); an amplifier (Fig. 12A 206) having a first input (Fig. 12A 206B), a second input (Fig. 12A 206A), and an output (Fig. 12A 206), the first input coupled to the second voltage terminal (Fig. 12A 28), the second input coupled to a reference voltage circuit (Fig. 12A 204); a buffer (Fig. 12A 210) having an input coupled to the output of the amplifier and having an output(Fig. 12A 218), and a second capacitor (Fig. 12A 18A) coupled between the output of the buffer and the second voltage terminal (Fig. 12A 28).
Khlat discloses the output of the second voltage supply terminal (Fig. 12A 28) is directly feedback to the amplifier (Fig. 12A 206A) without a voltage divider. The use of voltage divider circuits to reduce the feedback voltage to the amplifier were well known before the effective filing date of the claimed invention. Khlat discloses a voltage divider (Fig. 30 686) coupled between the voltage to be divided (Fig. 30 VDD) and a voltage supply terminal (Fig. 30 ground), the voltage divider having an output (Fig. 30 VDD/2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a voltage divider coupled between the second voltage terminal and a voltage supply terminal, the voltage divider having an output in order to reduce the feedback voltage to the amplifier in order to simplify the amplifier design as was well known before the effective filing date of the invention.
Furthermore, Khlat does not require the amplifier to be a transconductance amplifier. However, the use of transconductance amplifiers were also well known before the effective filing date of the claimed invention. Mottola discloses a transconductance amplifier (Fig. 2 101) coupled to a buffer (Fig. 2 102,124,105,201) and a first capacitor (Fig. 2 104) coupled between the output of the transconductance amplifier (Fig. 2 110) and the voltage supply terminal (Fig. 2 ground symbol). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the amplifier as a transconductance amplifier with a first capacitor coupled between the output of the transconductance amplifier and the voltage supply terminal, to implement the amplifier with high speed and fast turn on capability.
With respect to claims 7, 12, 13 and 18, Khlat in view of Mottola make obvious the apparatus as set forth above. See claim 1 for additional details.
Claim(s) 2-5, 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (US 2012/0313701) in view of Mottola (US 2007/0216479) and further in view of Walter (US 2010/0237840).
With respect to claim 2, Khlat in view of Mottola make obvious the apparatus of claim 1 as set forth above. Khlat remains silent as to the power converter being bidirectional. Nevertheless, it was well known before the effective filing date of the claimed invention to implement wherein the power converter is bidirectional.
Walter discloses a bidirectional power converter (Fig. 1A 10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a bidirectional power converter in order to return power to the source to conserve energy.
With respect to claim 3, Khlat in view of Mottola and Walter make obvious the
apparatus of claim 2 as set forth above, wherein the power converter has an enable input (Walter Fig. 3 250) and is configured to operate as a boost converter when a signal at the enable input is in a first logic state and is configured to operate as a buck converter when the signal is in a second logic state (Walter paragraph 30).
With respect to claim 4, Khlat in view of Mottola and Walter make obvious the
apparatus of claim 3, wherein, when configured to operate as a boost converter (Walter paragraph 47), the power converter is configured to convert a first voltage received at the first voltage terminal to a second voltage at the second voltage terminal.
With respect to claim 5, Khlat in view of Mottola and Walter make obvious the
apparatus of claim 3, wherein the enable input (Walter Fig. 3 250) is a first enable input, the buffer has a second enable input (Mottola Fig. 2 Enable). Khlat teaches selecting the mode of the converter (Fig. 7A 60), but remains silent as to disabling the buffer. Mottola teaches enabling and disabling (Fig. 2 201) the buffer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein: when the second enable input of the buffer is at the first logic state, the buffer is configured to be enabled; and when the second enable input of the buffer is at the second logic state, the buffer is configured to be disabled, in order to enable the ripple cancellation during boost when the ripple cancellation is used, and to disable it during buck mode operation when the ripple cancellation is not used.
With respect to claims 11 and 20, Khlat in view of Mottola and Walters make obvious the apparatus as set forth above. See claim 5 for additional details.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (US 2012/0313701) in view of Walter (US 2010/0237840).
With respect to claim 9, Khlat discloses the apparatus of claim 6 as set forth above, and remains silent as to wherein the power converter is bidirectional. Nevertheless, it was well known before the effective filing date of the claimed invention to implement wherein the power converter is bidirectional.
Walter discloses a bidirectional power converter (Fig. 1A 10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a bidirectional power converter in order to return power to the source to conserve energy.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Matsumoto (US 2024/0288891) discloses power stabilization. Hanson (US 2023/0253878) discloses EMI cancellation. Klotz (US 6,791,303) discloses voltage stabilization. Chu (US 2018/0294714) discloses an EMI filter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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