DETAILED ACTION
Claim Objections
Claims 14-20 are objected to because of the following informalities:
in claim 14, last line, “on difference between” should be ‘on a difference between’.
Appropriate correction is required.
Response to Arguments
Applicant’s arguments with respect to claim(s) the amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The previous primary reference has been replaced with a new primary reference, also by Khlat, US 12,212,285. The new grounds of rejection are presented below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6, 8, 14-16 and 19 are rejected under 35 U.S.C. 102a1 as being anticipated by Khlat (US 12,212,285).
With respect to claim 6, Khlat discloses an apparatus, comprising: a power converter (Fig. 1 16,24A) having a first voltage terminal (Fig. 1 terminal VBAT), a second voltage terminal (Fig. 1 32A), and a reference terminal (Fig. 1 termial VTGTA), the power converter configurable to regulate a first voltage (Fig. 1 VCCA) at the first or second voltage terminals at a second voltage (Fig. 1 VTGTA) at the reference terminal; and an amplifier (Fig. VAA,COFFA) having a first input (Fig. 1 input from 26A), a second input (Fig. 1 input from VTGTA), and an output (Fig. 1 32A), the first input and the output coupled to the second voltage terminal (Fig. 1 32A), and the second input coupled to the reference terminal (Fig. 1 terminal VTGTA).
With respect to claim 8, Khlat discloses the apparatus of claim 6, further comprising a capacitor (Fig. 1 COFFA) coupled between the output of the amplifier (Fig. 1 terminal VAMPA) and the second voltage terminal (Fig. 1 32A).
With respect to claim 14, Khlat discloses an apparatus, comprising: a power converter (Fig. 1 16,24A) having a first voltage terminal (Fig. 1 terminal VBAT), a second voltage terminal (Fig. 1 32A) and a reference terminal (Fig. 1 terminal VTGTA), the power converter configurable to regulate a first voltage (Fig. 1 VCCA) at the first or second voltage terminals at a second voltage (Fig. 1 VTGTA) at the reference terminal; and a voltage support circuit (Fig. 1 VAA,COFFA,26A) having a first input (Fig. 1 feedback input from 26A), a second input (Fig. 1 input VTGTA), and an output (Fig. 1 32A), the first input and the output coupled to the second voltage terminal (Fig. 1 32A), the second input coupled to the reference terminal (Fig. 1 terminal VTGTA), the voltage support circuit configurable to respond to a reduction in the first voltage (Fig. 1 VCCA) by increasing the first voltage based on (Fig. 1 VAA) a difference (Fig. 1 VAMPA) between the first and second voltages (Fig. 1 VTGTA - VCCA).
With respect to claim 15, Khlat discloses the apparatus of claim 14, wherein the voltage support circuit includes an amplifier (Fig. 1 VAA) having inputs (Fig. 1 input from 26A and VTGTA) coupled to the first and second inputs of the voltage support circuit and having an output (Fig. 1 VAMPA).
With respect to claim 16, Khlat discloses the apparatus of claim 15, further comprising a capacitor (Fig.1 COFFA) coupled between the output of the amplifier and the second voltage terminal (Fig. 1 32A).
With respect to claim 19, Khlat discloses the apparatus of claim 14, wherein the power converter is configurable as a boost converter (column 4, lines 33-35).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 10, 12-13 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (US 12,212,285) in view of Mottola (US 2007/0216479).
With respect to claim 1, Khlat discloses an apparatus, comprising: a power converter (Fig. 1 16,24A) having a first voltage terminal (Fig. 1 terminal VBAT), a second voltage terminal (Fig. 1 32A), the power converter configurable to regulate a first voltage (Fig. 1 VCCA) at the first or second voltage terminals at a second voltage (Fig. 1 VTGTA) at the reference terminal; a feedback circuit (Fig. 1 26A) coupled between the second voltage terminal (Fig. 1 32A) and a voltage supply terminal (Fig. 1 return ground not depicted), the feedback circuit having an output (Fig. 1 26A output to VAA); an amplifier (Fig. 1 VAA) having a first input (Fig. 1 input from 26A), a second input (Fig. 1 input VTGTA), and an output (Fig. 1 output VAMPA), the first input coupled to the feedback circuit (Fig. 1 26A), the second input coupled to the reference terminal (Fig. 1 terminal VTGTA); and a second capacitor (Fig. 1 COFFA) coupled between the output of the amplifier and the second voltage terminal (Fig. 1 32A).
Khlat discloses the output of the second voltage supply terminal (Fig. 1 32A) is fedback to the amplifier through a feedback circuit (Fig. 1 26A). Khlat remains silent as to whether the feedback circuit (Fig. 1 FB) is a voltage divider. The use of voltage divider circuits to reduce the feedback voltage to the amplifier were well known before the effective filing date of the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a voltage divider coupled between the second voltage terminal and a voltage supply terminal, the voltage divider having an output in order to reduce the feedback voltage to the amplifier in order to simplify the amplifier design as was well known before the effective filing date of the invention.
Furthermore, Khlat does not require the amplifier to be a transconductance amplifier coupled to a capacitor an output buffer. However, the use of transconductance amplifiers were also well known before the effective filing date of the claimed invention. Mottola discloses a transconductance amplifier (Fig. 2 101) coupled to a buffer (Fig. 2 102,124,105,201), the buffer having an input (Fig. 2 110) coupled to the output of the amplifier (Fig. 2 101), and a first capacitor (Fig. 2 104) coupled between the output of the transconductance amplifier (Fig. 2 110) and the voltage supply terminal (Fig. 2 ground symbol). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the amplifier as a transconductance amplifier with a first capacitor coupled between the output of the transconductance amplifier and the voltage supply terminal; a buffer having an input coupled to the output of the amplifier and having an output; and a second capacitor coupled between the output of the buffer and the second voltage terminal, in order to implement the amplifier with high speed and fast turn on capability, and to provide a buffer to deliver high speed and current capability to the load.
With respect to claims 7, 10, 12, 13 and 17-18, Khlat in view of Mottola make obvious the apparatus as set forth above. See claim 1 for additional details.
Claim(s) 2-5, 11 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (US 2012/0313701) in view of Mottola (US 2007/0216479) and further in view of Walter (US 2010/0237840).
With respect to claim 2, Khlat in view of Mottola make obvious the apparatus of claim 1 as set forth above. Khlat remains silent as to the power converter being bidirectional. Nevertheless, it was well known before the effective filing date of the claimed invention to implement wherein the power converter is bidirectional.
Walter discloses a bidirectional power converter (Fig. 1A 10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the power converter is a bidirectional power converter in order to return power to the source to conserve energy.
With respect to claim 3, Khlat in view of Mottola and Walter make obvious the
apparatus of claim 2 as set forth above, wherein the power converter has an enable input (Walter Fig. 3 250) and is configurable to operate as a boost converter (Khlat column 4, lines 33-35, Walter paragraph 47) when a signal at the enable input is in a first logic state and is configured to operate as a buck converter when the signal is in a second logic state (Walter paragraph 30).
With respect to claim 4, Khlat in view of Mottola and Walter make obvious the
apparatus of claim 3, wherein, the power converter is configurable to convert a first voltage (Fig. 1 VBAT) received at the first voltage terminal to a second voltage (Fig. 2 VCCA) at the second voltage terminal when operating as the boost converter.
With respect to claim 5, Khlat in view of Mottola and Walter make obvious the
apparatus of claim 3, wherein the enable input (Walter Fig. 3 250) is a first enable input, the buffer has a second enable input (Mottola Fig. 2 Enable). Khlat teaches selecting the mode of the converter (Fig. 7A 60), but remains silent as to disabling the buffer. Mottola teaches enabling and disabling (Fig. 2 201) the buffer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein: when the second enable input of the buffer is at the first logic state, the buffer is enabled; and when the second enable input of the buffer is at the second logic state, the buffer is disabled, in order to enable the ripple cancellation during boost when the ripple cancellation is used, and to disable it during buck mode operation when the ripple cancellation is not used.
With respect to claims 11 and 20, Khlat in view of Mottola and Walter make obvious the apparatus as set forth above. See claim 5 for additional details.
With respect to claim 21, Khlat in view of Mottola make obvious the apparatus of claim 1 as set forth above. Khlat remains silent as to wherein the second voltage terminal is coupled to a universal serial bus (USB) port. It was well known before the effective filing date of the claimed invention to implement wherein the second voltage terminal is coupled to a universal serial bus (USB) port.
Walter teaches wherein the second voltage terminal is coupled to a universal serial bus (USB) port (Fig. 1B 33). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the second voltage terminal is coupled to a universal serial bus (USB) port, in order to provide power to the load over the widely available USP port connection.
With respect to claim 22, Khlat in view of Mottola and Walter make obvious the apparatus of claim 21, further comprising a device (Fig. 1B 20) coupled to the second voltage terminal via the USB port, the device including a battery (Fig. 5 312).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khlat (US 2012/0313701) in view of Walter (US 2010/0237840).
With respect to claim 9, Khlat discloses the apparatus of claim 6 as set forth above, and remains silent as to wherein the power converter is bidirectional. Nevertheless, it was well known before the effective filing date of the claimed invention to implement wherein the power converter is bidirectional.
Walter discloses a bidirectional power converter (Fig. 1A 10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a bidirectional power converter in order to return power to the source to conserve energy.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. El-Nozahi (US 2014/0266104) and (US 2014/0266106) disclose use of a transconductance amplifier in a capacitorless LDO.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HARRY R BEHM/Primary Examiner, Art Unit 2838
Prosecution Insights