DETAILED ACTION
This office action is in response to the application filed on 06/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 11-14 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al. US 2001/0026460.
Regarding Claim 1, Ito teach (Figures 1-12) a power-conditioning system (Fig. 1) comprising: a load output (at 11) configured to be coupled to a load (11); a power-factor-correction circuit (L1, s1-s4 and C) having an input configured to be connected to an input power source (see fig. 1, at 4-5), the PFC comprising a first switching leg and a second switching leg (S1-S4), wherein the first switching leg and the second switching leg are configured to be controlled based on a first modulation index (See fig. 5, same controlled modulation); an inverter (s3-s5) configure to provide electrical power to the load output (see fig. 1, at 6-7), the inverter comprising the second switching leg and a third switching leg, wherein the third switching leg is configured to be controlled based on a second modulation index (s5-s6 modulation control according to fig. 5); and a capacitor (c2) coupled to an inverter output (at 6) of the inverter and being coupled in series with the load output (11). (For example: Par. 60-74)
Regarding Claims 2 and 12, Ito teach (Figures 1-12) wherein the first modulation index is different than the second modulation index (see fig. 5, the operation is different and see fig. 10-12 with Vr1-vr3 values and ranges). (For example: Par. 118-128)
Regarding Claim 3, Ito teach (Figures 1-12) further comprising at least one controller (2) coupled to the PFC and the inverter (see fig. 1).
Regarding Claims 4 and 13, Ito teach (Figures 1-12)wherein the at least one controller (2) is configured to modify at least one of the first modulation index or the second modulation index (see the operation between figures 4-5 and the levels for the Vr1-Vr3 signals at figures 10-12) to modify an output AC voltage output by the inverter (buck and boost modes). (For example: Par. 60-74 and 118-128)
Regarding Claims 5 and 14, Ito teach (Figures 1-12) wherein modifying a value of the at least one of the first modulation index or the second modulation index modifies a phase of the output AC voltage (phase is modified by the operation of the system with the boost and buck modes). (For example: Par. 60-74 and 118-128)
Regarding Claim 6, Ito teach (Figures 1-12)further comprising a first AC input and a second AC input (fig. 1, terminals 4-5).
Regarding Claim 7, Ito teach (Figures 1-12)wherein the first AC input is coupled to the capacitor (6, through operation of the system) and to a midpoint of the second switching leg (at 9 and 5).
Regarding Claim 8, Ito teach (Figures 1-12) further comprising an inductor (L1) having a first connection coupled to the second AC input (when the combination of S1 and S4 or S2 and S3 are one the current loop formed makes the elements connected) and a second connection coupled to a midpoint of the first switching leg (at 8, fig. 1).
Regarding Claim 9, Ito teach (Figures 1-12) further comprising an inductor (L2) having a first connection coupled to the load output (at 11) and a second connection coupled to a midpoint of the third switching leg (10).
Regarding Claim 11, Ito teach (Figures 1-12) a method of operating a load-conditioning system (Fig. 1) comprising a load output (at 11) configured to be coupled to a load (11), a power-factor-correction circuit (L1, s1-s4 and C) comprising a first switching leg and a second switching leg (s1-s4), an inverter (s3-s6) comprising the second switching leg and a third switching leg (s3-s6), and a capacitor (c2) coupled to an inverter output (at 6) of the inverter and being coupled in series with the load output, the PFC having an input configured to be connected to an input power source (see fig. 1, at 4-5 ), and the inverter configured to provide electrical power to the load output (see fig. 1, at 6-7), the method comprising: controlling the first switching leg and the second switching leg (s1-s4) based on a first modulation index(See fig. 5, same controlled modulation); controlling the third switching leg based on a second modulation index (s5-s6 modulation control according to fig. 5); and providing, by the inverter, an output AC voltage (Vo) to the capacitor based on the first modulation index and the second modulation index(with 2). (For example: Par. 60-74)
Regarding Claim 21, Ito teach (Figures 1-12) a power-conditioning system (Fig. 1) comprising: a load output (at 11) configured to be coupled to a load (11); a power-factor-correction circuit (L1, s1-s4 and C) having an input configured to be connected to an input power source (see fig. 1, at 4-5), the PFC comprising a first switching leg and a second switching leg (S1-S4), wherein the first switching leg and the second switching leg are configured to be controlled based on a first switching frequency (See abstract, 50hz); an inverter (s3-s5) configure to provide electrical power to the load output (see fig. 1, at 6-7), the inverter comprising the second switching leg and a third switching leg, wherein the third switching leg is configured to be controlled based on a second switching frequency (see abstract, 20khz); and a capacitor (c2) coupled to an inverter output (at 6) of the inverter and being coupled in series with the load output (11). (For example: Par. 43-52)
Claim(s) 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schneider et al. US 9787211.
Regarding Claim 19, Ito teach (Figures 1 and 9-17) a non-transitory computer-readable medium storing thereon sequences of computer-executable instructions (see col. 15 lines 1-12) for operating a load-conditioning system (fig. 9) comprising a load output (at Vo) configured to be coupled to a load (108), a power-factor-correction circuit (S3-S5, Li, C3, 1101 and 206) comprising a first switching leg and a second switching leg(s3-s5), an inverter (s1-s4) comprising the second switching leg and a third switching leg (S1-s4), and a capacitor (C2) coupled to an inverter output of the inverter (at Vo) and being coupled in series with the load output (108), the PFC having an input configured to be connected to an input power source (see fig. 1, at 101 ), and the inverter configured to provide electrical power to the load output (see fig. 1, at 108), the sequences of computer-executable instructions including instructions that instruct at least one processor to: control the first switching leg and the second switching leg based on a first modulation index (see table 1); control the third switching leg based on a second modulation index (see table 2); and provide, by the inverter, an output AC voltage (Vo) to the capacitor based on the first modulation index and the second modulation index (with 102). (For example: Col. 7-11)
Regarding Claim 20, Schneider teach (Figures 1 and 9-17) wherein the instructions further instruct the at least one processor (see col. 15 lines 1-12) to modify at least one of the first modulation index or the second modulation index to modify the output AC voltage (with the operation as mentioned in tables 1 and 2). (For example: Col. 7-11)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Maoh A modular three-phase voltage regulator with fictitious dc-link.
Regarding Claim 10, Ito teach (Figures 1-12) the capacitor.
Ito does not teach wherein the capacitor is coupled in parallel with the inverter.
Maoh teaches (Figure 4) wherein the capacitor is coupled in parallel with the inverter. (see Section III)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Ito to include wherein the capacitor is coupled in parallel with the inverter as taught by Maoh to provide compensation to the system in response to voltage disturbances.
Regarding Claim 15-17, Ito teach (Figures 1-12) the capacitor.
Ito does not teach further comprising receiving, from an input coupled in series with the capacitor, an input AC voltage; wherein providing the output AC voltage to the capacitor includes generating a differential voltage across the capacitor, the output AC voltage being in-phase with the input AC voltage; further comprising providing, by the capacitor, a load AC voltage to the load, wherein the load AC voltage is a sum of the input AC voltage and the output AC voltage.
Maoh teaches (Figures 4-5) further comprising receiving, from an input coupled in series with the capacitor (Fig. 4. At Vs), an input AC voltage (Vs); wherein providing the output AC voltage to the capacitor includes generating a differential voltage across the capacitor (Vsr across Cf capacitor which receives Vs and the voltage from the inverter with switches s5-s6), the output AC voltage being in-phase with the input AC voltage (see fig. 5, Vs and Vo); further comprising providing, by the capacitor, a load AC voltage to the load (VL), wherein the load AC voltage is a sum of the input AC voltage and the output AC voltage (the charge accumulated by the capacitor by receiving power from Vs and the converter module). (see Section III)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Ito to include further comprising receiving, from an input coupled in series with the capacitor, an input AC voltage; wherein providing the output AC voltage to the capacitor includes generating a differential voltage across the capacitor, the output AC voltage being in-phase with the input AC voltage; further comprising providing, by the capacitor, a load AC voltage to the load, wherein the load AC voltage is a sum of the input AC voltage and the output AC voltage, as taught by Maoh to provide compensation to the system in response to voltage disturbances.
Regarding Claim 18, Ito teach (Figures 1-12) further comprising selecting at least one of the first modulation index and the second modulation index to maintain the load AC voltage at a desired level (using one of the operation modes of figures 3-5, either as buck or boost modes of operation). (For example: Par. 60-74 and 118-128)
Response to Arguments
Applicant's arguments filed 06/11/2026 have been fully considered but they are not persuasive.
Applicant argued that “Therefore, nowhere does Ito disclose at least "wherein the first switching leg and the second switching leg [of the power-factor correction circuit] are configured to be controlled based on a first modulation index," as recited in independent claim 1 and as similarly recited in independent claims 11 and 19. None of the other references of record remedy this deficiency of Ito”. However, the claims recite that the switching legs are controlled based on a first modulation index without any further details about the modulation index. Ito teaches in Figure 5 an operation mode of the switching legs where the system operates in step-up mode and the first modulation index is used in the operation of switches S1-S4 as is shown in said figure and paragraphs 64-74.
Applicant argued that “Thus, only switches S3 and S4 are modulated according to table 1. Moreover, nowhere does table 1 indicate any two sets of switches sharing a common modulation index. Therefore neither Ito nor Schneider discloses such a limitation as recited in each of independent claims 1, 11 and 19”. However, par. 58 of the application’s PG Pub recite “The first modulation-index trace 510 is a sinusoidal wave oscillating between +0.8 and −0.8, which represents a modulation index for the control signals provided to the second switching leg 312. The modulation index represents a peak value of the fundamental waveform divided by a DC-bus voltage on the DC-power capacitor 306”. Schneider table 1 on the first row says at the end and s5-s6 modulate VLI this means that the system and said table modulate more than two switches as mentioned by the applicant. Also, the values mentioned in the table 1 provide the operation of the system which dictate the modulation index used to control the operation of the switches S3-S6. Schneider teaches for example, when Switch 1 is on the combination of switches being turn on and off is 4-5, 4-6, 3-5 and 3-6 and this is the modulation index when S1 is turned on.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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