DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 5, 6, 11, 12, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 9,439,301).
With respect to claim 1, Jeon teaches a multilayer ceramic capacitor (see abstract) comprising: a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated (see FIG. 2, body 12, dielectric layers 52/54 and internal electrodes 22/24; see col. 4, lines 60-67); and external electrodes each on a corresponding one of end surfaces in a length direction perpendicular or substantially perpendicular to a lamination direction of the multilayer body, the external electrodes each being connected to the plurality of internal electrode layers (see FIG. 2, external electrodes 42/44 and col. 5, lines 26-31); wherein a surface, in a plan view in the length direction, of each of the external electrodes is covered with an insulating layer (see FIG. 2, insulating layer 80 and col. 6, lines 56-59) except for a frame region (see FIG. 2, noting that the insulating layer 80 does not cover the entirety of the surface of the external electrode layers, leaving a frame region).
Jeon fails to explicitly teach that the frame region has a width of about 1 µm or more and about 100 µm or less from an outer peripheral edge of the surface.
However, Jeon teaches that the insulating layer 80 decreases the height of the solder fillets (see FIG. 6 and col. 6, lines 31-36), which is known to reduce the transfer of vibrations from the ceramic chip capacitor to a printed circuit board on which the capacitor is mounted (see col. 1, lines 52-56). Accordingly, Jeon clearly indicates that the sizing of the insulating layer 80 is a result-oriented variable minimize vibrations from ceramic chip capacitor. As such, it would have been obvious to one of ordinary skill in the art to optimize the sizing of the insulating layer, through routine experimentation, such that it has a frame region that is 1 µm or more and about 100 µm or less from an outer peripheral edge of the surface. See MPEP 2144.05(II)(A) and (B), citing In re Stepan, 868 F.3d 1342, 1346, 123 USPQ2d 1838, 1841 (Fed. Cir. 2017) and In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Further, the Office notes that the difference between the prior art and the instant claims is merely a change in size/proportion, which has been determined to be obvious as being well within the purview of one of ordinary skill in the art. See MPEP 2144.04(IV)(A), citing Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984). Finally, the Office submits that the instant specification fails to establish any criticality to the sizing of the insulating layer, as the instant specification merely notes that the frame region establishes the sizing of the solder fillet to be within “a certain height.” See paragraph [0053] of the instant specification. There is no discussion or comparative examples disclosing the level of vibration occurring when the frame region is outside the range recited in claim 1.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Jeon by optimizing the sizing of the insulting layer, in order to decrease the height of the solder fillets that connect the ceramic chip capacitor to an external printed wiring board and reduce the transfer of vibrations between the same.
With respect to claim 2, Jeon teaches that a surface, in a plan view in the length direction, of each of the external electrodes corresponding to a region in which the internal electrode layers are laminated is covered with the insulating layer. See FIG. 2.
With respect to claim 5, Jeon teaches that the multilayer body includes an inner layer portion and outer layer portions on both sides of the inner layer portion in the lamination direction; the inner layer portion includes dielectric layers of the plurality of dielectric layers and the plurality of internal electrode layers; and each of the outer layer portions includes dielectric layers of the plurality of dielectric layers, but does not include any of the plurality of internal electrode layers. See FIG. 2, active region 60, upper cover layer 53, and lower cover layer 55; see also col. 5, lines 46-49.
With respect to claim 6, Jeon teaches that each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component. See col. 5, lines 13-21.
With respect to claim 11, Jeon discloses a mounting structure of a multilayer ceramic capacitor (see FIG. 6), the mounting structure comprising: a multilayer ceramic capacitor according to claim 1 (see FIG. 6, element 10, and the rejection of claim 1); a land on a wiring board (see FIG. 6, elements 122/124); and a solder connecting the land and a corresponding one of the external electrodes of the multilayer ceramic capacitor to each other (see FIG. 6, elements 142/144); wherein the solder is provided below an insulating layer (see FIG. 6, noting in the inset that the solder fillets are below the insulating layer 80).
With respect to claim 12, Jeon discloses that a surface, in a plan view in the length direction, of each of the external electrodes corresponding to a region in which the internal electrode layers are laminated is covered with the insulating layer. See FIG. 6, element 80; see also, FIG. 2).
With respect to claim 15, Jeon teaches that the multilayer body includes an inner layer portion and outer layer portions on both sides of the inner layer portion in the lamination direction; the inner layer portion includes dielectric layers of the plurality of dielectric layers and the plurality of internal electrode layers; and each of the outer layer portions includes dielectric layers of the plurality of dielectric layers, but does not include any of the plurality of internal electrode layers. See FIG. 2, active region 60, upper cover layer 53, and lower cover layer 55; see also col. 5, lines 46-49.
With respect to claim 16, Jeon teaches that each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component. See col. 5, lines 13-21.
Claims 4, 7-10, 14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 9,439,301) in view of Chikuma et al. (US Pat. App. Pub. No. 2021/0125785).
With respect to claim 4, Jeon fails to teach that the multilayer ceramic capacitor has a dimension in the lamination direction of about 0.1 mm to about 2.5 mm, a dimension in the length direction of about 0.1 mm to about 3.2 mm, and a dimension in the width direction of about 0.1 mm to about 2.5 mm.
Chikuma, on the other hand, teaches that the multilayer ceramic capacitor has a dimension in the lamination direction of about 0.1 mm to about 2.5 mm, a dimension in the length direction of about 0.1 mm to about 3.2 mm, and a dimension in the width direction of about 0.1 mm to about 2.5 mm. See paragraph [0050]. Such a modification maintains a reduced sizing for the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having a desired reduced size.
With respect to claim 7, Jeon fails to teach that each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as an auxiliary component.
Chikuma, on the other hand, teaches that each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as an auxiliary component. See paragraph [0053]. Such an arrangement produces the desired characteristics for the dielectric layers.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having a desired reduced size.
With respect to claim 8, Jeon fails to explicitly teach that a thickness of each of the plurality of dielectric layers in the inner layer portion is about 0.3 µm to about 2.0 µm.
Chikuma, on the other hand, teaches teach that a thickness of each of the plurality of dielectric layers in the inner layer portion is about 0.3 µm to about 2.0 µm. See paragraph [0052], citing a thickness of 0.5 to 10 µm. Such a modification maintains a desired size and capacitance for the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having a desired reduced size.
With respect to claim 9, Jeon fails to explicitly teach that each of the outer layer portions has a thickness of about 15 µm to about 150 µm.
Chikuma, on the other hand, teaches that each of the outer layer portions has a thickness of about 15 µm to about 150 µm. See paragraph [0052], noting a thickness T1 of 100 to 200 µm. Such an arrangement maintains a desired size for the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having a desired reduced size.
With respect to claim 10, Jeon fails to explicitly teach that each of the inner electrode layers includes Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.
Chikuma, on the other hand, teaches that each of the inner electrode layers includes Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. See paragraph [0054]. Such a modification is known in the art as a design choice to produce the desired electrical characteristics.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having the desired electrical characteristics.
With respect to claim 14, Jeon fails to teach that the multilayer ceramic capacitor has a dimension in the lamination direction of about 0.1 mm to about 2.5 mm, a dimension in the length direction of about 0.1 mm to about 3.2 mm, and a dimension in the width direction of about 0.1 mm to about 2.5 mm.
Chikuma, on the other hand, teaches that the multilayer ceramic capacitor has a dimension in the lamination direction of about 0.1 mm to about 2.5 mm, a dimension in the length direction of about 0.1 mm to about 3.2 mm, and a dimension in the width direction of about 0.1 mm to about 2.5 mm. See paragraph [0050]. Such a modification maintains a reduced sizing for the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having a desired reduced size.
With respect to claim 17, Jeon fails to teach that each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as an auxiliary component.
Chikuma, on the other hand, teaches that each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as an auxiliary component. See paragraph [0053]. Such an arrangement produces the desired characteristics for the dielectric layers.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having a desired reduced size.
With respect to claim 18, Jeon fails to explicitly teach that a thickness of each of the plurality of dielectric layers in the inner layer portion is about 0.3 µm to about 2.0 µm.
Chikuma, on the other hand, teaches teach that a thickness of each of the plurality of dielectric layers in the inner layer portion is about 0.3 µm to about 2.0 µm. See paragraph [0052], citing a thickness of 0.5 to 10 µm. Such a modification maintains a desired size and capacitance for the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having a desired reduced size.
With respect to claim 19, Jeon fails to explicitly teach that each of the outer layer portions has a thickness of about 15 µm to about 150 µm.
Chikuma, on the other hand, teaches that each of the outer layer portions has a thickness of about 15 µm to about 150 µm. See paragraph [0052], noting a thickness T1 of 100 to 200 µm. Such an arrangement maintains a desired size for the capacitor.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having a desired reduced size.
With respect to claim 20, Jeon fails to explicitly teach that each of the inner electrode layers includes Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.
Chikuma, on the other hand, teaches that each of the inner electrode layers includes Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. See paragraph [0054]. Such a modification is known in the art as a design choice to produce the desired electrical characteristics.
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify Jeon, as taught by Chikuma, in order to produce a capacitor having the desired electrical characteristics.
Allowable Subject Matter
Claims 3 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: with respect to claims 3 and 13, the prior art fails to teach, or fairly suggest, that the insulating layer has a thickest portion in a middle as viewed in the length direction, when taken in conjunction with limitations of base claims 1 and 11, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al. (US 2019/0278921) and Chae et al. (US 2017/0367187) each teach a capacitor having an insulating layer on the surface of the external electrodes, but fails to teach the details of the insulating layer recited claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DION R. FERGUSON/Primary Examiner, Art Unit 2848