DETAILED ACTION
Remarks
The present application was filed 1 July 2024.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
The drawings filed 1 July 2023 are acceptable for examination purposes.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
As to claim 20, the claim is directed to a computer-readable medium, which one of ordinary skill would normally understand as including a transitory signal. Paragraph [0015] also discloses such a medium can include “any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.” The claim is thus directed to a transitory signal per se. Transitory signals per se are non-statutory subject matter. See M.P.E.P. § 2106.03(I).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 11 and 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 9, the claim refers to high-performance and low-performance cores but the specification does not provide any standard for determining the level a performance a core must possess in order to be considered high or low performance. Nothing of record suggests one of ordinary skill would nonetheless be able ascertain the scope of the claim either. The claim is therefore indefinite. For the purposes of examination, any core that performs higher relative to another core will be construed as a high-performance core and any core that performs lower relative to another core will be construed as a low performance core.
As to claim 11, the claim refers to “the forked processes” but only provides antecedent basis for one forked process. It is thus unclear to which additional forked process the claim is referring. For the purposes of examination “the forked processes” will be interpreted as -the forked process-.
As to claims 17-18, the claims refer to “the” instructions in line 1 of each claim. However, claim 16, from which claims 17-18 depend refers to memory storing instructions as well as instructions based on the second ISA and instructions based on the first ISA. It is thus unclear to which instructions lines 1 of claims 17-18 are referring. For the purposes of examination, line 1 of claims 17-18 will be interpreted as referring to the instructions stored in the memory of claim 16.
11. The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 2-3, 7 and 12-15 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
As to claims 2-3, 7 and 12-15, these claims are all dependent on claim 1 and al; further describe contingent limitations of claim 1. Those contingent limitations, under the broadest reasonable interpretation, are not required by the claim. See M.P.E.P. § 2111.04(II). Thus, all limitations of claims 2-3, 7 and 12-15 are not required under the broadest reasonable interpretation either. They accordingly do not further limit claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 12, 14, 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Segelken et al. (US 2014/0317382) (art made of record – hereinafter Segelken) in view of Lahteenmaki et al. (US 2015/0261543) (art made of record – hereinafter Lahteenmaki).
As to claim 1, Segelken discloses a method of operation of a computing device, comprising:
determining, by the dispatching service, whether the application uses a first instruction set architecture (ISA) or a second ISA; (e.g., Segelken, par. [0014]: type determining logic is configured to determine, at runtime, whether fetched instruction code is non-native ISA code [second ISA] or native ISA code [first ISA])
in response to determining that the application uses the second ISA, determining whether the application is compute-bound or non-compute-bound; (e.g., Segelken, par. [0016]: a native translation may be generated for portions of non-ISA [second ISA] code that are executed frequently or consume substantial processing time [are compute-bound])
in response to determining that the application is compute-bound, performing binary translation to convert instructions based on the second ISA from the application to instructions based on the first ISA; (see immediately above) and
executing the instructions based on the first ISA on one or more cores supporting the first ISA (e.g., Segelken, par. [0017]: to allow the processing pipeline to retrieve and execute a translation; par. [0005]: non-native code has to be translated in order to be executed by the micro-processing system; Fig. 1 and associated text, par. [0009]: an example micro-processing system 100 including processing core 102; par. [0024]: instruction code may be executed by execution stage 126 [of the core, see figure]; par. [0009]: it will be appreciated that the micro-processing system may include additional processor cores).
Segelkin does not explicitly disclose receiving, by a dispatching service, an application start request for an application.
However, in an analogous art, Lahteenmaki discloses:
receiving, by a dispatching service, an application start request for an application (e.g., Lahteenmaki, par. [0122]: embodiments of the invention may be implemented in hardware, software, or any combination; par. [0079]: when an application is selected to be started, e.g., by a user of the apparatus or as a consequence of a call from another program [the software portion receiving the selection or call being the dispatching service], the operating system fetches the code to memory 58 so that multicore processor 102 can start running the program portions of the OS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dispatcher service of Segelken to include receiving, an application start request for an application, as taught by Lahteenmaki, as Lahteenmaki would provide the advantage of a means of initiating execution of the application. (See Lahteenmaki, par. [0079]).
As to claim 2, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above), Segelken further discloses further comprising:
in response to determining that the application uses the first ISA, executing the application on one or more cores supporting the first ISA without performing binary translation (e.g., Segelken, par. [0005]: native ISA code may be directly executed by the micro-processing system without having to be translated; Fig. 1 and associated text, par. [0009]: an example micro-processing system 100 including processing core 102; par. [0024]: instruction code may be executed by execution stage 126 [of the core, see figure] )
As to claim 3, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above), Segelken further discloses further comprising:
in response to determining that the application is non-compute-bound, executing the application on one or more cores supporting the second ISA without performing binary translation (e.g., Segelken, par. [0016]: there may be substantial overhead costs associated with generating an optimized native translation of non-native ISA code. Accordingly, a native translation may be generated for portions of non-native ISA code that are generated frequently or consume substantial processing time [i.e., native translation is only generated for code that is generated frequently or consumes substantial processing time (is compute bound)]; par. [0005] non-native ISA [second ISA] code has to be decoded or translated in order to be executed by the micro-processing system; Fig. 1 and associated text, par. [0021]: HWD 124 is used to decode non-native ISA code for execution via the execution logic 126 [of core 102, see figure]).
As to claim 5, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 5 above), Segelken further discloses further comprising:
collecting runtime profile results of the application, wherein the application is determined to be compute-bound or non-compute-bound according to the runtime profile results (e.g., Segelken, par. [0016]: a native translation may be generated for portions of non-native ISA code that are executed frequently or consume substantial processing time, such as frequently used or "hot" loops or functions. In some embodiments, code portions of non-native ISA code may be profiled in order to identify whether and how those code portions should be included in new or reformed translations. For example, profiled code portions may be identified and defined by taken branches. In another example, a translation may be generated for a portion of non-native ISA code in response to that code portion being executed a threshold number of times).
As to claim 7, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above), Segelken further discloses: wherein performing binary translation comprises at least one of:
translating instructions from the second ISA to the first ISA; (e.g., Segelken, par. [0016]: to generate native ISA [first ISA] code [instructions] that includes translation of corresponding portions of non-native ISA [second ISA] code [instructions])
mapping registers from the second ISA to registers of the first ISA; and
converting system calls from a format of the second ISA to a format of the first ISA.
As to claim 10, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above), Segelken further discloses further comprising:
in response to determining that the application uses the second ISA and is compute-bound, passing application information to a first execution service that initiates the binary translation (e.g., Segelken, par. [0016]: a native translation of non-native ISA code may be created by a translation system that is executed by a software layer [i.e., translating instructions requires passing them to some translation logic. Note that the translation is performed in response to determining the application uses the second ISA and is compute-bound as set forth above with respect to claim 1]).
As to claim 12, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above), Segelken further discloses further comprising:
in response to determining that the application uses the second ISA and is non-compute-bound, passing application information to a second execution service that does not initiate the binary translation (e.g., Segelken, par. [0005]: non-native code has to be decoded or translated; par. [0016]: there may be substantial overheard associated with generating an optimized native translation. Accordingly, a native translation may be generated for portions of non-ISA code that are executed frequently or consume substantial processing time [are compute-bound]; par. [0027]: since the fetched instruction code is identified as non-native ISA code, the non-native ISA code is directed through a DECODE processing stage that uses the HWD in order to decode the non-native ISA code)
As to claim 14, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above), Segelken further discloses further comprising:
in response to determining that the application uses the first ISA, passing application information to a third execution service that does not initiate the binary translation (e.g., Segelken, Fig)
As to claim 16, it is a device claim having limitations substantially the same as those of claim 1. Accordingly, it is rejected to substantially the same reasons. Further limitations, disclosed by Lahteenmaki, include:
one or more processors; (e.g., Lahteenmaki, par. [0123]: a data processor of the apparatus) and
memory storing instructions that, when executed by the one or more processors, cause the computing device to (e.g., Lahteenmaki, par. [0123]: embodiments may be implemented by computer software executable by a data processor of the apparatus. The software may be stored in physical media such as memory chips) perform the operations.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Segelken such that it is embodied in instructions that when executed by the one or more processors, cause a computing device to perform the method, as taught by Lahteenmaki, as Lahteenmaki would provide the advantage of a means of implementing the method in computer software and performing the method using a programmable computer. (See Lahteenmaki, par. [0123]).
As to claim 17, it is a device claim having limitations substantially the same as those of claim 2. Accordingly, it is rejected to substantially the same reasons.
As to claim 18, it is a device claim having limitations substantially the same as those of claim 3. Accordingly, it is rejected to substantially the same reasons.
As to claim 20, it is a medium claim having limitations substantially the same as those of claim 1. Accordingly, it is rejected to substantially the same reasons. Further limitations, disclosed by Lahteenmaki, include:
a computer-readable medium storing computer executable code for operation of a computing device, comprising code to (e.g., Lahteenmaki, par. [0123]: embodiments may be implemented by computer software executable by a data processor of the apparatus. The software may be stored in physical media such as memory chips) perform the operations.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Segelken such that it is embodied in computer executable code stored on a computer-readable medium for operation of a computing device, as taught by Lahteenmaki, as Lahteenmaki would provide the advantage of a means of implementing the method in computer software and performing the method using a programmable computer. (See Lahteenmaki, par. [0123]).
Claims 4, 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Segelken (US 2014/0317382) in view of Lahteenmaki (US 2015/0261543) in further view of Tian et al. (US 2021/0311925) (art made of record – hereinafter Tian).
As to claim 4, Segelken/ Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above), but does not explicitly disclose wherein the application is determined to be compute-bound or non-compute-bound according to a static dispatching policy based on an application signature, wherein the application signature includes at least one of an application name, an application category, and a library dependency.
However, in an analogous art, Tian discloses:
wherein the application is determined to be compute-bound or non-compute-bound according to a static dispatching policy based on an application signature, wherein the application signature includes at least one of an application name, an application category, and a library dependency (e.g., Tian, par. [0030]: a blockchain transaction [application] can include instructions executed by a blockchain node; par. [0112]: a bound type “(e.g., CPU-bound or I/O bound)” of one or more transactions may be determined based on transaction types [application category] of the one or more blockchain transactions. For example, a type that does not include I/O operations “(e.g., an encryption transaction, a native smart contract transaction)” can be considered as CPU-bound).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the determination of compute-bound taught by Segelken to include determining the application is compute-bound or non-compute-bound according to a static dispatching policy based on an application signature, wherein the application signature includes at least one of an application name, an application category, and a library dependency, as taught by Tian, as Tian would avoid the overhead of other means of making the determination, such as profiling or machine learning models. (See Segelken, par. [0016] and Tian, par. [0113]).
As to claim 6, Segelken/Lahteenmaki disclose the method of claim 1 (see rejection of claim 1 above) but does not explicitly disclose wherein the application is determined to be compute-bound or non-compute-bound according to an artificial intelligence (AI) model pre-trained with runtime profile results.
However, in an analogous art, Tian discloses:
wherein the application is determined to be compute-bound or non-compute-bound according to an artificial intelligence (AI) model pre-trained with runtime profile results (e.g., Tian, par. [0030]: a blockchain transaction [application] can include instructions executed by a blockchain node; par. [0113]: a machine learning algorithm can be used to build a blockchain transaction model based on training data. The training data may include historical transaction data of the processing apparatus “(e.g., transaction types of processed [executed] blockchain transactions)”. The blockchain transaction model can predict whether a blockchain transaction of a particular transaction type will be I/O bound or CPU bound).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the determination of compute-bound taught by Segelken to include making determining the application is compute-bound according to an artificial intelligence (AI) model pre-trained with runtime profile results, as taught by Tian, as Tan would provide the advantage of a means of making the determination using machine learning (see Tian, par. [0113]), which would enable the computer to make the determination without explicitly programming to do so and permit improved predictions over time.
As to claim 19, it is a device claim having limitations substantially the same as those of claim 4. Accordingly, it is rejected to substantially the same reasons.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Segelken (US 2014/0317382) in view of Lahteenmaki (US 2015/0261543) in further view of Zaarur et al. (US 2013/0061237) (art made of record – hereinafter Zaarur).
As to claim 8, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above) but does not explicitly disclose wherein the first ISA is a 64-bit ISA and the second ISA is a 32-bit ISA.
However, in an analogous art, Zaarur discloses:
wherein the first ISA is a 64-bit ISA and the second ISA is a 32-bit ISA (e.g., Zaarur, par. [0033]: Core 1 202 may support a 64-bit instruction set; par. [0034]: Core-2 204 may support a subset of a full 32-but instruction set).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second ISAs taught by Segelken such that they include a 64-bt ISA for a first core and a 32-bit ISA for a second core, as taught by Zaarur, as Zaarur would provide the advantage of a means of reducing the energy consumed for certain tasks without comprising performance. (See Zaarur, pars. [0060], [0058]).
As to claim 9, Segelken/Lahteenmaki discloses the method of claim 1 (see rejection of claim 1 above), but does not explicitly disclose wherein the one or more cores supporting the first ISA are one or more high-performance cores, and wherein the computing device further comprises one or more low-performance cores supporting the second ISA.
However, in an analogous art, Zaarur discloses:
wherein the one or more cores supporting the first ISA are one or more high-performance cores, and wherein the computing device further comprises one or more low-performance cores supporting the second ISA (e.g., Zaarur, par. [0033]: Core 1 202 may support a 64-bit instruction set; par. [0034]: Core-2 204 may support a subset of a full 32-but instruction set; par. [0032]: Core-1 202 may be configured as a high performance core. Core-2 204 may be configured as a medium performance code [low-performance core]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the cores taught by Segelken such that the one or more cores supporting the first ISA are one or more high-performance cores, and wherein the computing device further comprises one or more low-performance cores supporting the second ISA, as taught by Zaarur, as Zaarur would provide the advantage of a means of reducing the energy consumed for certain tasks without comprising performance. (See Zaarur, pars. [0060], [0058]).
Claims 11, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Segelken (US 2014/0317382) in view of Lahteenmaki (US 2015/0261543) in further view of Norton et al. (US 2018/0253315) (art made of record – hereinafter Norton).
As to claim 11, Segelken/Lahteenmaki discloses the method of claim 10 (see rejection of claim 10 above), Segelken further discloses: the binary translation and execut[ing] the instructions based on the first ISA on one or more cores supporting the first ISA (see rejection of claim 1 above) but does not explicitly disclose wherein the first execution service provides a first forked process, wherein the binary translation is performed by the first forked process, wherein the first forked processes executes the instructions based on the first ISA on one or more cores supporting the first ISA.
However, in an analogous art, Norton discloses:
wherein the first execution service provides a first forked process, wherein the task is performed by the first forked process, wherein the first forked processes executes the instructions (e.g., Norton, par. [0030]: each time the launched application attempts to create a process [forked process], the function library assigns the process to the next available set of cores).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first execution service and binary translation task and execution of instructions based on a first ISA on cores supporting that ISA taught by Segelken such that the first execution service provides a first forked process, the task is performed by the first forked process, and the first forked processes executes the instructions, as taught by Norton, as Norton would provide the advantage of a means of performing the different tasks in parallel.
As to claim 13, Segelken/Lahteenmaki discloses the method of claim 12 (see rejection of claim 12 above), and further discloses the second execution service (see rejection of claim 1 above) but does not explicitly disclose wherein the second execution service forks a second child process that executes the application on one or more cores supporting the second ISA.
However, in an analogous art Lahteenmaki discloses
execution on one more cores supporting the second ISA (e.g., Lahteenmaki, par. [0003-0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the execution of the application of Segelken such that it is executed on one more cores supporting the second ISA, as taught by Lahteenmaki, as Lahteenmaki would provide the advantage of a means of execution the application on the most efficient core. (See Lahteenmake, par. [0119]).
Further, in an analogous art, Norton discloses:
wherein the second execution service forks a second child process that executes the application on one or more cores (e.g., Norton, par. [0030]: each time the launched application attempts to create a process [forked process], the function library assigns the process to the next available set of cores).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first execution service and binary translation task and execution of instructions based on a first ISA on cores supporting that ISA taught by Segelken such that the first execution service provides a first forked process, the task is performed by the first forked process, and the first forked processes executes the instructions, as taught by Norton, as Norton would provide the advantage of a means of performing the different tasks in parallel.
As to claim 15 Segelken/Lahteenmaki discloses the method of claim 14 (See rejection of claim 14 above), and discloses one or more cores supporting the first ISA (see rejection of claim 1 above) but does not explicitly dislcose wherein the third execution service forks a third child process that executes the application on one or more cores supporting the first ISA.
However, in an analogous art, Norton discloses
the third execution service forks a third child process that executes the application on one or more cores (e.g., Norton, par. [0030]: each time the launched application attempts to create a process [forked process], the function library assigns the process to the next available set of cores).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first execution service and binary translation task and execution of instructions based on a first ISA on cores supporting that ISA taught by Segelken such that the first execution service provides a first forked process, the task is performed by the first forked process, and the first forked processes executes the instructions, as taught by Norton, as Norton would provide the advantage of a means of performing the different tasks in parallel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TODD AGUILERA whose telephone number is (571)270-5186. The examiner can normally be reached M-F 11AM - 7:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung S Sough can be reached at (571)272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TODD AGUILERA/Primary Examiner, Art Unit 2192
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