Detail Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Status: Please all the replies and correspondence should be addressed to Examiner’s art unit 2629. Receipt is acknowledged of papers submitted on 07-01-2024 under new application; which have been placed of record in the file. Claims 1-14 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07-01-2024, 11-08-2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 9-11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI Hwang Ho et al. (US-20160209462-A1) hereinafter referenced as CHOI et al. in view of Liskov Nathan A et al. (US-4449223-A) hereinafter referenced as Liskov et al. and LEE HAERI et al. (US-20250117303-A1) hereinafter referenced as LEE et al.
Regarding Claim 1, CHOI et al. discloses an eye opening monitor circuit (fig.1) configured to measure information for generating an eye diagram with respect to at least one point of a transmission apparatus or reception apparatus (please see fig.9 apparatus with a transmission apparatus or reception apparatus with EOM, (paras. 3, 5, 19, disclosing An eye opening monitor circuit configured to measure information for generating an eye diagram with respect to at least one point of a transmission apparatus or reception apparatus), the eye opening monitor circuit comprising: a first sampler that samples a data value by comparing an input signal with a first reference voltage (para. 102); a second sampler that samples a data value by comparing the input signal with a second reference voltage (para. 102); a comparison block that compares an output value of the first sampler with an output value of the second sampler to output a comparison result value (para. 102).
However, CHOI et al. fails to discloses change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different.
However, prior art of LIskov et al. discloses change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different (Col. 4, Lines 10-19, and Lines 40-52 disclosing if the error (the difference between the first and second reference voltages) is detected on the comparator the voltage is lowered (or decrease) and if the error is “0” (first sampler and the output value of the second sampler are the same) is detected on the comparator the voltage is high (or increased). Please notice CHOI et al. in View of LIskov et al. explicitly do not disclose or recite control logic block ). Further LIskov et al. discloses wherein the second sampler, the comparison block, and the control logic block form a loop (col. 4, Lines 16-18, figs. 3-4, please also see Col. 5, Lines 34-36, Col. 2, Line 66 to Col. 3, Line 1, disclosing the basic concept of operation is to have a closed loop which adjusts a threshold voltage, +V.sub.th, to approximately the inside of the eye opening at which point the loop is designed to be stable, please notice the labels “first and second” is very arbitrary).
CHOI et al. teaches An integrated circuit having an eye opening monitor (EOM) is with an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit.
CHOI et al. teaches the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages.
LIskov et al teaches change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different as noted above.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, CHOI et al. performs the same function as it does separately of managing process operating, eye-opening monitor(EOM) configured to measure an eye diagram of a predetermined point of the internal circuit.
LIskov et al performs the same function as it does separately of The loop formed with control circuit stabilizes with the range of voltages of the output signals being quantitatively indicative of the eye opening
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify of CHOI et al.to include change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different, as disclosed by LIskov et al thereby stabilizes with the range of voltages of the output signals being quantitatively indicative of the eye opening, as LIskov et al discusses at col. 4, lines 17-19.
Further Regarding Claim 1, CHOI et al. in View of LIskov et al. fails to disclose or recite control logic block.
However, prior art of LEE et al. Discloses control logic block (Figs. 3, 5, paras. 105,1o6), a control command signal ((Figs. 3, 5, paras. 105, 106), and wherein the second sampler, the comparison block, and the control logic block form a loop (please see Figs. 3, 5 paras. 8 , 86-87, 105-106 discloses second sampler, the comparison block, and the control logic block form a loop).
CHOI et al. teaches An integrated circuit having an eye opening monitor (EOM) is with an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit.
CHOI et al. teaches the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages.
LEE et al teaches control logic block, a control command signal and wherein the second sampler, the comparison block, and the control logic block form a loop as noted above.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, CHOI et al. performs the same function as it does separately of managing process operating, eye-opening monitor(EOM) configured to measure an eye diagram of a predetermined point of the internal circuit.
LEE et al performs the same function as it does separately of The loop formed with the second sampler, the comparison block, and the control logic block.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify of CHOI et al.to include control logic block, as disclosed by LEE et al thereby to be able to equalize eye-opening monitor’s result using comparator block and feedback circuit loop, as LEE et al discusses at para. 8.
Regarding Claim 2, CHOI et al. discloses an edge detector that detects an edge at which the output value of the first sampler changes, wherein the edge detector provides an enable signal EN to the comparison block when a change in the output value of the first sampler is detected (paras. 21, 66, 82, please notice the flipflop or RS type latches type storage samples data at rising edge or falling edge of the clock, which obviously makes them edge detector).
Please also see prior art of LIskov et al. disclosure, Col. 4, Lines 22-52.
Regarding Claim 3, LIskov et al. discloses the comparison block comprises an XOR gate (fig. 4, item 108, 114) in which an output terminal of the first sampler is connected to a first input terminal and an output terminal of the second sampler is connected to a second input terminal (please see fig. 4, item 20, 22), wherein the control logic block comprises a counter (fig. 4, item 42) connected to an output terminal of the XOR gate (fig. 4, items 114, 42).
CHOI et al. discloses wherein the XOR gate operates when the enable signal is applied thereto, and wherein the control logic block generates the control command signal according to a digital code value of the counter (please see fig. 5, paras. 66, 78, 82-84)
Regarding Claim 4, CHOI et al. discloses the XOR gate outputs 0 when input values of the first input terminal and the second input terminal are the same ( please see fig. 5, disclosing exclusive OR gate item # 124, please notice the truth table of the exclusive OR gate discloses when both inputs are digital code zero or digital code 1 the output is zero, and when inputs are digital code 0 and 1 output is 1) outputs 1 when they are different (please notice the truth table of the exclusive OR gate discloses when both inputs are digital code zero or digital code 1 the output is zero, and when inputs are digital code 0 and 1 output is 1).
LIskov et al. discloses wherein the counter increases the digital code value when an output value of the XOR gate is 0, wherein the counter decreases the digital code value when the output value of the XOR gate is 1, and wherein the control logic block generates a control command signal to change the second reference voltage when the digital code value reaches a predetermined value (please see fig. 4, Col. 4, Lines 10-19, and Lines 40-52 disclosing if the error (the difference between the first and second reference voltages) is detected on the comparator the voltage is lowered (or decrease) and if the error is “0” (first sampler and the output value of the second sampler are the same) is detected on the comparator the voltage is high (or increased)).
Regarding Claim 5, LEE et al. discloses a reference voltage generator that generates the second reference voltage, wherein the reference voltage generator determines the second reference voltage according to the control command signal (para. 8)
6. The eye opening monitor circuit of claim 3, wherein a ratio of increase and decrease widths of the digital code value is determined according to a target value of an output error rate, wherein when the target value of the output error rate is a first target value, an eye opening of the eye diagram is relatively small, and wherein when the target value of the output error rate is a second target value greater than the first target value, the eye opening of the eye diagram is relatively large.
7. The eye opening monitor circuit of claim 3, wherein the counting information of the counter consists of a digital code value including most significant bit information CNT_bit1 and least significant bit information CNT_bit2, wherein the most significant bit information is fed back to the loop, wherein the most significant bit information is utilized to generate the eye diagram outside the loop, and wherein the least significant bit information is utilized to increase a resolution of the eye diagram outside the loop.
8. The eye opening monitor circuit of claim 3, further comprising: an eye diagram generator that generates an eye diagram using the control command signal, wherein the counting information of the counter consists of a digital code value including most significant bit information and least significant bit information, wherein the most significant bit information is fed back to the loop, wherein the most significant bit information is provided to the eye diagram generator outside the loop and utilized to generate the eye diagram, and wherein the least significant bit information is provided to the eye diagram generator outside the loop and utilized to increase a resolution of the eye diagram.
Regarding Claim 9, CHOI et al. An eye opening monitoring method (paras. 5-6), the method comprising: a step A of outputting, by a first sampler, a first digital value sampled by comparing an input signal with a first reference voltage, and outputting, by a second sampler, a second digital value sampled by comparing the input signal with a second reference voltage (paras. 5-6, 102); a step B of comparing, by a comparison block, the first digital value with the second digital value to output a comparison result value (paras. 5, 102).
However, CHOI et al. fails to discloses change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different.
However, prior art of LIskov et al. discloses change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different (Col. 4, Lines 10-19, and Lines 40-52 disclosing if the error (the difference between the first and second reference voltages) is detected on the comparator the voltage is lowered (or decrease) and if the error is “0” (first sampler and the output value of the second sampler are the same) is detected on the comparator the voltage is high (or increased). Please notice CHOI et al. in View of LIskov et al. explicitly do not disclose or recite control logic block ). Further LIskov et al. discloses wherein the second sampler, the comparison block, and the control logic block form a loop (col. 4, Lines 16-18, figs. 3-4, please also see Col. 5, Lines 34-36, Col. 2, Line 66 to Col. 3, Line 1, disclosing the basic concept of operation is to have a closed loop which adjusts a threshold voltage, +V.sub.th, to approximately the inside of the eye opening at which point the loop is designed to be stable, please notice the labels “first and second” is very arbitrary).
CHOI et al. teaches An integrated circuit having an eye opening monitor (EOM) is with an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit.
CHOI et al. teaches the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages.
LIskov et al teaches change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different as noted above.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, CHOI et al. performs the same function as it does separately of managing process operating, eye-opening monitor(EOM) configured to measure an eye diagram of a predetermined point of the internal circuit.
LIskov et al performs the same function as it does separately of The loop formed with control circuit stabilizes with the range of voltages of the output signals being quantitatively indicative of the eye opening
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify of CHOI et al.to include change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different, as disclosed by LIskov et al thereby stabilizes with the range of voltages of the output signals being quantitatively indicative of the eye opening, as LIskov et al discusses at col. 4, lines 17-19.
Further Regarding Claim 1, CHOI et al. in View of LIskov et al. fails to disclose or recite control logic block.
However, prior art of LEE et al. Discloses control logic block (Figs. 3, 5, paras. 105,1o6), a control command signal ((Figs. 3, 5, paras. 105, 106), and wherein the second sampler, the comparison block, and the control logic block form a loop (please see Figs. 3, 5 paras. 8 , 86-87, 105-106 discloses second sampler, the comparison block, and the control logic block form a loop).
CHOI et al. teaches An integrated circuit having an eye opening monitor (EOM) is with an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit.
CHOI et al. teaches the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages.
LEE et al teaches control logic block, a control command signal and wherein the second sampler, the comparison block, and the control logic block form a loop as noted above.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, CHOI et al. performs the same function as it does separately of managing process operating, eye-opening monitor(EOM) configured to measure an eye diagram of a predetermined point of the internal circuit.
LEE et al performs the same function as it does separately of The loop formed with the second sampler, the comparison block, and the control logic block.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify of CHOI et al.to include control logic block, as disclosed by LEE et al thereby to be able to equalize eye-opening monitor’s result using comparator block and feedback circuit loop, as LEE et al discusses at para. 8.
Regarding Claim 10 CHOI et al. a B1 step of detecting an edge at which the first digital value changes, wherein the step B is performed when the edge is detected in the step B1 (paras. 21, 66, 82, please notice the flipflop or RS type latches type storage samples data at rising edge or falling edge of the clock, which obviously makes them edge detector).
Please also see prior art of LIskov et al. disclosure, Col. 4, Lines 22-52.
Regarding Claim 11 CHOI et al. discloses the XOR gate outputs 0 when input values of the first input terminal and the second input terminal are the same ( please see fig. 5, disclosing exclusive OR gate item # 124, please notice the truth table of the exclusive OR gate discloses when both inputs are digital code zero or digital code 1 the output is zero, and when inputs are digital code 0 and 1 output is 1) outputs 1 when they are different (please notice the truth table of the exclusive OR gate discloses when both inputs are digital code zero or digital code 1 the output is zero, and when inputs are digital code 0 and 1 output is 1).
LIskov et al. discloses wherein the counter increases the digital code value when an output value of the XOR gate is 0, wherein the counter decreases the digital code value when the output value of the XOR gate is 1, and wherein the control logic block generates a control command signal to change the second reference voltage when the digital code value reaches a predetermined value (please see fig. 4, Col. 4, Lines 10-19, and Lines 40-52 disclosing if the error (the difference between the first and second reference voltages) is detected on the comparator the voltage is lowered (or decrease) and if the error is “0” (first sampler and the output value of the second sampler are the same) is detected on the comparator the voltage is high (or increased)).
Regarding Claim 14, CHOI et al. discloses an eye opening monitor circuit (fig.1) configured to measure information for generating an eye diagram with respect to at least one point of a transmission apparatus or reception apparatus (please see fig.9 apparatus with a transmission apparatus or reception apparatus with EOM, (paras. 3, 5, 19, disclosing An eye opening monitor circuit configured to measure information for generating an eye diagram with respect to at least one point of a transmission apparatus or reception apparatus), the eye opening monitor circuit comprising: a first sampler that samples a data value by comparing an input signal with a first reference voltage (para. 102); a second sampler that samples a data value by comparing the input signal with a second reference voltage (para. 102); a comparison block that compares an output value of the first sampler with an output value of the second sampler to output a comparison result value (para. 102).V1 with a first reference voltage Vcm at an edge of a main clock MCLK (please see fig.3, 5, para. 78); a second sampler that samples a data value by comparing the input signal with a second reference voltage V2 at an edge of a sub-clock PCLK (please see Figs. 3, 5, para. 78); a comparison block that compares an output value of the first sampler with an output value of the second sampler to output a comparison result value (paras. 102); and a control logic block that generates a phase control command signal EPo (paras. 97-99) to change a phase of the sub-clock (paras. 97-99), wherein the control logic block generates a phase control command signal to change the sub-clock (paras. 97-99)
CHOI et al. teaches An integrated circuit having an eye opening monitor (EOM) is with an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit.
CHOI et al. teaches the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages.
LIskov et al teaches change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different as noted above.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, CHOI et al. performs the same function as it does separately of managing process operating, eye-opening monitor(EOM) configured to measure an eye diagram of a predetermined point of the internal circuit.
LIskov et al performs the same function as it does separately of The loop formed with control circuit stabilizes with the range of voltages of the output signals being quantitatively indicative of the eye opening
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify of CHOI et al.to include change the second reference voltage, wherein the control logic block generates a control command signal to change the second reference voltage in a direction in which a difference between the first and second reference voltages increases when the output value of the first sampler and the output value of the second sampler are the same, and generates a control command signal to change the second reference voltage in a direction in which the difference between the first and second reference voltages decreases when the output value of the first sampler and the output value of the second sampler are different, as disclosed by LIskov et al thereby stabilizes with the range of voltages of the output signals being quantitatively indicative of the eye opening, as LIskov et al discusses at col. 4, lines 17-19.
Further Regarding Claim 1, CHOI et al. in View of LIskov et al. fails to disclose or recite control logic block.
However, prior art of LEE et al. Discloses control logic block (Figs. 3, 5, paras. 105,1o6), a control command signal ((Figs. 3, 5, paras. 105, 106), and wherein the second sampler, the comparison block, and the control logic block form a loop (please see Figs. 3, 5 paras. 8 , 86-87, 105-106 discloses second sampler, the comparison block, and the control logic block form a loop).
CHOI et al. teaches An integrated circuit having an eye opening monitor (EOM) is with an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit.
CHOI et al. teaches the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages.
LEE et al teaches control logic block, a control command signal and wherein the second sampler, the comparison block, and the control logic block form a loop as noted above.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, CHOI et al. performs the same function as it does separately of managing process operating, eye-opening monitor(EOM) configured to measure an eye diagram of a predetermined point of the internal circuit.
LEE et al performs the same function as it does separately of The loop formed with the second sampler, the comparison block, and the control logic block.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and it would have been obvious to one of ordinary skill in the art to modify of CHOI et al.to include control logic block, as disclosed by LEE et al thereby to be able to equalize eye-opening monitor’s result using comparator block and feedback circuit loop, as LEE et al discusses at para. 8.
Allowable Subject Matter
Claims 6-8 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicant is requested to review the prior art cited on USTO 892’s.
The prior art of YOO Hyunjoon et al. (US 20230139392 A1) disclosure; paras. 27-194, discloses, a storage device includes: a non-volatile memory device including at least one memory die, wherein the at least one memory die includes a plurality of memory regions, each region inputting and outputting a first data signal and a second data signal; and a memory controller including an eye open monitoring (EOM) circuit configured to perform a first EOM operation of generating first EOM information based on the first data signal and a second EOM operation of generating second EOM information based on of the second data signal of at least one of the regions, and configured to compare the second EOM information with the first EOM information, and control the at least one memory die based on a result of the comparison of the first EOM information and the second EOM information. A storage device includes: a non-volatile memory device including at least one memory die, the at least one memory die includes a memory cell array including a plurality of memory regions, a memory interface circuit for providing signals to control the plurality of memory regions through first control pins, and a control logic circuit for controlling the plurality of memory regions based on the signals; and a memory controller including a controller interface circuit for providing the signals to the first control pins through second control pins, an eye open monitoring (EOM) circuit for accumulating a data signal input to or output from the at least one memory die, among the signals, to perform at least one EOM operation, and an EOM memory storing EOM information acquired by the at least one EOM operation, wherein the memory controller controls the at least one memory die, based on the EOM information stored in the EOM memory. A method of controlling a storage device includes: performing a first eye open monitoring (EOM) operation on at least one memory die; storing first EOM information acquired by the first EOM operation in an EOM memory included in a memory controller; performing a second EOM operation by accumulating a signal input to or output from an input/output terminal of the at least one memory die when an operation on the at least one memory die is performed; comparing the first EOM information with second EOM information acquired by the second EOM operation; and determining a state of the at least one memory die, based on a result of the comparison.
The prior art of Chung Younwoong et al. (US 11646917 B1) disclosure; Col. 4, Line 28 to Col. 16, Line 12, disclosing, an equalizing circuit includes a first current summer configured to receive a data signal and a first plurality of feedback signals, a first multiplexer configured to select a first sampling clock signal from a plurality of clock signals using a signal that indicates a mode of operation of the equalizing circuit, and a first slicer configured to sample the output of the first current summer in accordance with timing provided by the first sampling clock signal. The plurality of clock signals may include one or more phase versions of a receive clock signal. At least one of the one or more phase versions of the receive clock signal may be inverted. The plurality of clock signals may include quadrature and in-phase versions of the receive clock signal. The plurality of clock signals may include the receive clock signal and an auxiliary clock signal that has a preconfigured phase shift with respect to the receive clock signal. The first plurality of feedback signals includes a signal generated using an output of the first slicer. The first plurality of feedback signals may include a signal generated by an eye opening monitor. The first plurality of feedback signals may include an offset signal configured to calibrate the equalizing circuit. The equalizing circuit has a second current summer configured to receive the data signal and a second plurality of feedback signals, a second multiplexer configured to select a second sampling clock signal from the plurality of clock signals using the signal that indicates the mode of operation of the equalizing circuit, and a second slicer configured to sample the output of the second current summer in accordance with timing provided by the second sampling clock signal. Each of a plurality of clock inputs of the second multiplexer is coupled to a signal that is an inverse of a clock signal coupled to a corresponding clock input of the first multiplexer such that the second sampling clock signal is inverted with respect to the first sampling clock signal. In some instances, the first plurality of feedback signals includes a signal generated using an output of the second slicer and the second plurality of feedback signals includes a signal generated using an output of the first slicer.
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Any response to this action should be mailed to:
Commissioner of Patents and Trademarks
P.O. Box 1450
Alexandria VA 22313-1450
/Prabodh M Dharia/
Primary Examiner
Art Unit 2629
04-09-2026
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