DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claim of U.S. Patent No. 12,061,818. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of U.S. Patent No. 12,061,818 are directed to “A storage device” and the claims of the Application are directed to “A method of operating a storage” which contain substantially similar limitations; the method claims including limitations directed to storage device components while the storage device claims include limitations directed to the steps of a method performed by a storage device. In comparing the claims, as shown in the comparison table below, one of ordinary skill in the art would recognize that although the claims at issue are not identical, they are not patentably distinct from each other.
Application
Patent
(Claim 1) “A method of operating a storage configured to communicate with a host via a first port and communicate with a reconfigurable logic chip via a second port such that the reconfigurable logic chip is only indirectly connected to the host via the storage, the method comprising:”
(Claim 1) “A storage device comprising: a first port through which the storage device communicates with a first external device; a second port through which the storage device communicates with a second external device;”
(Claim 1) “the first external device and the second external device only indirectly exchange data via the storage device.”
(Claim 1) “a non-volatile memory”
(Claim 3) “a buffer memory;”
(Claim 1) “a non-volatile memory;”
(Claim 1) “a buffer memory;”
(Claim 1) “receiving, via the first port of the storage, a host command from the host, the host command including a data processing request;”
(Claim 1) “receive, via the first port, a command from the first external device”
(Claim 6) “receiving, via the first port of the storage, write data from the host”
(claim 12) “receiving the data from…a buffer memory included in the storage, or a non-volatile memory included in the storage; and encrypting the data received”
(Claim 1) “store, in one or more of the non-volatile memory or the buffer memory, first non-encrypted data received from the first external device via the first port,”
(Claim 1) “reading data stored in a non-volatile memory included in the storage;”
(Claim 1) “read first the non-encrypted data from the buffer memory or the non- volatile memory,”
(Claim 1) “encrypting read data to generate encrypted input data;”
(Claim 1) “encrypt the first non-encrypted data to generate first encrypted data”
(Claim 1) “transmitting, via the second port of the storage, the encrypted input data and a first command to the reconfigurable logic chip, the first command commanding data processing with respect to the encrypted input data; and”
(Claim 1) “transmit, via the second port, the first encrypted data to the second external device,”
(Claim 1) “receiving, via the second port of the storage, encrypted processed data from the reconfigurable logic chip.”
(Claim 1) “receive, via the second port, second encrypted data from the second external device in response to at least the first encrypted data”
(Claim 3) “loading the encrypted processed data into a buffer memory included in the storage”
(Claim 1) “perform a write operation with the second encrypted data, and”
(Claim 10) “transmitting, via the first port of the storage, a response message indicating completion of the data processing data to the host.”
(Claim 1) “transmit, via the first port, a response indicating completion of data processing to the first external device”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10-20 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 10 recites the limitation "the data processing data" in the last line of the claim. There is insufficient antecedent basis for this limitation in the claim because there is no first instance of ‘a data processing data’; therefore, the relationship between identified limitation and the previous limitations regarding “data” is uncertain. Claims 11-16 are rejected due to dependence on claim 10.
Claim 17 recites the limitation "the non-volatile memory" in the last line of the claim. There is insufficient antecedent basis for this limitation in the claim because there is no first instance of ‘a non-volatile memory’. Claims 18-20 are rejected due to dependence on claim 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Khan et al. (US Pub. No. 2017/0091127), hereinafter referred to as Khan, in view of Burger et al. (US Pub. No. 2016/0373416), hereinafter referred to as Burger.
Referring to claim 1, Khan discloses a method of operating a storage (fig. 1, storage device 102; fig. 2, storage 202) configured to communicate with a host (fig. 1, host computing device 101) via a first port (fig. 1, port 165; fig. 2, port 265) and communicate with a reconfigurable logic chip (fig. 2, FPGA 280) via a second port (fig. 1, port 135; fig. 2, port 235) such that the reconfigurable logic chip is only indirectly connected to the host via the storage (fig. 1-2, links 267 and 236 indirectly connected through the storage device), the method comprising: receiving, via the first port of the storage, a host command from the host, the host command including a data processing request (a command may be received from a host computing device through communication port 565 via serial communication link 567 that indicates a workload to be performed on data, [0041]); reading data stored in a non-volatile memory included in the storage (non-volatile memory dies, [0017]; Storage controller 505…facilitate reading, modifying or writing to memory die(s), [0039]); transmitting, via the second port of the storage, data and a first command to the reconfigurable logic chip, the first command commanding data processing with respect to the data; and receiving, via the second port of the storage, processed data from the reconfigurable logic chip (Acceleration logic 580…configured for hardware acceleration of certain storage related tasks or workloads…related tasks may include…compression of data written to memory die(s) 510-1, decompression of compressed data read from memory die(s) 510-1, a filter operation on data stored in memory die(s) 510-1 or a search string associated with data stored in memory die(s)….a workload to be performed on data to be written to or read from memory die(s) 510-1…configure configurable communication port 535 to facilitate communication of the workload via serial communication link 537 and to allow acceleration logic to access memory die(s) 510 to complete at least its offloaded portion of the workload, [0040-0041]).
While Khan teaches encryption of data, the encryption does not appear to apply to the data read and transmitted to the reconfigurable logic chip, therefore Khan does not appear to explicitly disclose encrypting read data to generate encrypted input data and transmitting the encrypted input data and receiving encrypted processed data.
However, Burger discloses encrypting read data to generate encrypted input data and transmitting the encrypted input data and receiving encrypted processed data (customers' data can be stored in encrypted form on, for example, exemplary hard disk 211. hardware accelerator 232 can then retrieve such encrypted data from such a memory space and, internally to the hardware accelerator 232, decrypt such data to perform one or more operations with respect to such data and, if necessary, re-encrypt such data retrieve the re-encrypted data and store it back onto the exemplary hard disk 211; [0046]).
Khan and Burger are analogous art because they are from the same field of endeavor, managing accelerator operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khan and Burger before him or her, to modify the hardware accelerator system of Khan to include the encryption technique of Burger because the encryption would render the information not meaningfully accessible to unauthorized devices or processes.
The suggestion/motivation for doing so would have been to secure the data communications (Burger: [0031]).
Therefore, it would have been obvious to combine Khan and Burger to obtain the invention as specified in the instant claim.
As to claim 2, the combination of Khan in view of Burger discloses transmitting, via the first port, decrypted output data to the host (Khan: a response and/or data generated or provided by an addressed storage device for a command from the host computing device (e.g., originating from a host processor) may move…to be received by the host computing device, [0034]), the decrypted output data being generated by decrypting the encrypted processed data (Burger: hardware accelerator 232 can then retrieve such encrypted data from such a memory space and, internally to the hardware accelerator 232, decrypt such data to perform one or more operations with respect to such data and, if necessary, re-encrypt such data retrieve the re-encrypted data and store it back onto the exemplary hard disk 211; [0046]). The suggestion/motivation to combine remains as indicated above.
As to claim 3, the combination of Khan in view of Burger discloses loading the encrypted processed data (Burger: retrieve such encrypted data…decrypt such data to perform one or more operations with respect to such data and, if necessary, re-encrypt such data; [0046]) into a buffer memory included in the storage (Khan: fig. 2, transfer buffer 250, [0018]), and wherein the transmitting of the decrypted output data includes, generating the decrypted output data by decrypting the encrypted processed data stored in the buffer memory; and transmitting the decrypted output data to the host (Khan: a response and/or data generated or provided by an addressed storage device for a command from the host computing device (e.g., originating from a host processor) may move…to be received by the host computing device, [0034]; decryption of encrypted data read from memory die, [0040]). The suggestion/motivation to combine remains as indicated above.
As to claim 4, the combination of Khan in view of Burger discloses loading the encrypted input data (Burger: retrieve such encrypted data from such a memory space; [0046]) into a buffer memory included in the storage (Khan: fig. 2, transfer buffer 250, [0018]), and wherein the transmitting includes, transmitting the first command to the reconfigurable logic chip, in response to completion of the loading; and transmitting the encrypted input data to the reconfigurable logic chip, in response to a read command received from the reconfigurable logic chip (Khan: a command may be received from a host computing device through communication port 565 via serial communication link 567 that indicates a workload to be performed on data to be written to or read from memory die(s) 510-1…and to allow acceleration logic to access memory die(s) 510 to complete at least its offloaded portion of the workload, [0041]). The suggestion/motivation to combine remains as indicated above.
As to claim 5, while Khan teaches the storage, the reconfigurable logic chip, and a printed circuit board ([0025]), Khan is silent regard which components are mounted on the printed circuit board and therefore does not appear to explicitly disclose the storage and the reconfigurable logic chip are mounted in a same board to form a storage device set.
However, Burger teaches an architecture in which the components “are mounted in a same board” (Depending on the specific physical implementation, one or more of the CPUs 120, the hardware accelerator 150, the system memory 130 and other components of the computing device 100 can be physically co-located, such as on a single chip or silicon die or on a single circuit board, [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khan and Burger before him or her, to modify the storage system of Khan to employ the single circuit board architecture of Suresh because circuit boards are widely used in the field of electronics and capable of mass production and customization.
As to claim 6, the combination of Khan in view of Burger discloses receiving, via the first port of the storage, write data from the host (Khan: a command may be received from a host computing device through communication port 565 via serial communication link 567 that indicates a workload to be performed on data, [0041]); encrypting the write data to generate encrypted write data; and transmitting, via the second port of the storage, the encrypted write data to the reconfigurable logic chip (Burger: data can be stored in encrypted form on, for example, exemplary hard disk 211. hardware accelerator 232 can then retrieve such encrypted data from such a memory space and, internally to the hardware accelerator 232, decrypt such data to perform one or more operations with respect to such data and; [0046]). The suggestion/motivation to combine remains as indicated above.
As to claim 7, the combination of Khan in view of Burger discloses loading the encrypted write data (Burger: retrieve such encrypted data from such a memory space; [0046]) into a buffer memory (Khan: fig. 2, transfer buffer 250, [0018]), and wherein the transmitting of the encrypted write data includes, transmitting a second command to the reconfigurable logic chip, the second command commanding data processing with respect to the encrypted write data, in response to completion of the loading; and transmitting the encrypted write data to the reconfigurable logic chip, in response to a read command received from the reconfigurable logic chip (Khan: a command may be received from a host computing device through communication port 565 via serial communication link 567 that indicates a workload to be performed on data to be written to or read from memory die(s) 510-1…and to allow acceleration logic to access memory die(s) 510 to complete at least its offloaded portion of the workload, [0041]). The suggestion/motivation to combine remains as indicated above.
As to claims 9 and 20, Khan discloses the storage communicates with the host via the first port according to a first interface protocol, and communicates with the reconfigurable logic chip via the second port according to a second interface protocol that is different from the first interface protocol (communication port 165 may be arranged to use a communication protocol described in the PCIe specification…configurable communication port 135 may be arranged to also use…the NVMe communication protocol, [0020-0021]).
Referring to claim 17, Khan discloses a method of operating a storage (fig. 1, storage device 102; fig. 2, storage 202) configured to communicate with a host (fig. 1, host computing device 101) via a first port (fig. 1, port 165; fig. 2, port 265) and communicate with a reconfigurable logic chip (fig. 2, FPGA 280) via a second port such that the reconfigurable logic chip (fig. 1, port 135; fig. 2, port 235) is only indirectly connected to the host via the storage (fig. 1-2, links 267 and 236 indirectly connected through the storage device), the method comprising: receiving, via the first port of the storage, a host command from the host, the host command including a data processing request (a command may be received from a host computing device through communication port 565 via serial communication link 567 that indicates a workload to be performed on data, [0041]); loading the input data into a buffer memory included in the storage (fig. 2, transfer buffer 250, [0018]); transmitting, via the second port of the storage, the input data and a command to the reconfigurable logic chip, the command commanding data processing with respect to the input data; receiving, via the second port of the storage, output data from the reconfigurable logic chip (Acceleration logic 580…configured for hardware acceleration of certain storage related tasks or workloads…related tasks may include…compression of data written to memory die(s) 510-1, decompression of compressed data read from memory die(s) 510-1, a filter operation on data stored in memory die(s) 510-1 or a search string associated with data stored in memory die(s)….a workload to be performed on data to be written to or read from memory die(s) 510-1…configure configurable communication port 535 to facilitate communication of the workload via serial communication link 537 and to allow acceleration logic to access memory die(s) 510 to complete at least its offloaded portion of the workload, [0040-0041]); and writing the output data into the buffer memory (fig. 2, transfer buffer 250, [0018]) or the non-volatile memory (non-volatile memory dies, [0017]; Storage controller 505…facilitate reading, modifying or writing to memory die(s), [0039]).
While Khan teaches encrypting data to generate encrypted input data by an encryption/decryption module (encryption of data written to memory die(s) 510-1, [0040]), Khan does not appear to explicitly disclose the encryption “included in the storage” such that encrypted input data is loaded and transmitted and output data to be received are encrypted.
However, Burger discloses a local encryption technique such that encryption is applied to data to be loaded, transmitted, and recevied (customers' data can be stored in encrypted form on, for example, exemplary hard disk 211. hardware accelerator 232 can then retrieve such encrypted data from such a memory space and, internally to the hardware accelerator 232, decrypt such data to perform one or more operations with respect to such data and, if necessary, re-encrypt such data retrieve the re-encrypted data and store it back onto the exemplary hard disk 211; [0046]).
Khan and Burger are analogous art because they are from the same field of endeavor, managing accelerator operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khan and Burger before him or her, to modify the hardware accelerator system of Khan to include the encryption technique of Burger because the encryption would render the information not meaningfully accessible to unauthorized devices or processes.
The suggestion/motivation for doing so would have been to secure the data communications (Burger: [0031]).
Therefore, it would have been obvious to combine Khan and Burger to obtain the invention as specified in the instant claim.
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Burger, as applied to claims 1-7, 9, 17, and 20 above, further in view of Suresh et al. (US Pub. No. 2018/0062829), hereinafter referred to as Suresh,
As claims 8 and 19, the combination of Khan in view of Burger does not appear to explicitly disclose the reconfigurable logic chip is configured to change from a first accelerator to a second accelerator during an operation of the storage.
However, Suresh discloses a reconfigurable logic chip (logic device...may be a field-programmable gate array (FPGA), [0032]) is configured to change from a first accelerator to a second accelerator during an operation of the storage (hardware accelerator that can be reconfigured to support AES and/or SMS4 encryption and/or decryption, [0023]).
Khan, Burger, and Suresh are analogous art because they are from the same field of endeavor, offloading operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khan, Burger, and Suresh before him or her, to modify the storage system of Khan in view of Burger to include the accelerator architecture of Suresh because the FPGA accelerator architecture of Suresh would provide flexible operation acceleration.
The suggestion/motivation for doing so would have been to accelerate secure data tasks and provide support for multiple encrypt/decrypt schemes (Suresh: [0023]).
Therefore, it would have been obvious to combine Khan, Burger, and Suresh to obtain the invention as specified in the instant claim.
Claims 10, 12-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Burger, further in view of Sheffield et al. (US Pub. No. 2014/0359216), hereinafter referred to as Sheffield.
Referring to claim 10, Khan discloses a method of operating a storage (fig. 1, storage device 102; fig. 2, storage 202) configured to communicate with a host (fig. 1, host computing device 101) via a first port (fig. 1, port 165; fig. 2, port 265) and communicate with a reconfigurable logic chip (fig. 2, FPGA 280) via a second port (fig. 1, port 135; fig. 2, port 235) such that the reconfigurable logic chip is only indirectly connected to the host via the storage (fig. 1-2, links 267 and 236 indirectly connected through the storage device), the method comprising: receiving, via the first port of the storage, a host command from the host, the host command including a data processing request (a command may be received from a host computing device through communication port 565 via serial communication link 567 that indicates a workload to be performed on data, [0041]); generating encrypted input data by encrypting data (encryption of data written to memory die(s) 510-1, [0040]); transmitting, via the second port of the storage, the data and a command to the reconfigurable logic chip, the command commanding data processing with respect to the data; receiving, via the second port of the storage, output data from the reconfigurable logic chip (Acceleration logic 580…configured for hardware acceleration of certain storage related tasks or workloads…related tasks may include…compression of data written to memory die(s) 510-1, decompression of compressed data read from memory die(s) 510-1, a filter operation on data stored in memory die(s) 510-1 or a search string associated with data stored in memory die(s)….a workload to be performed on data to be written to or read from memory die(s) 510-1…configure configurable communication port 535 to facilitate communication of the workload via serial communication link 537 and to allow acceleration logic to access memory die(s) 510 to complete at least its offloaded portion of the workload, [0040-0041]); performing a write operation with respect to the output data (writing to memory die(s) 110-1 to 110-n responsive to commands received from host computing device, [0018]; acceleration logic to access memory die(s) 510 to complete at least its offloaded portion of the workload, [0041]).
While Khan teaches encryption of data, the encryption does not appear to apply to the data transmitted to the reconfigurable logic chip, therefore Khan does not appear to explicitly disclose transmitting the encrypted input data, receiving encrypted output data, and performing a write operation with respect to the encrypted output data. Additionally, while Khan teaches communicating, via the first port of the storage, data to the host, Khan does not appear to explicitly disclose transmitting a response message indicating completion of the data processing data to the host.
However, Burger discloses transmitting the encrypted input data, receiving encrypted output data, and performing a write operation with respect to the encrypted output data (data can be stored in encrypted form on, for example, exemplary hard disk 211. hardware accelerator 232 can then retrieve such encrypted data from such a memory space and, internally to the hardware accelerator 232, decrypt such data to perform one or more operations with respect to such data and, if necessary, re-encrypt such data retrieve the re-encrypted data; [0046]).
Furthermore, Sheffield discloses transmitting a response message indicating completion of the data processing data to the host (accelerator 114 routes the completion status…return completion status to the host, [0014]).
Khan, Burger, and Sheffield are analogous art because they are from the same field of endeavor, managing accelerator operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khan, Burger, and Sheffield before him or her, to modify the hardware accelerator system of Khan to include the encryption technique of Burger and the status messaging of Sheffield because the encryption would render the information not meaningfully accessible to unauthorized devices or processes and the status messaging would inform the host of completion of operations.
The suggestion/motivation for doing so would have been to secure the data communications (Burger: [0031]) and confirm completion of operations (Sheffield: [0006], [0054]).
Therefore, it would have been obvious to combine Khan, Burger, and Sheffield to obtain the invention as specified in the instant claim.
As to claim 12, Khan discloses the generating includes: receiving the data from the host, a buffer memory included in the storage, or a non-volatile memory included in the storage; and encrypting the data received from the host, the buffer memory, or the non-volatile memory (encryption of data written to memory die(s) 510-1…a command may be received from a host computing device through communication port 565 via serial communication link 567 that indicates a workload to be performed on data, [0040-0041]).
As to claim 13, Khan discloses the performing of the write operation includes: writing the encrypted output data into a buffer memory included in the storage or a non-volatile memory included in the storage (writing to memory die(s) 110-1 to 110-n responsive to commands received from host computing device, [0018]; acceleration logic to access memory die(s) 510 to complete at least its offloaded portion of the workload, [0041]).
As to claim 14, the combination of Khan, Burger, and Sheffield discloses the performing of the write operation includes: decrypting the encrypted output data; and performing the writing operation with respect to the decrypted output data (Burger: data can be stored in encrypted form on, for example, exemplary hard disk 211. hardware accelerator 232 can then retrieve such encrypted data from such a memory space and, internally to the hardware accelerator 232, decrypt such data to perform one or more operations with respect to such data and, if necessary, re-encrypt such data retrieve the re-encrypted data; [0046]). The suggestion/motivation to combine remains as indicated above.
As to claim 16, Khan discloses the storage communicates with the host via the first port according to a first interface protocol, and communicates with the reconfigurable logic chip via the second port according to a second interface protocol that is different from the first interface protocol (communication port 165 may be arranged to use a communication protocol described in the PCIe specification…configurable communication port 135 may be arranged to also use…the NVMe communication protocol, [0020-0021]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Khan, Burger, and Sheffield, as applied to claim 10, 12-14, and 16 above, further in view of Xu et al. (US Pub. No. 2020/0234411), hereinafter referred to as Xu.
As to claim 11, while Khan discloses generating the encrypted input data, Khan does not appear to explicitly disclose the encrypted data is “an image file that is a target of an image recognition”.
However, Xu discloses the first accelerator is configured to perform a machine learning algorithm, which includes processing of “an image file that is a target of an image recognition” (image recognition applications because of its feature detection abilities, [0005]; Hardware acceleration for the machine learning application, [0141]).
Khan, Burger, Sheffield, and Xu are analogous art because they are from the same field of endeavor, offloading operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khan, Burger, Sheffield, and Xu before him or her, to modify the hardware accelerator of Drysdale to implement machine learning as taught by Xu to adapt and train the acceleration to specific tasks.
The suggestion/motivation for doing so would have been to facilitate the training of specific tasks (Xu: [0004]).
Therefore, it would have been obvious to combine Khan, Burger, Sheffield, and Xu to obtain the invention as specified in the instant claim.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Khan, Burger, and Sheffield, as applied to claim 10, 12-14, and 16 above, further in view of Suresh.
As claim 15, the combination of Khan in view of Burger does not appear to explicitly disclose the reconfigurable logic chip is configured to change from a first accelerator to a second accelerator during an operation of the storage.
However, Suresh discloses a reconfigurable logic chip (logic device...may be a field-programmable gate array (FPGA), [0032]) is configured to change from a first accelerator to a second accelerator during an operation of the storage (hardware accelerator that can be reconfigured to support AES and/or SMS4 encryption and/or decryption, [0023]).
Khan, Burger, Sheffield, and Suresh are analogous art because they are from the same field of endeavor, offloading operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khan, Burger, Sheffield, and Suresh before him or her, to modify the storage system of Khan to include the accelerator architecture of Suresh because the FPGA accelerator architecture of Suresh would provide flexible operation acceleration.
The suggestion/motivation for doing so would have been to accelerate secure data tasks and provide support for multiple encrypt/decrypt schemes (Suresh: [0023]).
Therefore, it would have been obvious to combine Khan, Burger, Sheffield, and Suresh to obtain the invention as specified in the instant claim.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Burger, as applied to claim 17 above, further in view of Sheffield.
As to claim 18, while Khan teaches communicating, via the first port of the storage, data to the host, Khan does not appear to explicitly disclose transmitting a response message indicating completion of the data processing data to the host.
However, Sheffield discloses transmitting a response message indicating completion of the data processing data to the host (accelerator 114 routes the completion status…return completion status to the host, [0014]).
Khan, Burger, and Sheffield are analogous art because they are from the same field of endeavor, managing accelerator operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khan, Burger, and Sheffield before him or her, to modify the hardware accelerator system of Khan to include the status messaging of Sheffield because the status messaging would inform the host of completion of operations.
The suggestion/motivation for doing so would have been to confirm completion of operations (Sheffield: [0006], [0054]).
Therefore, it would have been obvious to combine Khan, Burger, and Sheffield to obtain the invention as specified in the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2020/0210597 of Bates et al. is pertinent to data encryption in storage systems including hardware accelerators.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Center. For more information about the Patent Center, see https://patentcenter.uspto.gov/. Should you have questions on access to the Patent Center system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T OBERLY/ Primary Examiner, Art Unit 2184