Last updated: October 25, 2026

Application No. 18/760,451

POWER SEMICONDUCTOR INTEGRATED UNIT AND POWER CONVERTER CIRCUIT STRUCTURE THEREOF, AND LOOP STRUCTURE WITH INTEGRATED UNITS CONNECTED IN PARALLEL

Non-Final OA

Filed

Jul 01, 2024

Priority

Jun 29, 2023 — CN 202310787722.5 +1 more

Examiner

CHIU, TSZ K

Art Unit

2898

Tech Center

2800 — Semiconductors & Electrical Systems

Assignee

Cambridge Integration Ltd.

OA Round

1 (Non-Final)

Interview Optional

— +11.0% interview lift. Interview lift (+11.0%) is below the 15.0% threshold. A written response is recommended.

Based on 691 resolved cases, 2023–2026

Examiner Intelligence

CHIU, TSZ K View full profile →

Grants 79% — above average

Career Allowance Rate

548 granted / 691 resolved

+11.3% vs TC avg

Moderate +11% lift

Without

With

+11.0%

Interview Lift

resolved cases with interview

Typical timeline

3y 4m

Avg Prosecution

30 currently pending

Career history

736

Total Applications

across all art units

Statute-Specific Performance

§101

0.7%

-39.3% vs TC avg

§103

49.6%

+9.6% vs TC avg

§102

33.8%

-6.2% vs TC avg

§112

8.8%

-31.2% vs TC avg

Black line = Tech Center average estimate • Based on career data from 691 resolved cases

Prosecution Timeline

Jul 01, 2024

Application Filed

Aug 20, 2026

Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

17/746,990

Patent 12757780

SEMICONDUCTOR PACKAGE WITH STACKED DIES AND THERMAL SUBSTRATE ENCAPSULATION

4y 4m to grant Granted Oct 06, 2026

17/812,616

Patent 12757703

STAIRCASE STRUCTURES FOR ACCESSING THREE-DIMENSIONAL MEMORY ARRAYS

4y 2m to grant Granted Oct 06, 2026

17/861,960

Patent 12733220

NANOSHEET TRANSISTOR DEVICE WITH BOTTOM ISOLATION

4y 2m to grant Granted Sep 08, 2026

17/591,704

Patent 12708027

MULTILAYER ENCAPSULATION FOR HUMIDITY ROBUSTNESS AND HIGHLY ACCELERATED STRESS TESTS AND RELATED FABRICATION METHODS

4y 6m to grant Granted Aug 11, 2026

17/954,164

Patent 12707636

MANUFACTURING METHOD OF A SEMICONDUCTOR MEMORY DEVICE

3y 10m to grant Granted Aug 11, 2026

Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.

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Prosecution Projections

1-2

Expected OA Rounds

79%

Grant Probability

90%

With Interview (+11.0%)

3y 4m (~1y 0m remaining)

Median Time to Grant

Low

PTA Risk

Based on 691 resolved cases by this examiner. Grant probability derived from career allowance rate.