Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 of U.S. Application 18/760,570 filed on July 01, 2024 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/06/2024 has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (USPGPub 20230142493) in view of Lee et al (USPGPub 20210327476).
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Prior Art: Kim
Regarding claim 1, Kim discloses an apparatus (figs 1-13), comprising: a first external pin (such as 150) communicatively coupled to a first circuit (first output driver as disclosed in claim 8); a second external pin (not fully shown but disclose in claim 14 as second signal pin) communicatively coupled to a second circuit (second output driver); and a calibration circuit (220)configured to: generate a first calibration signal (from 220) comprising a first ZQ code (CODE1) for calibrating a first termination resistance of the first circuit (par 47 & 49 discloses providing termination resistance of pin 240); and generate a second calibration signal comprising (from 220) a second ZQ code (CODE2), , and wherein the second calibration signal is for calibrating a second termination resistance of the second circuit (claim 14 discloses for a second termination resistance of the second signal pin). Kim does not fully disclose wherein the second ZQ code is generated via a logic circuit by using the first ZQ code.
However, Lee discloses wherein the second ZQ code is generated via a logic circuit (from a latch command) by using the first ZQ code (claim 2 discloses using ZQ calibration that response from the first ZQ to produce second ZQ from a latch command).It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Lee in order to compare different signals to accurately calibrate memory devices.
Regarding claim 2, Kim discloses wherein the first circuit comprises one of a pull-up driver (410) and a pull-down driver (420) having the first termination resistance and the other of the pull-up driver and the pull-down driver having a third termination resistance, and wherein the calibration circuit is configured to generate a third calibration signal comprising a third ZQ code for calibrating the third termination resistance (pars 46 and 48 discloses pull up and pull down using CODE3 may be generated by performing the pull-up calibration and fourth code CODE4 may be performed the pull-down calibration).
Regarding claim 3, Kim discloses wherein the second circuit comprises a termination driver having the second termination resistance (claim 14 discloses a second ZQ calibration circuit connected to the ZQ pin and configured to perform calibration using external resistor and control second termination resistor).
Regarding claim 4, Kim discloses wherein the calibration circuit is in a memory chip and configured to generate the first calibration signal based on a precision resistor arranged outside of the memory chip (par 91 discloses DRAM or Flash and an external resistor connected to the ZQ pin and perform ZQ calibration using external resistor).
Regarding claim 5, Kim discloses wherein the logic circuit comprises adder/subtractor circuitry (par 89 discloses addition and subtraction operations. Therefore, the logic circuitry would incorporate these operations).
Regarding claim 6, Kim does not fully disclose wherein the first ZQ code is different from the second ZQ code by an integer number.
However, Lee discloses wherein the first ZQ code is different from the second ZQ code by an integer number (claim 2 discloses ZQUF when the second ZQ code is different than the first ZQ code). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Lee in order to use updating values based off memory.
Regarding claim 7, Kim does not fully disclose wherein the calibration circuit is configured to generate the second calibration signal based on characteristics associated with the second circuit.
However, Lee discloses wherein the calibration circuit is configured to generate the second calibration signal based on characteristics associated with the second circuit (claim 14 discloses second ZQ calibration circuit connected to ZQ pin to perform calibration). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Lee in order to compare different signals to accurately calibrate memory devices.
Regarding claim 8, Kim does not fully disclose wherein the calibration circuit is configured to generate the first calibration signal and the second calibration signal within a threshold time period.
However, Lee discloses the calibration circuit is configured to generate the first calibration signal and the second calibration signal within a threshold time period (claim 9 discloses the memory device receiving the second ZQ latch command after a predetermined time command). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Lee in order to determine calibration of the memory controller (Lee par 58).
Regarding claim 9, Kim discloses a method, comprising: generating a first calibration signal (from 220) comprising a first ZQ code (CODE1) for calibrating a first termination resistance of a first circuit (first output driver as disclosed in claim 8) communicatively coupled to a first external pin (such as 150); and generating a second calibration signal (from 220) comprising a second ZQ code (CODE2), wherein the second ZQ code is generated via a logic circuit by using the first ZQ code, and wherein the second calibration signal (from 220) is for calibrating a second termination resistance (par 47 & 49 discloses providing termination resistance of pin 240) of a second circuit (second output driver) communicatively coupled to a second external pin (not fully shown but disclose in claim 14 as second signal pin). Kim does not fully disclose wherein the second ZQ code is generated via a logic circuit by using the first ZQ code.
However, Lee discloses wherein the second ZQ code is generated via a logic circuit (from a latch command) by using the first ZQ code (claim 2 discloses using ZQ calibration that response from the first ZQ to produce second ZQ from a latch command). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Lee in order to compare different signals to accurately calibrate memory devices.
Regarding claim 10, Kim discloses comprising: generating a third calibration signal comprising a third ZQ code (CODE3) for calibrating a third termination resistance, wherein the first circuit comprises one of a pull-up driver (410) and a pull-down driver (420) having the first termination resistance and the other of the pull-up driver and the pull-down driver having the third termination resistance.
Regarding claim 11, Kim discloses comprising: wherein the second circuit comprises a termination driver having the second termination resistance (claim 14 discloses a second ZQ calibration circuit connected to the ZQ pin and configured to perform calibration using external resistor and control second termination resistor).
Regarding claim 12, Kim discloses comprising: wherein generating the first calibration signal comprises generating the first calibration signal based on a precision resistor (par 91 discloses DRAM or Flash and an external resistor connected to the ZQ pin and perform ZQ calibration using external resistor).
Regarding claim 13, Kim discloses comprising: wherein the logic circuit comprises adder/subtractor circuitry (par 89 discloses addition and subtraction operations. Therefore, the logic circuitry would incorporate these operations).
Regarding claim 14, Kim does not fully disclose wherein the first ZQ code is different from the second ZQ code by an integer number.
However, Lee discloses wherein the first ZQ code is different from the second ZQ code by an integer number (claim 2 discloses ZQUF when the second ZQ code is different than the first ZQ code). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Lee in order to use updating values based off memory.
Regarding claim 15, Kim discloses comprising: wherein generating the second calibration signal comprises generating the second calibration signal based on characteristics associated with the second circuit (claim 14 discloses second ZQ calibration circuit connected to ZQ pin to perform calibration). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Lee in order to compare different signals to accurately calibrate memory devices.
Regarding claim 16, Kim discloses an apparatus (figs 1-13), comprising: a first external pin (such as 150); a second external pin (not fully shown but disclose in claim 14 as second signal pin); a first circuit (first output driver as disclosed in claim 8) coupled to the first external pin, the first circuit including a pull-up driver (410) and a pull-down driver (420); a termination driver coupled between the second external pin and a voltage node (VDDQ); and a ZQ circuit (220) configured to generate a first calibration signal comprising a first ZQ code (CODE1) for calibrating a first termination resistance of the pull-up driver of the first circuit, a second calibration signal comprising a second ZQ code (CODE2) for calibrating a second termination resistance of the pull-down driver of the first circuit (par 47 & 49 discloses providing termination resistance of pin 240) and a third calibration signal comprising a third ZQ code (CODE3) for calibrating a third termination resistance of the termination driver(pars 46 and 48 discloses pull up and pull down using CODE3 may be generated by performing the pull-up calibration and fourth code CODE4 may be performed the pull-down calibration), the third ZQ code being generated based on one of the first ZQ code and the second ZQ code (claim 16 discloses ZQ which is a second calibration circuit is a replica from the first. Therefore, CODE3 is based on at least the first CODE1).
Regarding claim 17, Kim discloses comprising: wherein the voltage node is supplied with a lower voltage and the third ZQ code is generated based on the second ZQ code (par 43 discloses being about .3V-.5V and par 72 discloses the ZQ and vef voltage can be adjusted based on counter 914. The counter 914 may be provided as CODE3 of 915. Therefore, the CODE3 may be based on the second ZQ code).
Regarding claim 18, Kim discloses comprising: wherein the voltage node is supplied with an upper voltage and the third ZQ code is generated based on the first ZQ code (par 43 discloses being about .3V-.5V and fig 7 discloses being a replica device. Therefore, the third ZQ is based on the first ZQ code).
Regarding claim 19, Kim discloses comprising: wherein the third ZQ code is generated by a logic circuit comprising adder/subtractor circuitry (par 89 discloses addition and subtraction operations. Therefore, the logic circuitry would incorporate these operations).
Regarding claim 20, Kim discloses comprising: wherein the logic circuit is configured to generate the third ZQ code based on characteristics associated with the termination driver (shown in fig 7 as the control circuitry generates CODE3).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al (USPGPub 20230326497): discloses calibration circuit with code generator.
Kang et al (USPGPb 20210099172): discloses semiconductor with calibration circuit and Zcodes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOMINIC E HAWKINS whose telephone number is (571)272-2647. The examiner can normally be reached Monday-Friday 7:30am-5:00pm EST.
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/DOMINIC E HAWKINS/Primary Examiner, Art Unit 2858